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-rw-r--r--src/compiler/codegen/MethodBitcode.cc23
-rw-r--r--src/compiler/codegen/MethodCodegenDriver.cc2
-rw-r--r--src/compiler/codegen/Ralloc.h6
-rw-r--r--src/compiler/codegen/RallocUtil.cc2
-rw-r--r--src/compiler/codegen/arm/Assemble.cc2
-rw-r--r--src/compiler/codegen/arm/Thumb2/Factory.cc4
-rw-r--r--src/compiler/codegen/mips/Assemble.cc2
-rw-r--r--src/compiler/codegen/mips/Codegen.h7
-rw-r--r--src/compiler/codegen/x86/X86/Factory.cc4
9 files changed, 24 insertions, 28 deletions
diff --git a/src/compiler/codegen/MethodBitcode.cc b/src/compiler/codegen/MethodBitcode.cc
index 66823c2313..ad9b020e9e 100644
--- a/src/compiler/codegen/MethodBitcode.cc
+++ b/src/compiler/codegen/MethodBitcode.cc
@@ -29,7 +29,7 @@
#include <llvm/Support/Casting.h>
#include <llvm/Support/InstIterator.h>
-const char* labelFormat = "L0x%x_%d";
+static const char* kLabelFormat = "L0x%x_%d";
namespace art {
extern const RegLocation badLoc;
@@ -345,7 +345,7 @@ void setShadowFrameEntry(CompilationUnit* cUnit, llvm::Value* newVal)
break;
}
}
- DCHECK(index != -1) << "Corrupt shadowMap";
+ DCHECK_NE(index, -1) << "Corrupt shadowMap";
greenland::IntrinsicHelper::IntrinsicId id =
greenland::IntrinsicHelper::SetShadowFrameEntry;
llvm::Function* func = cUnit->intrinsic_helper->GetIntrinsicFunction(id);
@@ -1341,7 +1341,7 @@ bool createLLVMBasicBlock(CompilationUnit* cUnit, BasicBlock* bb)
bool entryBlock = (bb->blockType == kEntryBlock);
llvm::BasicBlock* llvmBB =
llvm::BasicBlock::Create(*cUnit->context, entryBlock ? "entry" :
- StringPrintf(labelFormat, offset, bb->id),
+ StringPrintf(kLabelFormat, offset, bb->id),
cUnit->func);
if (entryBlock) {
cUnit->entryBB = llvmBB;
@@ -1443,17 +1443,16 @@ RegLocation getLoc(CompilationUnit* cUnit, llvm::Value* val) {
DCHECK(val != NULL);
SafeMap<llvm::Value*, RegLocation>::iterator it = cUnit->locMap.find(val);
if (it == cUnit->locMap.end()) {
- const char* valName = val->getName().str().c_str();
- DCHECK(valName != NULL);
- DCHECK(strlen(valName) > 0);
+ std::string valName(val->getName().str());
+ DCHECK(!valName.empty());
if (valName[0] == 'v') {
int baseSReg = INVALID_SREG;
- sscanf(valName, "v%d_", &baseSReg);
+ sscanf(valName.c_str(), "v%d_", &baseSReg);
res = cUnit->regLocation[baseSReg];
cUnit->locMap.Put(val, res);
} else {
UNIMPLEMENTED(WARNING) << "Need to handle llvm temps";
- DCHECK(valName[0] == 't');
+ DCHECK_EQ(valName[0], 't');
}
} else {
res = it->second;
@@ -1628,7 +1627,7 @@ void cvtCall(CompilationUnit* cUnit, llvm::CallInst* callInst,
void cvtCopy(CompilationUnit* cUnit, llvm::CallInst* callInst)
{
- DCHECK(callInst->getNumArgOperands() == 1);
+ DCHECK_EQ(callInst->getNumArgOperands(), 1);
RegLocation rlSrc = getLoc(cUnit, callInst->getArgOperand(0));
RegLocation rlDest = getLoc(cUnit, callInst);
if (rlSrc.wide) {
@@ -1641,7 +1640,7 @@ void cvtCopy(CompilationUnit* cUnit, llvm::CallInst* callInst)
// Note: Immediate arg is a ConstantInt regardless of result type
void cvtConst(CompilationUnit* cUnit, llvm::CallInst* callInst)
{
- DCHECK(callInst->getNumArgOperands() == 1);
+ DCHECK_EQ(callInst->getNumArgOperands(), 1);
llvm::ConstantInt* src =
llvm::dyn_cast<llvm::ConstantInt>(callInst->getArgOperand(0));
uint64_t immval = src->getZExtValue();
@@ -1659,7 +1658,7 @@ void cvtConst(CompilationUnit* cUnit, llvm::CallInst* callInst)
void cvtConstString(CompilationUnit* cUnit, llvm::CallInst* callInst)
{
- DCHECK(callInst->getNumArgOperands() == 1);
+ DCHECK_EQ(callInst->getNumArgOperands(), 1);
llvm::ConstantInt* stringIdxVal =
llvm::dyn_cast<llvm::ConstantInt>(callInst->getArgOperand(0));
uint32_t stringIdx = stringIdxVal->getZExtValue();
@@ -1733,7 +1732,7 @@ bool methodBitcodeBlockCodeGen(CompilationUnit* cUnit, llvm::BasicBlock* bb)
if (!isEntry) {
const char* blockName = bb->getName().str().c_str();
int dummy;
- sscanf(blockName, labelFormat, &blockLabel->operands[0], &dummy);
+ sscanf(blockName, kLabelFormat, &blockLabel->operands[0], &dummy);
}
// Set the label kind
blockLabel->opcode = kPseudoNormalBlockLabel;
diff --git a/src/compiler/codegen/MethodCodegenDriver.cc b/src/compiler/codegen/MethodCodegenDriver.cc
index 7898ddb7be..a07e569394 100644
--- a/src/compiler/codegen/MethodCodegenDriver.cc
+++ b/src/compiler/codegen/MethodCodegenDriver.cc
@@ -1020,7 +1020,7 @@ void oatSpecialMIR2LIR(CompilationUnit* cUnit, SpecialCaseHandler specialCase)
return;
}
DCHECK_EQ(bb->startOffset, 0);
- DCHECK(bb->firstMIRInsn != 0);
+ DCHECK(bb->firstMIRInsn != NULL);
/* Get the first instruction */
MIR* mir = bb->firstMIRInsn;
diff --git a/src/compiler/codegen/Ralloc.h b/src/compiler/codegen/Ralloc.h
index ec47e22963..d1518e8e3f 100644
--- a/src/compiler/codegen/Ralloc.h
+++ b/src/compiler/codegen/Ralloc.h
@@ -50,14 +50,12 @@ inline int oatSRegHi(int lowSreg) {
}
-inline bool oatLiveOut(CompilationUnit* cUnit, int sReg)
-{
+inline bool oatLiveOut(CompilationUnit* cUnit, int sReg) {
//For now.
return true;
}
-inline int oatSSASrc(MIR* mir, int num)
-{
+inline int oatSSASrc(MIR* mir, int num) {
DCHECK_GT(mir->ssaRep->numUses, num);
return mir->ssaRep->uses[num];
}
diff --git a/src/compiler/codegen/RallocUtil.cc b/src/compiler/codegen/RallocUtil.cc
index 074fd26ca0..affb545aea 100644
--- a/src/compiler/codegen/RallocUtil.cc
+++ b/src/compiler/codegen/RallocUtil.cc
@@ -1003,7 +1003,7 @@ extern RegLocation oatGetRawSrc(CompilationUnit* cUnit, MIR* mir, int num)
}
extern RegLocation oatGetRawDest(CompilationUnit* cUnit, MIR* mir)
{
- DCHECK(mir->ssaRep->numDefs > 0);
+ DCHECK_GT(mir->ssaRep->numDefs, 0);
RegLocation res = cUnit->regLocation[mir->ssaRep->defs[0]];
DCHECK(!res.wide || mir->ssaRep->numDefs == 2);
return res;
diff --git a/src/compiler/codegen/arm/Assemble.cc b/src/compiler/codegen/arm/Assemble.cc
index 86517fa0dd..ede3f6152c 100644
--- a/src/compiler/codegen/arm/Assemble.cc
+++ b/src/compiler/codegen/arm/Assemble.cc
@@ -1305,7 +1305,7 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit* cUnit,
break;
case kFmtDfp: {
DCHECK(DOUBLEREG(operand));
- DCHECK((operand & 0x1) == 0);
+ DCHECK_EQ((operand & 0x1), 0U);
int regName = (operand & FP_REG_MASK) >> 1;
/* Snag the 1-bit slice and position it */
value = ((regName & 0x10) >> 4) << encoder->fieldLoc[i].end;
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index c9dbe62cdf..c6cb220107 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -660,7 +660,7 @@ LIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rDest,
} else {
DCHECK(DOUBLEREG(rDest));
DCHECK((size == kLong) || (size == kDouble));
- DCHECK((rDest & 0x1) == 0);
+ DCHECK_EQ((rDest & 0x1), 0);
opcode = kThumb2Vldrd;
size = kDouble;
}
@@ -725,7 +725,7 @@ LIR* storeBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rSrc,
} else {
DCHECK(DOUBLEREG(rSrc));
DCHECK((size == kLong) || (size == kDouble));
- DCHECK((rSrc & 0x1) == 0);
+ DCHECK_EQ((rSrc & 0x1), 0);
opcode = kThumb2Vstrd;
size = kDouble;
}
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 39ad36b4ad..25e13d7d8f 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -674,7 +674,7 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,
break;
case kFmtDfp: {
DCHECK(DOUBLEREG(operand));
- DCHECK((operand & 0x1) == 0);
+ DCHECK_EQ((operand & 0x1), 0U);
value = ((operand & FP_REG_MASK) << encoder->fieldLoc[i].start) &
((1 << (encoder->fieldLoc[i].end + 1)) - 1);
bits |= value;
diff --git a/src/compiler/codegen/mips/Codegen.h b/src/compiler/codegen/mips/Codegen.h
index 6add82ab0d..106c030b70 100644
--- a/src/compiler/codegen/mips/Codegen.h
+++ b/src/compiler/codegen/mips/Codegen.h
@@ -67,12 +67,11 @@ void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
* Must use a core register for data types narrower than word (due
* to possible unaligned load/store.
*/
-inline RegisterClass oatRegClassBySize(OpSize size)
-{
+inline RegisterClass oatRegClassBySize(OpSize size) {
return (size == kUnsignedHalf ||
size == kSignedHalf ||
size == kUnsignedByte ||
- size == kSignedByte ) ? kCoreReg : kAnyReg;
+ size == kSignedByte) ? kCoreReg : kAnyReg;
}
/*
@@ -84,7 +83,7 @@ inline RegisterClass oatRegClassBySize(OpSize size)
*/
#if __BYTE_ORDER == __LITTLE_ENDIAN
inline s4 s4FromSwitchData(const void* switchData) {
- return *(s4*) switchData;
+ return *reinterpret_cast<const s4*>(switchData);
}
#else
inline s4 s4FromSwitchData(const void* switchData) {
diff --git a/src/compiler/codegen/x86/X86/Factory.cc b/src/compiler/codegen/x86/X86/Factory.cc
index 8b02aeddb8..0a02c533b9 100644
--- a/src/compiler/codegen/x86/X86/Factory.cc
+++ b/src/compiler/codegen/x86/X86/Factory.cc
@@ -58,7 +58,7 @@ LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
int opcode;
/* must be both DOUBLE or both not DOUBLE */
- DCHECK_EQ(DOUBLEREG(rDest),DOUBLEREG(rSrc));
+ DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
if (DOUBLEREG(rDest)) {
opcode = kX86MovsdRR;
} else {
@@ -73,7 +73,7 @@ LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
opcode = kX86MovdrxRR;
}
}
- DCHECK((EncodingMap[opcode].flags & IS_BINARY_OP) != 0);
+ DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0);
LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, opcode, rDest, rSrc);
if (rDest == rSrc) {
res->flags.isNop = true;
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-09 11:12:03 +0000