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-rw-r--r--src/compiler/codegen/Ralloc.h4
-rw-r--r--src/compiler/codegen/arm/ArmLIR.h40
-rw-r--r--src/compiler/codegen/mips/MipsLIR.h32
-rw-r--r--src/compiler/codegen/x86/X86LIR.h32
4 files changed, 54 insertions, 54 deletions
diff --git a/src/compiler/codegen/Ralloc.h b/src/compiler/codegen/Ralloc.h
index c9e5308aad..8c8c693edb 100644
--- a/src/compiler/codegen/Ralloc.h
+++ b/src/compiler/codegen/Ralloc.h
@@ -28,11 +28,11 @@
namespace art {
/* Static register use counts */
-typedef struct RefCounts {
+struct RefCounts {
int count;
int sReg;
bool doubleStart; // Starting vReg for a double
-} RefCounts;
+};
inline int oatS2VReg(CompilationUnit* cUnit, int sReg)
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index bc85dd85e0..2f332f5816 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -129,7 +129,7 @@ namespace art {
INVALID_SREG}
#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, r0, r1, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 13,
kRegLR = 14,
@@ -144,7 +144,7 @@ typedef enum ResourceEncodingPos {
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -174,7 +174,7 @@ typedef enum ResourceEncodingPos {
*
* rPC, rFP, and rSELF are for architecture-independent code to use.
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r0 = 0,
r1 = 1,
r2 = 2,
@@ -242,7 +242,7 @@ typedef enum NativeRegisterPool {
dr13 = fr26 + FP_DOUBLE,
dr14 = fr28 + FP_DOUBLE,
dr15 = fr30 + FP_DOUBLE,
-} NativeRegisterPool;
+};
/* Target-independent aliases */
#define rARG0 r0
@@ -254,15 +254,15 @@ typedef enum NativeRegisterPool {
#define rINVOKE_TGT rLR
/* Shift encodings */
-typedef enum ArmShiftEncodings {
+enum ArmShiftEncodings {
kArmLsl = 0x0,
kArmLsr = 0x1,
kArmAsr = 0x2,
kArmRor = 0x3
-} ArmShiftEncodings;
+};
/* Thumb condition encodings */
-typedef enum ArmConditionCode {
+enum ArmConditionCode {
kArmCondEq = 0x0, /* 0000 */
kArmCondNe = 0x1, /* 0001 */
kArmCondCs = 0x2, /* 0010 */
@@ -279,7 +279,7 @@ typedef enum ArmConditionCode {
kArmCondLe = 0xd, /* 1101 */
kArmCondAl = 0xe, /* 1110 */
kArmCondNv = 0xf, /* 1111 */
-} ArmConditionCode;
+};
#define isPseudoOpcode(opcode) ((int)(opcode) < 0)
@@ -288,7 +288,7 @@ typedef enum ArmConditionCode {
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum ArmOpcode {
+enum ArmOpcode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -616,20 +616,20 @@ typedef enum ArmOpcode {
kThumb2Push1, /* t3 encoding of push */
kThumb2Pop1, /* t3 encoding of pop */
kArmLast,
-} ArmOpcode;
+};
/* DMB option encodings */
-typedef enum ArmOpDmbOptions {
+enum ArmOpDmbOptions {
kSY = 0xf,
kST = 0xe,
kISH = 0xb,
kISHST = 0xa,
kNSH = 0x7,
kNSHST = 0x6
-} ArmOpDmbOptions;
+};
/* Bit flags describing the behavior of each native opcode */
-typedef enum ArmOpFeatureFlags {
+enum ArmOpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -661,7 +661,7 @@ typedef enum ArmOpFeatureFlags {
kMemLoad,
kMemStore,
kPCRelFixup,
-} ArmOpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -705,7 +705,7 @@ typedef enum ArmOpFeatureFlags {
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Instruction assembly fieldLoc kind */
-typedef enum ArmEncodingKind {
+enum ArmEncodingKind {
kFmtUnused,
kFmtBitBlt, /* Bit string using end/start */
kFmtDfp, /* Double FP reg */
@@ -721,10 +721,10 @@ typedef enum ArmEncodingKind {
kFmtBrOffset, /* Signed extended [26,11,13,21-16,10-0]:0 */
kFmtFPImm, /* Encoded floating point immediate */
kFmtOff24, /* 24-bit Thumb2 unconditional branch encoding */
-} ArmEncodingKind;
+};
/* Struct used to define the snippet positions for each Thumb opcode */
-typedef struct ArmEncodingMap {
+struct ArmEncodingMap {
u4 skeleton;
struct {
ArmEncodingKind kind;
@@ -736,12 +736,12 @@ typedef struct ArmEncodingMap {
const char* name;
const char* fmt;
int size; /* Size in bytes */
-} ArmEncodingMap;
+};
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum ArmTargetOptHints {
+enum ArmTargetOptHints {
kMaxHoistDistance,
-} ArmTargetOptHints;
+};
extern const ArmEncodingMap EncodingMap[kArmLast];
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index 341e56bde4..1e7a80308f 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -154,7 +154,7 @@ namespace art {
#define LOC_C_RETURN_WIDE_ALT {kLocPhysReg, 1, 0, 0, 0, 0, 1, r_FRESULT0,\
r_FRESULT1, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 29,
kRegLR = 31,
@@ -171,7 +171,7 @@ typedef enum ResourceEncodingPos {
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -197,7 +197,7 @@ typedef enum ResourceEncodingPos {
* Annotate special-purpose core registers:
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r_ZERO = 0,
r_AT = 1,
r_V0 = 2,
@@ -286,7 +286,7 @@ typedef enum NativeRegisterPool {
r_HI = EXTRA_REG_OFFSET,
r_LO,
r_PC,
-} NativeRegisterPool;
+};
/*
* Target-independent aliases
@@ -304,12 +304,12 @@ typedef enum NativeRegisterPool {
#define rINVOKE_TGT r_V0
/* Shift encodings */
-typedef enum MipsShiftEncodings {
+enum MipsShiftEncodings {
kMipsLsl = 0x0,
kMipsLsr = 0x1,
kMipsAsr = 0x2,
kMipsRor = 0x3
-} MipsShiftEncodings;
+};
// MIPS sync kinds (Note: support for kinds other than kSYNC0 may not exist)
#define kSYNC0 0x00
@@ -330,7 +330,7 @@ typedef enum MipsShiftEncodings {
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum MipsOpCode {
+enum MipsOpCode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -441,10 +441,10 @@ typedef enum MipsOpCode {
kMipsSync, /* sync kind [000000] [0000000000000000] s[10..6] [001111] */
kMipsUndefined, /* undefined [011001xxxxxxxxxxxxxxxx] */
kMipsLast
-} MipsOpCode;
+};
/* Bit flags describing the behavior of each native opcode */
-typedef enum MipsOpFeatureFlags {
+enum MipsOpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -472,7 +472,7 @@ typedef enum MipsOpFeatureFlags {
kMemStore,
kPCRelFixup,
kRegUseLR,
-} MipsOpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -522,16 +522,16 @@ typedef enum MipsOpFeatureFlags {
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Instruction assembly fieldLoc kind */
-typedef enum MipsEncodingKind {
+enum MipsEncodingKind {
kFmtUnused,
kFmtBitBlt, /* Bit string using end/start */
kFmtDfp, /* Double FP reg */
kFmtSfp, /* Single FP reg */
kFmtBlt5_2, /* Same 5-bit field to 2 locations */
-} MipsEncodingKind;
+};
/* Struct used to define the snippet positions for each MIPS opcode */
-typedef struct MipsEncodingMap {
+struct MipsEncodingMap {
u4 skeleton;
struct {
MipsEncodingKind kind;
@@ -543,12 +543,12 @@ typedef struct MipsEncodingMap {
const char *name;
const char* fmt;
int size; /* Size in bytes */
-} MipsEncodingMap;
+};
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum MipsTargetOptHints {
+enum MipsTargetOptHints {
kMaxHoistDistance,
-} MipsTargetOptHints;
+};
extern MipsEncodingMap EncodingMap[kMipsLast];
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 32bb1f8cef..31449e0d12 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -138,7 +138,7 @@ namespace art {
INVALID_SREG}
#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 1, rAX, rDX, INVALID_SREG}
-typedef enum ResourceEncodingPos {
+enum ResourceEncodingPos {
kGPReg0 = 0,
kRegSP = 4,
kRegLR = -1,
@@ -151,7 +151,7 @@ typedef enum ResourceEncodingPos {
kLiteral, // 2 Literal pool (can be fully disambiguated)
kHeapRef, // 3 Somewhere on the heap (alias with any other heap)
kMustNotAlias, // 4 Guaranteed to be non-alias (eg *(r6+x))
-} ResourceEncodingPos;
+};
#define ENCODE_REG_LIST(N) ((u8) N)
#define ENCODE_REG_SP (1ULL << kRegSP)
@@ -175,7 +175,7 @@ typedef enum ResourceEncodingPos {
* Annotate special-purpose core registers:
*/
-typedef enum NativeRegisterPool {
+enum NativeRegisterPool {
r0 = 0,
rAX = r0,
r1 = 1,
@@ -216,7 +216,7 @@ typedef enum NativeRegisterPool {
fr13 = 13 + FP_REG_OFFSET,
fr14 = 14 + FP_REG_OFFSET,
fr15 = 15 + FP_REG_OFFSET,
-} NativeRegisterPool;
+};
/*
* Target-independent aliases
@@ -235,7 +235,7 @@ typedef enum NativeRegisterPool {
* assembler. Their corresponding EncodingMap positions will be defined in
* Assemble.cc.
*/
-typedef enum X86OpCode {
+enum X86OpCode {
kPseudoSuspendTarget = -15,
kPseudoThrowTarget = -14,
kPseudoCaseLabel = -13,
@@ -285,25 +285,25 @@ typedef enum X86OpCode {
BinaryOpCode(kOpMov),
#undef BinaryOpCode
kX86Last
-} X86OpCode;
+};
/* Instruction assembly fieldLoc kind */
-typedef enum X86EncodingKind {
+enum X86EncodingKind {
kData, // Special case for raw data
kRegImm, kMemImm, kArrayImm, // RI, MI, AI instruction kinds
kRegReg, kRegMem, kRegArray, // RR, RM, RA instruction kinds
kMemReg, kArrayReg, // MR and AR instruction kinds
kUnimplemented // Encoding used when an instruction isn't yet implemented.
-} X86EncodingKind;
+};
/* A form of instruction with an opcode byte and a secondary opcode within the modrm byte */
-typedef struct OpcodeModRMOpcode {
+struct OpcodeModRMOpcode {
uint8_t opcode; // 1 byte opcode
uint8_t modrm_opcode; // 3 bit opcode that gets encoded in the register bits of the modrm byte
-} OpcodeModRMOpcode;
+};
/* Struct used to define the EncodingMap positions for each X86 opcode */
-typedef struct X86EncodingMap {
+struct X86EncodingMap {
X86OpCode opcode; // e.g. kOpAddRI
X86EncodingKind kind; // Used to discriminate in the union below
int flags;
@@ -328,7 +328,7 @@ typedef struct X86EncodingMap {
} skeleton;
const char *name;
const char* fmt;
-} X86EncodingMap;
+};
extern X86EncodingMap EncodingMap[kX86Last];
@@ -337,7 +337,7 @@ extern X86EncodingMap EncodingMap[kX86Last];
#define kST 0
/* Bit flags describing the behavior of each native opcode */
-typedef enum X86OpFeatureFlags {
+enum X86OpFeatureFlags {
kIsBranch = 0,
kRegDef0,
kRegDef1,
@@ -363,7 +363,7 @@ typedef enum X86OpFeatureFlags {
kMemStore,
kPCRelFixup,
// FIXME: add NEEDS_FIXUP to instruction attributes
-} X86OpFeatureFlags;
+};
#define IS_LOAD (1 << kMemLoad)
#define IS_STORE (1 << kMemStore)
@@ -412,9 +412,9 @@ typedef enum X86OpFeatureFlags {
#define REG_DEF01_USE2 (REG_DEF0 | REG_DEF1 | REG_USE2)
/* Keys for target-specific scheduling and other optimization hints */
-typedef enum X86TargetOptHints {
+enum X86TargetOptHints {
kMaxHoistDistance,
-} X86TargetOptHints;
+};
#define IS_SIMM8(v) ((-128 <= (v)) && ((v) <= 127))
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-10-21 00:11:49 +0000