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-rw-r--r--src/compiler/codegen/x86/ArchFactory.cc32
-rw-r--r--src/compiler/codegen/x86/ArchUtility.cc91
-rw-r--r--src/compiler/codegen/x86/Assemble.cc68
-rw-r--r--src/compiler/codegen/x86/FP/X86FP.cc22
-rw-r--r--src/compiler/codegen/x86/X86/Factory.cc54
-rw-r--r--src/compiler/codegen/x86/X86/Gen.cc24
-rw-r--r--src/compiler/codegen/x86/X86LIR.h100
-rw-r--r--src/compiler/codegen/x86/X86RallocUtil.cc30
8 files changed, 251 insertions, 170 deletions
diff --git a/src/compiler/codegen/x86/ArchFactory.cc b/src/compiler/codegen/x86/ArchFactory.cc
index 1fc10340bd..0ed68484f4 100644
--- a/src/compiler/codegen/x86/ArchFactory.cc
+++ b/src/compiler/codegen/x86/ArchFactory.cc
@@ -123,7 +123,7 @@ void spillCoreRegs(CompilationUnit* cUnit) {
int offset = cUnit->frameSize - (4 * cUnit->numCoreSpills);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
- storeWordDisp(cUnit, rSP, offset, reg);
+ storeWordDisp(cUnit, rX86_SP, offset, reg);
offset += 4;
}
}
@@ -138,7 +138,7 @@ void unSpillCoreRegs(CompilationUnit* cUnit) {
int offset = cUnit->frameSize - (4 * cUnit->numCoreSpills);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
- loadWordDisp(cUnit, rSP, offset, reg);
+ loadWordDisp(cUnit, rX86_SP, offset, reg);
offset += 4;
}
}
@@ -159,17 +159,17 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
RegLocation rlMethod)
{
/*
- * On entry, rARG0, rARG1, rARG2 are live. Let the register
+ * On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live. Let the register
* allocation mechanism know so it doesn't try to use any of them when
* expanding the frame or flushing. This leaves the utility
* code with no spare temps.
*/
- oatLockTemp(cUnit, rARG0);
- oatLockTemp(cUnit, rARG1);
- oatLockTemp(cUnit, rARG2);
+ oatLockTemp(cUnit, rX86_ARG0);
+ oatLockTemp(cUnit, rX86_ARG1);
+ oatLockTemp(cUnit, rX86_ARG2);
/* Build frame, return address already on stack */
- opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - 4);
+ opRegImm(cUnit, kOpSub, rX86_SP, cUnit->frameSize - 4);
/*
* We can safely skip the stack overflow check if we're
@@ -184,9 +184,9 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
/* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
DCHECK_EQ(cUnit->numFPSpills, 0);
if (!skipOverflowCheck) {
- // cmp rSP, fs:[stack_end_]; jcc throw_launchpad
+ // cmp rX86_SP, fs:[stack_end_]; jcc throw_launchpad
LIR* tgt = rawLIR(cUnit, 0, kPseudoThrowTarget, kThrowStackOverflow, 0, 0, 0, 0);
- opRegThreadMem(cUnit, kOpCmp, rSP, Thread::StackEndOffset().Int32Value());
+ opRegThreadMem(cUnit, kOpCmp, rX86_SP, Thread::StackEndOffset().Int32Value());
opCondBranch(cUnit, kCondUlt, tgt);
// Remember branch target - will process later
oatInsertGrowableList(cUnit, &cUnit->throwLaunchpads, (intptr_t)tgt);
@@ -194,23 +194,23 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
flushIns(cUnit, argLocs, rlMethod);
- oatFreeTemp(cUnit, rARG0);
- oatFreeTemp(cUnit, rARG1);
- oatFreeTemp(cUnit, rARG2);
+ oatFreeTemp(cUnit, rX86_ARG0);
+ oatFreeTemp(cUnit, rX86_ARG1);
+ oatFreeTemp(cUnit, rX86_ARG2);
}
void genExitSequence(CompilationUnit* cUnit) {
/*
- * In the exit path, rRET0/rRET1 are live - make sure they aren't
+ * In the exit path, rX86_RET0/rX86_RET1 are live - make sure they aren't
* allocated by the register utilities as temps.
*/
- oatLockTemp(cUnit, rRET0);
- oatLockTemp(cUnit, rRET1);
+ oatLockTemp(cUnit, rX86_RET0);
+ oatLockTemp(cUnit, rX86_RET1);
newLIR0(cUnit, kPseudoMethodExit);
unSpillCoreRegs(cUnit);
/* Remove frame except for return address */
- opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize - 4);
+ opRegImm(cUnit, kOpAdd, rX86_SP, cUnit->frameSize - 4);
newLIR0(cUnit, kX86Ret);
}
diff --git a/src/compiler/codegen/x86/ArchUtility.cc b/src/compiler/codegen/x86/ArchUtility.cc
index 953ce4a899..32dd811045 100644
--- a/src/compiler/codegen/x86/ArchUtility.cc
+++ b/src/compiler/codegen/x86/ArchUtility.cc
@@ -22,6 +22,91 @@
namespace art {
+RegLocation locCReturn()
+{
+ RegLocation res = X86_LOC_C_RETURN;
+ return res;
+}
+
+RegLocation locCReturnWide()
+{
+ RegLocation res = X86_LOC_C_RETURN_WIDE;
+ return res;
+}
+
+RegLocation locCReturnFloat()
+{
+ RegLocation res = X86_LOC_C_RETURN_FLOAT;
+ return res;
+}
+
+RegLocation locCReturnDouble()
+{
+ RegLocation res = X86_LOC_C_RETURN_DOUBLE;
+ return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+ int res = INVALID_REG;
+ switch (reg) {
+ case kSelf: res = rX86_SELF; break;
+ case kSuspend: res = rX86_SUSPEND; break;
+ case kLr: res = rX86_LR; break;
+ case kPc: res = rX86_PC; break;
+ case kSp: res = rX86_SP; break;
+ case kArg0: res = rX86_ARG0; break;
+ case kArg1: res = rX86_ARG1; break;
+ case kArg2: res = rX86_ARG2; break;
+ case kArg3: res = rX86_ARG3; break;
+ case kFArg0: res = rX86_FARG0; break;
+ case kFArg1: res = rX86_FARG1; break;
+ case kFArg2: res = rX86_FARG2; break;
+ case kFArg3: res = rX86_FARG3; break;
+ case kRet0: res = rX86_RET0; break;
+ case kRet1: res = rX86_RET1; break;
+ case kInvokeTgt: res = rX86_INVOKE_TGT; break;
+ case kCount: res = rX86_COUNT; break;
+ }
+ return res;
+}
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+ return X86_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+ return X86_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+ return X86_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+ return X86_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+ return X86_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+ return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
+}
+
/*
* Decode the register id.
*/
@@ -35,7 +120,7 @@ u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
/* Double registers in x86 are just a single FP register */
seed = 1;
/* FP register starts at bit position 16 */
- shift = FPREG(reg) ? kX86FPReg0 : 0;
+ shift = X86_FPREG(reg) ? kX86FPReg0 : 0;
/* Expand the double register id into single offset */
shift += regId;
return (seed << shift);
@@ -149,8 +234,8 @@ std::string buildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
break;
}
case 'r':
- if (FPREG(operand) || DOUBLEREG(operand)) {
- int fp_reg = operand & FP_REG_MASK;
+ if (X86_FPREG(operand) || X86_DOUBLEREG(operand)) {
+ int fp_reg = operand & X86_FP_REG_MASK;
buf += StringPrintf("xmm%d", fp_reg);
} else {
DCHECK_LT(static_cast<size_t>(operand), sizeof(x86RegName));
diff --git a/src/compiler/codegen/x86/Assemble.cc b/src/compiler/codegen/x86/Assemble.cc
index 71fcdc8b38..a5388e8428 100644
--- a/src/compiler/codegen/x86/Assemble.cc
+++ b/src/compiler/codegen/x86/Assemble.cc
@@ -376,7 +376,7 @@ int oatGetInsnSize(LIR* lir) {
int disp = lir->operands[1];
// SP requires a special extra SIB byte. BP requires explicit disp,
// so add a byte for disp 0 which would normally be omitted.
- return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);
+ return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);
}
case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
return computeSize(entry, lir->operands[3], true);
@@ -385,7 +385,7 @@ int oatGetInsnSize(LIR* lir) {
int disp = lir->operands[1];
// SP requires a special extra SIB byte. BP requires explicit disp,
// so add a byte for disp 0 which would normally be omitted.
- return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);
+ return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);
}
case kArrayReg: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
return computeSize(entry, lir->operands[3], true);
@@ -400,7 +400,7 @@ int oatGetInsnSize(LIR* lir) {
int disp = lir->operands[2];
// SP requires a special extra SIB byte. BP requires explicit disp,
// so add a byte for disp 0 which would normally be omitted.
- return computeSize(entry, disp, false) + ((base == rSP) || (base == rBP && disp == 0) ? 1 : 0);
+ return computeSize(entry, disp, false) + ((base == rX86_SP) || (base == rBP && disp == 0) ? 1 : 0);
}
case kRegArray: { // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp
int base = lir->operands[1];
@@ -421,7 +421,7 @@ int oatGetInsnSize(LIR* lir) {
}
}
case kMemImm: // lir operands - 0: base, 1: disp, 2: immediate
- CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte
+ CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte
return computeSize(entry, lir->operands[1], false);
case kArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
return computeSize(entry, lir->operands[3], true);
@@ -430,7 +430,7 @@ int oatGetInsnSize(LIR* lir) {
case kRegRegImm: // lir operands - 0: reg, 1: reg, 2: imm
return computeSize(entry, 0, false);
case kRegMemImm: // lir operands - 0: reg, 1: base, 2: disp, 3: imm
- CHECK_NE(lir->operands[1], static_cast<int>(rSP)); // TODO: add extra SIB byte
+ CHECK_NE(lir->operands[1], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte
return computeSize(entry, lir->operands[2], false);
case kRegArrayImm: // lir operands - 0: reg, 1: base, 2: index, 3: scale, 4: disp, 5: imm
return computeSize(entry, lir->operands[4], true);
@@ -440,7 +440,7 @@ int oatGetInsnSize(LIR* lir) {
// Shift by immediate one has a shorter opcode.
return computeSize(entry, 0, false) - (lir->operands[1] == 1 ? 1 : 0);
case kShiftMemImm: // lir operands - 0: base, 1: disp, 2: immediate
- CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte
+ CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte
// Shift by immediate one has a shorter opcode.
return computeSize(entry, lir->operands[1], false) - (lir->operands[2] == 1 ? 1 : 0);
case kShiftArrayImm: // lir operands - 0: base, 1: index, 2: scale, 3: disp 4: immediate
@@ -449,14 +449,14 @@ int oatGetInsnSize(LIR* lir) {
case kShiftRegCl:
return computeSize(entry, 0, false);
case kShiftMemCl: // lir operands - 0: base, 1: disp, 2: cl
- CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte
+ CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte
return computeSize(entry, lir->operands[1], false);
case kShiftArrayCl: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: reg
return computeSize(entry, lir->operands[3], true);
case kRegCond: // lir operands - 0: reg, 1: cond
return computeSize(entry, 0, false);
case kMemCond: // lir operands - 0: base, 1: disp, 2: cond
- CHECK_NE(lir->operands[0], static_cast<int>(rSP)); // TODO: add extra SIB byte
+ CHECK_NE(lir->operands[0], static_cast<int>(rX86_SP)); // TODO: add extra SIB byte
return computeSize(entry, lir->operands[1], false);
case kArrayCond: // lir operands - 0: base, 1: index, 2: scale, 3: disp, 4: cond
return computeSize(entry, lir->operands[3], true);
@@ -555,8 +555,8 @@ static void emitOpReg(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg)) {
- reg = reg & FP_REG_MASK;
+ if (X86_FPREG(reg)) {
+ reg = reg & X86_FP_REG_MASK;
}
if (reg >= 4) {
DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
@@ -612,8 +612,8 @@ static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg)) {
- reg = reg & FP_REG_MASK;
+ if (X86_FPREG(reg)) {
+ reg = reg & X86_FP_REG_MASK;
}
if (reg >= 4) {
DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
@@ -623,9 +623,9 @@ static void emitMemReg(CompilationUnit* cUnit, const X86EncodingMap* entry,
DCHECK_LT(base, 8);
uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | base;
cUnit->codeBuffer.push_back(modrm);
- if (base == rSP) {
+ if (base == rX86_SP) {
// Special SIB for SP base
- cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);
+ cUnit->codeBuffer.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);
}
emitDisp(cUnit, base, disp);
DCHECK_EQ(0, entry->skeleton.modrm_opcode);
@@ -661,11 +661,11 @@ static void emitRegArray(CompilationUnit* cUnit, const X86EncodingMap* entry, ui
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg)) {
- reg = reg & FP_REG_MASK;
+ if (X86_FPREG(reg)) {
+ reg = reg & X86_FP_REG_MASK;
}
DCHECK_LT(reg, 8);
- uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rSP;
+ uint8_t modrm = (modrmForDisp(base, disp) << 6) | (reg << 3) | rX86_SP;
cUnit->codeBuffer.push_back(modrm);
DCHECK_LT(scale, 4);
DCHECK_LT(index, 8);
@@ -703,8 +703,8 @@ static void emitRegThread(CompilationUnit* cUnit, const X86EncodingMap* entry,
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg)) {
- reg = reg & FP_REG_MASK;
+ if (X86_FPREG(reg)) {
+ reg = reg & X86_FP_REG_MASK;
}
if (reg >= 4) {
DCHECK(strchr(entry->name, '8') == NULL) << entry->name << " " << (int) reg
@@ -744,11 +744,11 @@ static void emitRegReg(CompilationUnit* cUnit, const X86EncodingMap* entry,
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg1)) {
- reg1 = reg1 & FP_REG_MASK;
+ if (X86_FPREG(reg1)) {
+ reg1 = reg1 & X86_FP_REG_MASK;
}
- if (FPREG(reg2)) {
- reg2 = reg2 & FP_REG_MASK;
+ if (X86_FPREG(reg2)) {
+ reg2 = reg2 & X86_FP_REG_MASK;
}
DCHECK_LT(reg1, 8);
DCHECK_LT(reg2, 8);
@@ -781,11 +781,11 @@ static void emitRegRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg1)) {
- reg1 = reg1 & FP_REG_MASK;
+ if (X86_FPREG(reg1)) {
+ reg1 = reg1 & X86_FP_REG_MASK;
}
- if (FPREG(reg2)) {
- reg2 = reg2 & FP_REG_MASK;
+ if (X86_FPREG(reg2)) {
+ reg2 = reg2 & X86_FP_REG_MASK;
}
DCHECK_LT(reg1, 8);
DCHECK_LT(reg2, 8);
@@ -841,8 +841,8 @@ static void emitRegImm(CompilationUnit* cUnit, const X86EncodingMap* entry,
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
}
- if (FPREG(reg)) {
- reg = reg & FP_REG_MASK;
+ if (X86_FPREG(reg)) {
+ reg = reg & X86_FP_REG_MASK;
}
uint8_t modrm = (3 << 6) | (entry->skeleton.modrm_opcode << 3) | reg;
cUnit->codeBuffer.push_back(modrm);
@@ -1079,9 +1079,9 @@ static void emitCallMem(CompilationUnit* cUnit, const X86EncodingMap* entry,
}
uint8_t modrm = (modrmForDisp(base, disp) << 6) | (entry->skeleton.modrm_opcode << 3) | base;
cUnit->codeBuffer.push_back(modrm);
- if (base == rSP) {
+ if (base == rX86_SP) {
// Special SIB for SP base
- cUnit->codeBuffer.push_back(0 << 6 | (rSP << 3) | rSP);
+ cUnit->codeBuffer.push_back(0 << 6 | (rX86_SP << 3) | rX86_SP);
}
emitDisp(cUnit, base, disp);
DCHECK_EQ(0, entry->skeleton.ax_opcode);
@@ -1135,15 +1135,15 @@ static void emitPcRel(CompilationUnit* cUnit, const X86EncodingMap* entry, uint8
} else {
DCHECK_EQ(0, entry->skeleton.prefix2);
}
- if (FPREG(reg)) {
- reg = reg & FP_REG_MASK;
+ if (X86_FPREG(reg)) {
+ reg = reg & X86_FP_REG_MASK;
}
DCHECK_LT(reg, 8);
if (entry->opcode == kX86PcRelLoadRA) {
cUnit->codeBuffer.push_back(entry->skeleton.opcode);
DCHECK_EQ(0, entry->skeleton.extra_opcode1);
DCHECK_EQ(0, entry->skeleton.extra_opcode2);
- uint8_t modrm = (2 << 6) | (reg << 3) | rSP;
+ uint8_t modrm = (2 << 6) | (reg << 3) | rX86_SP;
cUnit->codeBuffer.push_back(modrm);
DCHECK_LT(scale, 4);
DCHECK_LT(index, 8);
diff --git a/src/compiler/codegen/x86/FP/X86FP.cc b/src/compiler/codegen/x86/FP/X86FP.cc
index af6ddb0c7e..5e97a50d50 100644
--- a/src/compiler/codegen/x86/FP/X86FP.cc
+++ b/src/compiler/codegen/x86/FP/X86FP.cc
@@ -104,11 +104,11 @@ static bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
DCHECK(rlDest.wide);
DCHECK(rlResult.wide);
- int rDest = S2D(rlResult.lowReg, rlResult.highReg);
- int rSrc1 = S2D(rlSrc1.lowReg, rlSrc1.highReg);
- int rSrc2 = S2D(rlSrc2.lowReg, rlSrc2.highReg);
+ int rDest = s2d(rlResult.lowReg, rlResult.highReg);
+ int rSrc1 = s2d(rlSrc1.lowReg, rlSrc1.highReg);
+ int rSrc2 = s2d(rlSrc2.lowReg, rlSrc2.highReg);
if (rDest == rSrc2) {
- rSrc2 = oatAllocTempDouble(cUnit) | FP_DOUBLE;
+ rSrc2 = oatAllocTempDouble(cUnit) | X86_FP_DOUBLE;
opRegCopy(cUnit, rSrc2, rDest);
}
opRegCopy(cUnit, rDest, rSrc1);
@@ -166,7 +166,7 @@ static bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
srcReg = rlSrc.lowReg;
oatClobberSReg(cUnit, rlDest.sRegLow);
rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
- int tempReg = oatAllocTempDouble(cUnit) | FP_DOUBLE;
+ int tempReg = oatAllocTempDouble(cUnit) | X86_FP_DOUBLE;
loadConstant(cUnit, rlResult.lowReg, 0x7fffffff);
newLIR2(cUnit, kX86Cvtsi2sdRR, tempReg, rlResult.lowReg);
@@ -193,14 +193,14 @@ static bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
}
if (rlSrc.wide) {
rlSrc = loadValueWide(cUnit, rlSrc, rcSrc);
- srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
+ srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
} else {
rlSrc = loadValue(cUnit, rlSrc, rcSrc);
srcReg = rlSrc.lowReg;
}
if (rlDest.wide) {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, op, S2D(rlResult.lowReg, rlResult.highReg), srcReg);
+ newLIR2(cUnit, op, s2d(rlResult.lowReg, rlResult.highReg), srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
@@ -223,9 +223,9 @@ static bool genCmpFP(CompilationUnit *cUnit, Instruction::Code code, RegLocation
srcReg2 = rlSrc2.lowReg;
} else {
rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
- srcReg1 = S2D(rlSrc1.lowReg, rlSrc1.highReg);
+ srcReg1 = s2d(rlSrc1.lowReg, rlSrc1.highReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
- srcReg2 = S2D(rlSrc2.lowReg, rlSrc2.highReg);
+ srcReg2 = s2d(rlSrc2.lowReg, rlSrc2.highReg);
}
oatClobberSReg(cUnit, rlDest.sRegLow);
RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
@@ -274,8 +274,8 @@ void genFusedFPCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
rlSrc2 = oatGetSrcWide(cUnit, mir, 2);
rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
- newLIR2(cUnit, kX86UcomisdRR, S2D(rlSrc1.lowReg, rlSrc1.highReg),
- S2D(rlSrc2.lowReg, rlSrc2.highReg));
+ newLIR2(cUnit, kX86UcomisdRR, s2d(rlSrc1.lowReg, rlSrc1.highReg),
+ s2d(rlSrc2.lowReg, rlSrc2.highReg));
} else {
rlSrc1 = oatGetSrc(cUnit, mir, 0);
rlSrc2 = oatGetSrc(cUnit, mir, 1);
diff --git a/src/compiler/codegen/x86/X86/Factory.cc b/src/compiler/codegen/x86/X86/Factory.cc
index 040ef17278..454b98d687 100644
--- a/src/compiler/codegen/x86/X86/Factory.cc
+++ b/src/compiler/codegen/x86/X86/Factory.cc
@@ -20,12 +20,12 @@ namespace art {
//FIXME: restore "static" when usage uncovered
/*static*/ int coreRegs[] = {
- rAX, rCX, rDX, rBX, rSP, rBP, rSI, rDI
+ rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
#ifdef TARGET_REX_SUPPORT
r8, r9, r10, r11, r12, r13, r14, 15
#endif
};
-/*static*/ int reservedRegs[] = {rSP};
+/*static*/ int reservedRegs[] = {rX86_SP};
/*static*/ int coreTemps[] = {rAX, rCX, rDX, rBX};
/*static*/ int fpRegs[] = {
fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
@@ -52,18 +52,18 @@ LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
int opcode;
/* must be both DOUBLE or both not DOUBLE */
- DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
- if (DOUBLEREG(rDest)) {
+ DCHECK_EQ(X86_DOUBLEREG(rDest), X86_DOUBLEREG(rSrc));
+ if (X86_DOUBLEREG(rDest)) {
opcode = kX86MovsdRR;
} else {
- if (SINGLEREG(rDest)) {
- if (SINGLEREG(rSrc)) {
+ if (X86_SINGLEREG(rDest)) {
+ if (X86_SINGLEREG(rSrc)) {
opcode = kX86MovssRR;
} else { // Fpr <- Gpr
opcode = kX86MovdxrRR;
}
} else { // Gpr <- Fpr
- DCHECK(SINGLEREG(rSrc));
+ DCHECK(X86_SINGLEREG(rSrc));
opcode = kX86MovdrxRR;
}
}
@@ -87,11 +87,11 @@ LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
LIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
{
int rDestSave = rDest;
- if (FPREG(rDest)) {
+ if (X86_FPREG(rDest)) {
if (value == 0) {
return newLIR2(cUnit, kX86XorpsRR, rDest, rDest);
}
- DCHECK(SINGLEREG(rDest));
+ DCHECK(X86_SINGLEREG(rDest));
rDest = oatAllocTemp(cUnit);
}
@@ -103,7 +103,7 @@ LIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
res = newLIR2(cUnit, kX86Mov32RI, rDest, value);
}
- if (FPREG(rDestSave)) {
+ if (X86_FPREG(rDestSave)) {
newLIR2(cUnit, kX86MovdxrRR, rDestSave, rDest);
oatFreeTemp(cUnit, rDest);
}
@@ -145,7 +145,7 @@ LIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int value)
{
X86OpCode opcode = kX86Bkpt;
bool byteImm = IS_SIMM8(value);
- DCHECK(!FPREG(rDestSrc1));
+ DCHECK(!X86_FPREG(rDestSrc1));
switch (op) {
case kOpLsl: opcode = kX86Sal32RI; break;
case kOpLsr: opcode = kX86Shr32RI; break;
@@ -342,8 +342,8 @@ LIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo,
int rDestHi, int valLo, int valHi)
{
LIR *res;
- if (FPREG(rDestLo)) {
- DCHECK(FPREG(rDestHi)); // ignore rDestHi
+ if (X86_FPREG(rDestLo)) {
+ DCHECK(X86_FPREG(rDestHi)); // ignore rDestHi
if (valLo == 0 && valHi == 0) {
return newLIR2(cUnit, kX86XorpsRR, rDestLo, rDestLo);
} else {
@@ -393,12 +393,12 @@ LIR* loadBaseIndexedDisp(CompilationUnit *cUnit,
case kLong:
case kDouble:
is64bit = true;
- if (FPREG(rDest)) {
+ if (X86_FPREG(rDest)) {
opcode = isArray ? kX86MovsdRA : kX86MovsdRM;
- if (SINGLEREG(rDest)) {
- DCHECK(FPREG(rDestHi));
+ if (X86_SINGLEREG(rDest)) {
+ DCHECK(X86_FPREG(rDestHi));
DCHECK_EQ(rDest, (rDestHi - 1));
- rDest = S2D(rDest, rDestHi);
+ rDest = s2d(rDest, rDestHi);
}
rDestHi = rDest + 1;
} else {
@@ -411,9 +411,9 @@ LIR* loadBaseIndexedDisp(CompilationUnit *cUnit,
case kWord:
case kSingle:
opcode = isArray ? kX86Mov32RA : kX86Mov32RM;
- if (FPREG(rDest)) {
+ if (X86_FPREG(rDest)) {
opcode = isArray ? kX86MovssRA : kX86MovssRM;
- DCHECK(SINGLEREG(rDest));
+ DCHECK(X86_SINGLEREG(rDest));
}
DCHECK_EQ((displacement & 0x3), 0);
break;
@@ -449,7 +449,7 @@ LIR* loadBaseIndexedDisp(CompilationUnit *cUnit,
displacement + HIWORD_OFFSET);
}
}
- if (rBase == rSP) {
+ if (rBase == rX86_SP) {
annotateDalvikRegAccess(load, (displacement + (pair ? LOWORD_OFFSET : 0))
>> 2, true /* isLoad */, is64bit);
if (pair) {
@@ -516,12 +516,12 @@ LIR* storeBaseIndexedDisp(CompilationUnit *cUnit,
case kLong:
case kDouble:
is64bit = true;
- if (FPREG(rSrc)) {
+ if (X86_FPREG(rSrc)) {
opcode = isArray ? kX86MovsdAR : kX86MovsdMR;
- if (SINGLEREG(rSrc)) {
- DCHECK(FPREG(rSrcHi));
+ if (X86_SINGLEREG(rSrc)) {
+ DCHECK(X86_FPREG(rSrcHi));
DCHECK_EQ(rSrc, (rSrcHi - 1));
- rSrc = S2D(rSrc, rSrcHi);
+ rSrc = s2d(rSrc, rSrcHi);
}
rSrcHi = rSrc + 1;
} else {
@@ -534,9 +534,9 @@ LIR* storeBaseIndexedDisp(CompilationUnit *cUnit,
case kWord:
case kSingle:
opcode = isArray ? kX86Mov32AR : kX86Mov32MR;
- if (FPREG(rSrc)) {
+ if (X86_FPREG(rSrc)) {
opcode = isArray ? kX86MovssAR : kX86MovssMR;
- DCHECK(SINGLEREG(rSrc));
+ DCHECK(X86_SINGLEREG(rSrc));
}
DCHECK_EQ((displacement & 0x3), 0);
break;
@@ -560,7 +560,7 @@ LIR* storeBaseIndexedDisp(CompilationUnit *cUnit,
store = newLIR3(cUnit, opcode, rBase, displacement + LOWORD_OFFSET, rSrc);
store2 = newLIR3(cUnit, opcode, rBase, displacement + HIWORD_OFFSET, rSrcHi);
}
- if (rBase == rSP) {
+ if (rBase == rX86_SP) {
annotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
>> 2, false /* isLoad */, is64bit);
if (pair) {
diff --git a/src/compiler/codegen/x86/X86/Gen.cc b/src/compiler/codegen/x86/X86/Gen.cc
index b57acac271..37cd725025 100644
--- a/src/compiler/codegen/x86/X86/Gen.cc
+++ b/src/compiler/codegen/x86/X86/Gen.cc
@@ -163,12 +163,12 @@ void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
// Making a call - use explicit registers
oatFlushAllRegs(cUnit); /* Everything to home location */
- loadValueDirectFixed(cUnit, rlSrc, rARG0);
+ loadValueDirectFixed(cUnit, rlSrc, rX86_ARG0);
// Materialize a pointer to the fill data image
- newLIR1(cUnit, kX86StartOfMethod, rARG2);
- newLIR2(cUnit, kX86PcRelAdr, rARG1, (intptr_t)tabRec);
- newLIR2(cUnit, kX86Add32RR, rARG1, rARG2);
- callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rARG0, rARG1,
+ newLIR1(cUnit, kX86StartOfMethod, rX86_ARG2);
+ newLIR2(cUnit, kX86PcRelAdr, rX86_ARG1, (intptr_t)tabRec);
+ newLIR2(cUnit, kX86Add32RR, rX86_ARG1, rX86_ARG2);
+ callRuntimeHelperRegReg(cUnit, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode), rX86_ARG0, rX86_ARG1,
true);
}
@@ -266,7 +266,7 @@ void genCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
newLIR2(cUnit, kX86Set8R, r0, kX86CondNz); // r0 = (r1:r0) != (r3:r2) ? 1 : 0
newLIR2(cUnit, kX86Movzx8RR, r0, r0);
opRegReg(cUnit, kOpOr, r0, r2); // r0 = r0 | r2
- RegLocation rlResult = LOC_C_RETURN;
+ RegLocation rlResult = locCReturn();
storeValue(cUnit, rlDest, rlResult);
}
@@ -320,7 +320,7 @@ LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
LIR* opRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
- if (FPREG(rDest) || FPREG(rSrc))
+ if (X86_FPREG(rDest) || X86_FPREG(rSrc))
return fpRegCopy(cUnit, rDest, rSrc);
LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, kX86Mov32RR,
rDest, rSrc);
@@ -340,13 +340,13 @@ LIR* opRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
void opRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
- bool destFP = FPREG(destLo) && FPREG(destHi);
- bool srcFP = FPREG(srcLo) && FPREG(srcHi);
- assert(FPREG(srcLo) == FPREG(srcHi));
- assert(FPREG(destLo) == FPREG(destHi));
+ bool destFP = X86_FPREG(destLo) && X86_FPREG(destHi);
+ bool srcFP = X86_FPREG(srcLo) && X86_FPREG(srcHi);
+ assert(X86_FPREG(srcLo) == X86_FPREG(srcHi));
+ assert(X86_FPREG(destLo) == X86_FPREG(destHi));
if (destFP) {
if (srcFP) {
- opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
} else {
// TODO: Prevent this from happening in the code. The result is often
// unused or could have been loaded more easily from memory.
diff --git a/src/compiler/codegen/x86/X86LIR.h b/src/compiler/codegen/x86/X86LIR.h
index 59b1859134..bccd365604 100644
--- a/src/compiler/codegen/x86/X86LIR.h
+++ b/src/compiler/codegen/x86/X86LIR.h
@@ -105,18 +105,17 @@ namespace art {
*/
/* Offset to distingish FP regs */
-#define FP_REG_OFFSET 32
+#define X86_FP_REG_OFFSET 32
/* Offset to distinguish DP FP regs */
-#define FP_DOUBLE (FP_REG_OFFSET + 16)
+#define X86_FP_DOUBLE (X86_FP_REG_OFFSET + 16)
/* Offset to distingish the extra regs */
-#define EXTRA_REG_OFFSET (FP_DOUBLE + 16)
+#define X86_EXTRA_REG_OFFSET (X86_FP_DOUBLE + 16)
/* Reg types */
-#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
-#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)
-#define EXTRAREG(x) ((x & EXTRA_REG_OFFSET) == EXTRA_REG_OFFSET)
-#define LOWREG(x) ((x & 0x1f) == x)
-#define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE)
-#define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x))
+#define X86_REGTYPE(x) (x & (X86_FP_REG_OFFSET | X86_FP_DOUBLE))
+#define X86_FPREG(x) ((x & X86_FP_REG_OFFSET) == X86_FP_REG_OFFSET)
+#define X86_EXTRAREG(x) ((x & X86_EXTRA_REG_OFFSET) == X86_EXTRA_REG_OFFSET)
+#define X86_DOUBLEREG(x) ((x & X86_FP_DOUBLE) == X86_FP_DOUBLE)
+#define X86_SINGLEREG(x) (X86_FPREG(x) && !X86_DOUBLEREG(x))
/*
* Note: the low register of a floating point pair is sufficient to
@@ -125,20 +124,16 @@ namespace art {
* rework is done in this area. Also, it is a good reminder in the calling
* code that reg locations always describe doubles as a pair of singles.
*/
-#define S2D(x,y) ((x) | FP_DOUBLE)
+#define X86_S2D(x,y) ((x) | X86_FP_DOUBLE)
/* Mask to strip off fp flags */
-#define FP_REG_MASK 0xF
-/* non-existent Dalvik register */
-#define vNone (-1)
-/* non-existant physical register */
-#define rNone (-1)
+#define X86_FP_REG_MASK 0xF
/* RegisterLocation templates return values (rAX, rAX/rDX or XMM0) */
// location, wide, defined, const, fp, core, ref, highWord, home, lowReg, highReg, sRegLow
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rAX, INVALID_REG, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rAX, rDX, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_FLOAT {kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, fr0, INVALID_REG, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE_DOUBLE {kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, fr0, fr1, INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, rAX, INVALID_REG, INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, rAX, rDX, INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN_FLOAT {kLocPhysReg, 0, 0, 0, 1, 0, 0, 0, 1, fr0, INVALID_REG, INVALID_SREG, INVALID_SREG}
+#define X86_LOC_C_RETURN_DOUBLE {kLocPhysReg, 1, 0, 0, 1, 0, 0, 0, 1, fr0, fr1, INVALID_SREG, INVALID_SREG}
enum X86ResourceEncodingPos {
kX86GPReg0 = 0,
@@ -155,7 +150,7 @@ enum X86ResourceEncodingPos {
* Annotate special-purpose core registers:
*/
-enum NativeRegisterPool {
+enum X86NativeRegisterPool {
r0 = 0,
rAX = r0,
r1 = 1,
@@ -165,7 +160,7 @@ enum NativeRegisterPool {
r3 = 3,
rBX = r3,
r4sp = 4,
- rSP = r4sp,
+ rX86_SP = r4sp,
r4sib_no_index = r4sp,
r5 = 5,
rBP = r5,
@@ -187,43 +182,44 @@ enum NativeRegisterPool {
r15 = 15,
rRET = 16, // fake return address register for core spill mask
#endif
- fr0 = 0 + FP_REG_OFFSET,
- fr1 = 1 + FP_REG_OFFSET,
- fr2 = 2 + FP_REG_OFFSET,
- fr3 = 3 + FP_REG_OFFSET,
- fr4 = 4 + FP_REG_OFFSET,
- fr5 = 5 + FP_REG_OFFSET,
- fr6 = 6 + FP_REG_OFFSET,
- fr7 = 7 + FP_REG_OFFSET,
- fr8 = 8 + FP_REG_OFFSET,
- fr9 = 9 + FP_REG_OFFSET,
- fr10 = 10 + FP_REG_OFFSET,
- fr11 = 11 + FP_REG_OFFSET,
- fr12 = 12 + FP_REG_OFFSET,
- fr13 = 13 + FP_REG_OFFSET,
- fr14 = 14 + FP_REG_OFFSET,
- fr15 = 15 + FP_REG_OFFSET,
+ fr0 = 0 + X86_FP_REG_OFFSET,
+ fr1 = 1 + X86_FP_REG_OFFSET,
+ fr2 = 2 + X86_FP_REG_OFFSET,
+ fr3 = 3 + X86_FP_REG_OFFSET,
+ fr4 = 4 + X86_FP_REG_OFFSET,
+ fr5 = 5 + X86_FP_REG_OFFSET,
+ fr6 = 6 + X86_FP_REG_OFFSET,
+ fr7 = 7 + X86_FP_REG_OFFSET,
+ fr8 = 8 + X86_FP_REG_OFFSET,
+ fr9 = 9 + X86_FP_REG_OFFSET,
+ fr10 = 10 + X86_FP_REG_OFFSET,
+ fr11 = 11 + X86_FP_REG_OFFSET,
+ fr12 = 12 + X86_FP_REG_OFFSET,
+ fr13 = 13 + X86_FP_REG_OFFSET,
+ fr14 = 14 + X86_FP_REG_OFFSET,
+ fr15 = 15 + X86_FP_REG_OFFSET,
};
/*
* Target-independent aliases
*/
-#define rARG0 rAX
-#define rARG1 rCX
-#define rARG2 rDX
-#define rARG3 rBX
-#define rFARG0 rAX
-#define rFARG1 rCX
-#define rFARG2 rDX
-#define rFARG3 rBX
-#define rRET0 rAX
-#define rRET1 rDX
-#define rINVOKE_TGT rAX
-#define rLR INVALID_REG
-#define rSUSPEND INVALID_REG
-#define rSELF INVALID_REG
-#define rCOUNT rCX
+#define rX86_ARG0 rAX
+#define rX86_ARG1 rCX
+#define rX86_ARG2 rDX
+#define rX86_ARG3 rBX
+#define rX86_FARG0 rAX
+#define rX86_FARG1 rCX
+#define rX86_FARG2 rDX
+#define rX86_FARG3 rBX
+#define rX86_RET0 rAX
+#define rX86_RET1 rDX
+#define rX86_INVOKE_TGT rAX
+#define rX86_LR INVALID_REG
+#define rX86_SUSPEND INVALID_REG
+#define rX86_SELF INVALID_REG
+#define rX86_COUNT rCX
+#define rX86_PC INVALID_REG
#define isPseudoOpcode(opCode) ((int)(opCode) < 0)
diff --git a/src/compiler/codegen/x86/X86RallocUtil.cc b/src/compiler/codegen/x86/X86RallocUtil.cc
index 58ad25ac68..caf4e08977 100644
--- a/src/compiler/codegen/x86/X86RallocUtil.cc
+++ b/src/compiler/codegen/x86/X86RallocUtil.cc
@@ -65,7 +65,7 @@ void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
info1 = info2;
int vReg = SRegToVReg(cUnit, info1->sReg);
- oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg),
+ oatFlushRegWideImpl(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg),
info1->reg, info1->partner);
}
}
@@ -76,17 +76,17 @@ void oatFlushReg(CompilationUnit* cUnit, int reg)
if (info->live && info->dirty) {
info->dirty = false;
int vReg = SRegToVReg(cUnit, info->sReg);
- oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord);
+ oatFlushRegImpl(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
}
}
/* Give access to the target-dependent FP register encoding to common code */
bool oatIsFpReg(int reg) {
- return FPREG(reg);
+ return X86_FPREG(reg);
}
uint32_t oatFpRegMask() {
- return FP_REG_MASK;
+ return X86_FP_REG_MASK;
}
/* Clobber all regs that might be used by an external C call */
@@ -98,7 +98,7 @@ extern void oatClobberCalleeSave(CompilationUnit *cUnit)
}
extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit) {
- RegLocation res = LOC_C_RETURN_WIDE;
+ RegLocation res = locCReturnWide();
CHECK(res.lowReg == rAX);
CHECK(res.highReg == rDX);
oatClobber(cUnit, rAX);
@@ -111,7 +111,7 @@ extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit) {
extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
{
- RegLocation res = LOC_C_RETURN;
+ RegLocation res = locCReturn();
res.lowReg = rDX;
oatClobber(cUnit, rDX);
oatMarkInUse(cUnit, rDX);
@@ -120,26 +120,26 @@ extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
{
- return FPREG(reg) ? &cUnit->regPool->FPRegs[reg & FP_REG_MASK]
+ return X86_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & X86_FP_REG_MASK]
: &cUnit->regPool->coreRegs[reg];
}
/* To be used when explicitly managing register use */
extern void oatLockCallTemps(CompilationUnit* cUnit)
{
- oatLockTemp(cUnit, rARG0);
- oatLockTemp(cUnit, rARG1);
- oatLockTemp(cUnit, rARG2);
- oatLockTemp(cUnit, rARG3);
+ oatLockTemp(cUnit, rX86_ARG0);
+ oatLockTemp(cUnit, rX86_ARG1);
+ oatLockTemp(cUnit, rX86_ARG2);
+ oatLockTemp(cUnit, rX86_ARG3);
}
/* To be used when explicitly managing register use */
extern void oatFreeCallTemps(CompilationUnit* cUnit)
{
- oatFreeTemp(cUnit, rARG0);
- oatFreeTemp(cUnit, rARG1);
- oatFreeTemp(cUnit, rARG2);
- oatFreeTemp(cUnit, rARG3);
+ oatFreeTemp(cUnit, rX86_ARG0);
+ oatFreeTemp(cUnit, rX86_ARG1);
+ oatFreeTemp(cUnit, rX86_ARG2);
+ oatFreeTemp(cUnit, rX86_ARG3);
}
/* Convert an instruction to a NOP */
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-12 17:29:38 +0000