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-rw-r--r--src/compiler/codegen/x86/assemble_x86.cc4
-rw-r--r--src/compiler/codegen/x86/backend_x86.cc7
-rw-r--r--src/compiler/codegen/x86/call_x86.cc10
-rw-r--r--src/compiler/codegen/x86/codegen.h102
-rw-r--r--src/compiler/codegen/x86/fp_x86.cc18
-rw-r--r--src/compiler/codegen/x86/target_x86.cc27
-rw-r--r--src/compiler/codegen/x86/x86_lir.h8
7 files changed, 24 insertions, 152 deletions
diff --git a/src/compiler/codegen/x86/assemble_x86.cc b/src/compiler/codegen/x86/assemble_x86.cc
index 79ed075828..63d2b83a34 100644
--- a/src/compiler/codegen/x86/assemble_x86.cc
+++ b/src/compiler/codegen/x86/assemble_x86.cc
@@ -14,10 +14,8 @@
* limitations under the License.
*/
-#include "../../dalvik.h"
-#include "../../compiler_internals.h"
#include "x86_lir.h"
-#include "codegen.h"
+#include "../codegen_util.h"
namespace art {
diff --git a/src/compiler/codegen/x86/backend_x86.cc b/src/compiler/codegen/x86/backend_x86.cc
index 6abfb23b09..13388ff9b4 100644
--- a/src/compiler/codegen/x86/backend_x86.cc
+++ b/src/compiler/codegen/x86/backend_x86.cc
@@ -16,17 +16,14 @@
#define _CODEGEN_C
-#include "../../dalvik.h"
-#include "../../compiler_internals.h"
#include "x86_lir.h"
-#include "../ralloc.h"
-#include "codegen.h"
+#include "../ralloc_util.h"
/* Common codegen utility code */
#include "../codegen_util.cc"
#include "utility_x86.cc"
-#include "../codegen_factory.cc"
+#include "../gen_loadstore.cc"
#include "../gen_common.cc"
#include "../gen_invoke.cc"
#include "call_x86.cc"
diff --git a/src/compiler/codegen/x86/call_x86.cc b/src/compiler/codegen/x86/call_x86.cc
index 0cd9b2da2d..2b52270724 100644
--- a/src/compiler/codegen/x86/call_x86.cc
+++ b/src/compiler/codegen/x86/call_x86.cc
@@ -33,7 +33,7 @@ BasicBlock *findBlock(CompilationUnit* cUnit, unsigned int codeOffset,
void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
RegLocation rlSrc)
{
- const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+ const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
dumpSparseSwitchTable(table);
}
@@ -71,7 +71,7 @@ void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
void genPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
RegLocation rlSrc)
{
- const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+ const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
dumpPackedSwitchTable(table);
}
@@ -134,14 +134,14 @@ void callRuntimeHelperRegReg(CompilationUnit* cUnit, int helperOffset,
void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
RegLocation rlSrc)
{
- const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
+ const uint16_t* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
// Add the table to the list - we'll process it later
FillArrayData *tabRec = (FillArrayData *)oatNew(cUnit, sizeof(FillArrayData),
true, kAllocData);
tabRec->table = table;
tabRec->vaddr = cUnit->currentDalvikOffset;
- u2 width = tabRec->table[1];
- u4 size = tabRec->table[2] | (((u4)tabRec->table[3]) << 16);
+ uint16_t width = tabRec->table[1];
+ uint32_t size = tabRec->table[2] | ((static_cast<uint32_t>(tabRec->table[3])) << 16);
tabRec->size = (size * width) + 8;
oatInsertGrowableList(cUnit, &cUnit->fillArrayData, (intptr_t)tabRec);
diff --git a/src/compiler/codegen/x86/codegen.h b/src/compiler/codegen/x86/codegen.h
deleted file mode 100644
index c95fa672ac..0000000000
--- a/src/compiler/codegen/x86/codegen.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Copyright (C) 2012 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-/* This file contains register alloction support */
-
-#include "../../compiler_ir.h"
-
-namespace art {
-
-#if defined(_CODEGEN_C)
-bool genAddLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2);
-bool genSubLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2);
-bool genAndLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2);
-bool genOrLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2);
-bool genXorLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2);
-bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
- RegLocation rlSrc);
-LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
-LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
-LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
- int src2, LIR* target);
-LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
- int checkValue, LIR* target);
-
-/* Forward declaration of the portable versions due to circular dependency */
-bool genArithOpFloatPortable(CompilationUnit* cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc1,
- RegLocation rlSrc2);
-
-bool genArithOpDoublePortable(CompilationUnit* cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc1,
- RegLocation rlSrc2);
-
-bool genConversionPortable(CompilationUnit* cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc);
-
-int loadHelper(CompilationUnit* cUnit, int offset);
-LIR* loadConstant(CompilationUnit* cUnit, int reg, int immVal);
-void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
- int srcLo, int srcHi);
-LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc);
-void freeRegLocTemps(CompilationUnit* cUnit, RegLocation rlKeep,
- RegLocation rlFree);
-
-
-/*
- * Return most flexible allowed register class based on size.
- * Bug: 2813841
- * Must use a core register for data types narrower than word (due
- * to possible unaligned load/store.
- */
-inline RegisterClass oatRegClassBySize(OpSize size)
-{
- return (size == kUnsignedHalf ||
- size == kSignedHalf ||
- size == kUnsignedByte ||
- size == kSignedByte ) ? kCoreReg : kAnyReg;
-}
-
-/*
- * Construct an s4 from two consecutive half-words of switch data.
- * This needs to check endianness because the DEX optimizer only swaps
- * half-words in instruction stream.
- *
- * "switchData" must be 32-bit aligned.
- */
-#if __BYTE_ORDER == __LITTLE_ENDIAN
-inline s4 s4FromSwitchData(const void* switchData) {
- return *(s4*) switchData;
-}
-#else
-inline s4 s4FromSwitchData(const void* switchData) {
- u2* data = switchData;
- return data[0] | (((s4) data[1]) << 16);
-}
-#endif
-
-#endif
-
-extern void oatSetupResourceMasks(CompilationUnit* cUnit, LIR* lir);
-
-extern LIR* oatRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc);
-
-} // namespace art
diff --git a/src/compiler/codegen/x86/fp_x86.cc b/src/compiler/codegen/x86/fp_x86.cc
index 0a08ab0b4c..411bd1e381 100644
--- a/src/compiler/codegen/x86/fp_x86.cc
+++ b/src/compiler/codegen/x86/fp_x86.cc
@@ -16,9 +16,8 @@
namespace art {
-static bool genArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc1,
- RegLocation rlSrc2) {
+bool genArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2) {
X86OpCode op = kX86Nop;
RegLocation rlResult;
@@ -67,9 +66,8 @@ static bool genArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode,
return false;
}
-static bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc1,
- RegLocation rlSrc2) {
+bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2) {
X86OpCode op = kX86Nop;
RegLocation rlResult;
@@ -117,8 +115,8 @@ static bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
return false;
}
-static bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
- RegLocation rlDest, RegLocation rlSrc) {
+bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc) {
RegisterClass rcSrc = kFPReg;
X86OpCode op = kX86Nop;
int srcReg;
@@ -210,8 +208,8 @@ static bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
return false;
}
-static bool genCmpFP(CompilationUnit *cUnit, Instruction::Code code, RegLocation rlDest,
- RegLocation rlSrc1, RegLocation rlSrc2) {
+bool genCmpFP(CompilationUnit *cUnit, Instruction::Code code, RegLocation rlDest,
+ RegLocation rlSrc1, RegLocation rlSrc2) {
bool single = (code == Instruction::CMPL_FLOAT) || (code == Instruction::CMPG_FLOAT);
bool unorderedGt = (code == Instruction::CMPG_DOUBLE) || (code == Instruction::CMPG_FLOAT);
int srcReg1;
diff --git a/src/compiler/codegen/x86/target_x86.cc b/src/compiler/codegen/x86/target_x86.cc
index a211c2fe0e..a254876e60 100644
--- a/src/compiler/codegen/x86/target_x86.cc
+++ b/src/compiler/codegen/x86/target_x86.cc
@@ -16,7 +16,8 @@
#include "../../compiler_internals.h"
#include "x86_lir.h"
-#include "../ralloc.h"
+#include "../ralloc_util.h"
+#include "../codegen_util.h"
#include <string>
@@ -132,9 +133,9 @@ bool sameRegType(int reg1, int reg2)
/*
* Decode the register id.
*/
-u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
+uint64_t getRegMaskCommon(CompilationUnit* cUnit, int reg)
{
- u8 seed;
+ uint64_t seed;
int shift;
int regId;
@@ -280,7 +281,7 @@ std::string buildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
return buf;
}
-void oatDumpResourceMask(LIR *lir, u8 mask, const char *prefix)
+void oatDumpResourceMask(LIR *lir, uint64_t mask, const char *prefix)
{
char buf[256];
buf[0] = 0;
@@ -360,8 +361,7 @@ void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
info1 = info2;
int vReg = SRegToVReg(cUnit, info1->sReg);
- oatFlushRegWideImpl(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg),
- info1->reg, info1->partner);
+ storeBaseDispWide(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg), info1->reg, info1->partner);
}
}
@@ -371,7 +371,7 @@ void oatFlushReg(CompilationUnit* cUnit, int reg)
if (info->live && info->dirty) {
info->dirty = false;
int vReg = SRegToVReg(cUnit, info->sReg);
- oatFlushRegImpl(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
+ storeBaseDisp(cUnit, rX86_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
}
}
@@ -458,19 +458,6 @@ bool oatArchVariantInit(void)
return true;
}
-int dvmCompilerTargetOptHint(int key)
-{
- int res;
- switch (key) {
- case kMaxHoistDistance:
- res = 2;
- break;
- default:
- LOG(FATAL) << "Unknown target optimization hint key: " << key;
- }
- return res;
-}
-
void oatGenMemBarrier(CompilationUnit *cUnit, int /* barrierKind */)
{
#if ANDROID_SMP != 0
diff --git a/src/compiler/codegen/x86/x86_lir.h b/src/compiler/codegen/x86/x86_lir.h
index fe6d8cb338..3008bc259c 100644
--- a/src/compiler/codegen/x86/x86_lir.h
+++ b/src/compiler/codegen/x86/x86_lir.h
@@ -17,7 +17,6 @@
#ifndef ART_COMPILER_COMPILER_CODEGEN_X86_X86LIR_H_
#define ART_COMPILER_COMPILER_CODEGEN_X86_X86LIR_H_
-#include "../../dalvik.h"
#include "../../compiler_internals.h"
namespace art {
@@ -143,7 +142,7 @@ enum X86ResourceEncodingPos {
kX86RegEnd = kX86FPRegEnd,
};
-#define ENCODE_X86_REG_LIST(N) ((u8) N)
+#define ENCODE_X86_REG_LIST(N) (static_cast<uint64_t>(N))
#define ENCODE_X86_REG_SP (1ULL << kX86RegSP)
/*
@@ -436,11 +435,6 @@ extern X86EncodingMap EncodingMap[kX86Last];
#define kSY 0
#define kST 0
-/* Keys for target-specific scheduling and other optimization hints */
-enum X86TargetOptHints {
- kMaxHoistDistance,
-};
-
/* Offsets of high and low halves of a 64bit value */
#define LOWORD_OFFSET 0
#define HIWORD_OFFSET 4
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-15 21:10:03 +0000