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-rw-r--r--src/compiler/codegen/mips/ArchFactory.cc42
-rw-r--r--src/compiler/codegen/mips/ArchUtility.cc95
-rw-r--r--src/compiler/codegen/mips/Assemble.cc8
-rw-r--r--src/compiler/codegen/mips/FP/MipsFP.cc18
-rw-r--r--src/compiler/codegen/mips/Mips32/Factory.cc50
-rw-r--r--src/compiler/codegen/mips/Mips32/Gen.cc30
-rw-r--r--src/compiler/codegen/mips/Mips32/Ralloc.cc2
-rw-r--r--src/compiler/codegen/mips/MipsLIR.h114
-rw-r--r--src/compiler/codegen/mips/MipsRallocUtil.cc30
9 files changed, 235 insertions, 154 deletions
diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index e5dc98f0be..90c0ede67b 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -99,7 +99,7 @@ bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
*/
int loadHelper(CompilationUnit* cUnit, int offset)
{
- loadWordDisp(cUnit, rSELF, offset, r_T9);
+ loadWordDisp(cUnit, rMIPS_SELF, offset, r_T9);
return r_T9;
}
@@ -110,11 +110,11 @@ void spillCoreRegs(CompilationUnit* cUnit)
}
uint32_t mask = cUnit->coreSpillMask;
int offset = cUnit->numCoreSpills * 4;
- opRegImm(cUnit, kOpSub, rSP, offset);
+ opRegImm(cUnit, kOpSub, rMIPS_SP, offset);
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- storeWordDisp(cUnit, rSP, offset, reg);
+ storeWordDisp(cUnit, rMIPS_SP, offset, reg);
}
}
}
@@ -129,10 +129,10 @@ void unSpillCoreRegs(CompilationUnit* cUnit)
for (int reg = 0; mask; mask >>= 1, reg++) {
if (mask & 0x1) {
offset -= 4;
- loadWordDisp(cUnit, rSP, offset, reg);
+ loadWordDisp(cUnit, rMIPS_SP, offset, reg);
}
}
- opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize);
+ opRegImm(cUnit, kOpAdd, rMIPS_SP, cUnit->frameSize);
}
void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
@@ -140,15 +140,15 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
{
int spillCount = cUnit->numCoreSpills + cUnit->numFPSpills;
/*
- * On entry, rARG0, rARG1, rARG2 & rARG3 are live. Let the register
+ * On entry, rMIPS_ARG0, rMIPS_ARG1, rMIPS_ARG2 & rMIPS_ARG3 are live. Let the register
* allocation mechanism know so it doesn't try to use any of them when
* expanding the frame or flushing. This leaves the utility
* code with a single temp: r12. This should be enough.
*/
- oatLockTemp(cUnit, rARG0);
- oatLockTemp(cUnit, rARG1);
- oatLockTemp(cUnit, rARG2);
- oatLockTemp(cUnit, rARG3);
+ oatLockTemp(cUnit, rMIPS_ARG0);
+ oatLockTemp(cUnit, rMIPS_ARG1);
+ oatLockTemp(cUnit, rMIPS_ARG2);
+ oatLockTemp(cUnit, rMIPS_ARG3);
/*
* We can safely skip the stack overflow check if we're
@@ -161,36 +161,36 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
int newSP = oatAllocTemp(cUnit);
if (!skipOverflowCheck) {
/* Load stack limit */
- loadWordDisp(cUnit, rSELF, Thread::StackEndOffset().Int32Value(), checkReg);
+ loadWordDisp(cUnit, rMIPS_SELF, Thread::StackEndOffset().Int32Value(), checkReg);
}
/* Spill core callee saves */
spillCoreRegs(cUnit);
/* NOTE: promotion of FP regs currently unsupported, thus no FP spill */
DCHECK_EQ(cUnit->numFPSpills, 0);
if (!skipOverflowCheck) {
- opRegRegImm(cUnit, kOpSub, newSP, rSP, cUnit->frameSize - (spillCount * 4));
+ opRegRegImm(cUnit, kOpSub, newSP, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
genRegRegCheck(cUnit, kCondCc, newSP, checkReg, kThrowStackOverflow);
- opRegCopy(cUnit, rSP, newSP); // Establish stack
+ opRegCopy(cUnit, rMIPS_SP, newSP); // Establish stack
} else {
- opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4));
+ opRegImm(cUnit, kOpSub, rMIPS_SP, cUnit->frameSize - (spillCount * 4));
}
flushIns(cUnit, argLocs, rlMethod);
- oatFreeTemp(cUnit, rARG0);
- oatFreeTemp(cUnit, rARG1);
- oatFreeTemp(cUnit, rARG2);
- oatFreeTemp(cUnit, rARG3);
+ oatFreeTemp(cUnit, rMIPS_ARG0);
+ oatFreeTemp(cUnit, rMIPS_ARG1);
+ oatFreeTemp(cUnit, rMIPS_ARG2);
+ oatFreeTemp(cUnit, rMIPS_ARG3);
}
void genExitSequence(CompilationUnit* cUnit)
{
/*
- * In the exit path, rRET0/rRET1 are live - make sure they aren't
+ * In the exit path, rMIPS_RET0/rMIPS_RET1 are live - make sure they aren't
* allocated by the register utilities as temps.
*/
- oatLockTemp(cUnit, rRET0);
- oatLockTemp(cUnit, rRET1);
+ oatLockTemp(cUnit, rMIPS_RET0);
+ oatLockTemp(cUnit, rMIPS_RET1);
newLIR0(cUnit, kPseudoMethodExit);
unSpillCoreRegs(cUnit);
diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index 9a2b923baf..3063e69518 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -22,6 +22,91 @@
namespace art {
+RegLocation locCReturn()
+{
+ RegLocation res = MIPS_LOC_C_RETURN;
+ return res;
+}
+
+RegLocation locCReturnWide()
+{
+ RegLocation res = MIPS_LOC_C_RETURN_WIDE;
+ return res;
+}
+
+RegLocation locCReturnFloat()
+{
+ RegLocation res = MIPS_LOC_C_RETURN_FLOAT;
+ return res;
+}
+
+RegLocation locCReturnDouble()
+{
+ RegLocation res = MIPS_LOC_C_RETURN_DOUBLE;
+ return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+ int res = INVALID_REG;
+ switch (reg) {
+ case kSelf: res = rMIPS_SELF; break;
+ case kSuspend: res = rMIPS_SUSPEND; break;
+ case kLr: res = rMIPS_LR; break;
+ case kPc: res = rMIPS_PC; break;
+ case kSp: res = rMIPS_SP; break;
+ case kArg0: res = rMIPS_ARG0; break;
+ case kArg1: res = rMIPS_ARG1; break;
+ case kArg2: res = rMIPS_ARG2; break;
+ case kArg3: res = rMIPS_ARG3; break;
+ case kFArg0: res = rMIPS_FARG0; break;
+ case kFArg1: res = rMIPS_FARG1; break;
+ case kFArg2: res = rMIPS_FARG2; break;
+ case kFArg3: res = rMIPS_FARG3; break;
+ case kRet0: res = rMIPS_RET0; break;
+ case kRet1: res = rMIPS_RET1; break;
+ case kInvokeTgt: res = rMIPS_INVOKE_TGT; break;
+ case kCount: res = rMIPS_COUNT; break;
+ }
+ return res;
+}
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+ return MIPS_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+ return MIPS_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+ return MIPS_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+ return MIPS_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+ return MIPS_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+ return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
+}
+
/*
* Decode the register id.
*/
@@ -34,9 +119,9 @@ u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
regId = reg & 0x1f;
/* Each double register is equal to a pair of single-precision FP registers */
- seed = DOUBLEREG(reg) ? 3 : 1;
+ seed = MIPS_DOUBLEREG(reg) ? 3 : 1;
/* FP register starts at bit position 16 */
- shift = FPREG(reg) ? kMipsFPReg0 : 0;
+ shift = MIPS_FPREG(reg) ? kMipsFPReg0 : 0;
/* Expand the double register id into single offset */
shift += regId;
return (seed << shift);
@@ -109,11 +194,11 @@ std::string buildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
}
break;
case 's':
- sprintf(tbuf,"$f%d",operand & FP_REG_MASK);
+ sprintf(tbuf,"$f%d",operand & MIPS_FP_REG_MASK);
break;
case 'S':
- DCHECK_EQ(((operand & FP_REG_MASK) & 1), 0);
- sprintf(tbuf,"$f%d",operand & FP_REG_MASK);
+ DCHECK_EQ(((operand & MIPS_FP_REG_MASK) & 1), 0);
+ sprintf(tbuf,"$f%d",operand & MIPS_FP_REG_MASK);
break;
case 'h':
sprintf(tbuf,"%04x", operand);
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 9f8a68638f..e9dd2197e3 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -677,16 +677,16 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,
bits |= (value << encoder->fieldLoc[i].end);
break;
case kFmtDfp: {
- DCHECK(DOUBLEREG(operand));
+ DCHECK(MIPS_DOUBLEREG(operand));
DCHECK_EQ((operand & 0x1), 0U);
- value = ((operand & FP_REG_MASK) << encoder->fieldLoc[i].start) &
+ value = ((operand & MIPS_FP_REG_MASK) << encoder->fieldLoc[i].start) &
((1 << (encoder->fieldLoc[i].end + 1)) - 1);
bits |= value;
break;
}
case kFmtSfp:
- DCHECK(SINGLEREG(operand));
- value = ((operand & FP_REG_MASK) << encoder->fieldLoc[i].start) &
+ DCHECK(MIPS_SINGLEREG(operand));
+ value = ((operand & MIPS_FP_REG_MASK) << encoder->fieldLoc[i].start) &
((1 << (encoder->fieldLoc[i].end + 1)) - 1);
bits |= value;
break;
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index 990c71f232..fb6c8df9e6 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -107,9 +107,9 @@ static bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
DCHECK(rlDest.wide);
DCHECK(rlResult.wide);
- newLIR3(cUnit, (MipsOpCode)op, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlSrc1.lowReg, rlSrc1.highReg),
- S2D(rlSrc2.lowReg, rlSrc2.highReg));
+ newLIR3(cUnit, (MipsOpCode)op, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlSrc1.lowReg, rlSrc1.highReg),
+ s2d(rlSrc2.lowReg, rlSrc2.highReg));
storeValueWide(cUnit, rlDest, rlResult);
return false;
#else
@@ -149,14 +149,14 @@ static bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
}
if (rlSrc.wide) {
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
+ srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
} else {
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
if (rlDest.wide) {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, (MipsOpCode)op, S2D(rlResult.lowReg, rlResult.highReg),
+ newLIR2(cUnit, (MipsOpCode)op, s2d(rlResult.lowReg, rlResult.highReg),
srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
@@ -197,11 +197,11 @@ static bool genCmpFP(CompilationUnit *cUnit, Instruction::Code opcode, RegLocati
oatFlushAllRegs(cUnit);
oatLockCallTemps(cUnit);
if (wide) {
- loadValueDirectWideFixed(cUnit, rlSrc1, rFARG0, rFARG1);
- loadValueDirectWideFixed(cUnit, rlSrc2, rFARG2, rFARG3);
+ loadValueDirectWideFixed(cUnit, rlSrc1, rMIPS_FARG0, rMIPS_FARG1);
+ loadValueDirectWideFixed(cUnit, rlSrc2, rMIPS_FARG2, rMIPS_FARG3);
} else {
- loadValueDirectFixed(cUnit, rlSrc1, rFARG0);
- loadValueDirectFixed(cUnit, rlSrc2, rFARG2);
+ loadValueDirectFixed(cUnit, rlSrc1, rMIPS_FARG0);
+ loadValueDirectFixed(cUnit, rlSrc2, rMIPS_FARG2);
}
int rTgt = loadHelper(cUnit, offset);
// NOTE: not a safepoint
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index 2f0d46024b..0a0d906538 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -46,12 +46,12 @@ LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
{
int opcode;
/* must be both DOUBLE or both not DOUBLE */
- DCHECK_EQ(DOUBLEREG(rDest),DOUBLEREG(rSrc));
- if (DOUBLEREG(rDest)) {
+ DCHECK_EQ(MIPS_DOUBLEREG(rDest),MIPS_DOUBLEREG(rSrc));
+ if (MIPS_DOUBLEREG(rDest)) {
opcode = kMipsFmovd;
} else {
- if (SINGLEREG(rDest)) {
- if (SINGLEREG(rSrc)) {
+ if (MIPS_SINGLEREG(rDest)) {
+ if (MIPS_SINGLEREG(rSrc)) {
opcode = kMipsFmovs;
} else {
/* note the operands are swapped for the mtc1 instr */
@@ -61,7 +61,7 @@ LIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc)
opcode = kMipsMtc1;
}
} else {
- DCHECK(SINGLEREG(rSrc));
+ DCHECK(MIPS_SINGLEREG(rSrc));
opcode = kMipsMfc1;
}
}
@@ -88,9 +88,9 @@ LIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, int value)
#ifdef __mips_hard_float
int rDestSave = rDest;
- int isFpReg = FPREG(rDest);
+ int isFpReg = MIPS_FPREG(rDest);
if (isFpReg) {
- DCHECK(SINGLEREG(rDest));
+ DCHECK(MIPS_SINGLEREG(rDest));
rDest = oatAllocTemp(cUnit);
}
#endif
@@ -372,8 +372,8 @@ LIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase,
int tReg = oatAllocTemp(cUnit);
#ifdef __mips_hard_float
- if (FPREG(rDest)) {
- DCHECK(SINGLEREG(rDest));
+ if (MIPS_FPREG(rDest)) {
+ DCHECK(MIPS_SINGLEREG(rDest));
DCHECK((size == kWord) || (size == kSingle));
size = kSingle;
} else {
@@ -429,8 +429,8 @@ LIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase,
int tReg = oatAllocTemp(cUnit);
#ifdef __mips_hard_float
- if (FPREG(rSrc)) {
- DCHECK(SINGLEREG(rSrc));
+ if (MIPS_FPREG(rSrc)) {
+ DCHECK(MIPS_SINGLEREG(rSrc));
DCHECK((size == kWord) || (size == kSingle));
size = kSingle;
} else {
@@ -540,12 +540,12 @@ LIR *loadBaseDispBody(CompilationUnit *cUnit, int rBase,
pair = true;
opcode = kMipsLw;
#ifdef __mips_hard_float
- if (FPREG(rDest)) {
+ if (MIPS_FPREG(rDest)) {
opcode = kMipsFlwc1;
- if (DOUBLEREG(rDest)) {
- rDest = rDest - FP_DOUBLE;
+ if (MIPS_DOUBLEREG(rDest)) {
+ rDest = rDest - MIPS_FP_DOUBLE;
} else {
- DCHECK(FPREG(rDestHi));
+ DCHECK(MIPS_FPREG(rDestHi));
DCHECK(rDest == (rDestHi - 1));
}
rDestHi = rDest + 1;
@@ -558,9 +558,9 @@ LIR *loadBaseDispBody(CompilationUnit *cUnit, int rBase,
case kSingle:
opcode = kMipsLw;
#ifdef __mips_hard_float
- if (FPREG(rDest)) {
+ if (MIPS_FPREG(rDest)) {
opcode = kMipsFlwc1;
- DCHECK(SINGLEREG(rDest));
+ DCHECK(MIPS_SINGLEREG(rDest));
}
#endif
DCHECK_EQ((displacement & 0x3), 0);
@@ -608,7 +608,7 @@ LIR *loadBaseDispBody(CompilationUnit *cUnit, int rBase,
}
}
- if (rBase == rSP) {
+ if (rBase == rMIPS_SP) {
annotateDalvikRegAccess(load,
(displacement + (pair ? LOWORD_OFFSET : 0)) >> 2,
true /* isLoad */, pair /* is64bit */);
@@ -650,12 +650,12 @@ LIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
pair = true;
opcode = kMipsSw;
#ifdef __mips_hard_float
- if (FPREG(rSrc)) {
+ if (MIPS_FPREG(rSrc)) {
opcode = kMipsFswc1;
- if (DOUBLEREG(rSrc)) {
- rSrc = rSrc - FP_DOUBLE;
+ if (MIPS_DOUBLEREG(rSrc)) {
+ rSrc = rSrc - MIPS_FP_DOUBLE;
} else {
- DCHECK(FPREG(rSrcHi));
+ DCHECK(MIPS_FPREG(rSrcHi));
DCHECK_EQ(rSrc, (rSrcHi - 1));
}
rSrcHi = rSrc + 1;
@@ -668,9 +668,9 @@ LIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
case kSingle:
opcode = kMipsSw;
#ifdef __mips_hard_float
- if (FPREG(rSrc)) {
+ if (MIPS_FPREG(rSrc)) {
opcode = kMipsFswc1;
- DCHECK(SINGLEREG(rSrc));
+ DCHECK(MIPS_SINGLEREG(rSrc));
}
#endif
DCHECK_EQ((displacement & 0x3), 0);
@@ -709,7 +709,7 @@ LIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase,
oatFreeTemp(cUnit, rScratch);
}
- if (rBase == rSP) {
+ if (rBase == rMIPS_SP) {
annotateDalvikRegAccess(store, (displacement + (pair ? LOWORD_OFFSET : 0))
>> 2, false /* isLoad */, pair /* is64bit */);
if (pair) {
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index 22c8b84e5b..a772c09643 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -238,7 +238,7 @@ void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
// Making a call - use explicit registers
oatFlushAllRegs(cUnit); /* Everything to home location */
oatLockCallTemps(cUnit);
- loadValueDirectFixed(cUnit, rlSrc, rARG0);
+ loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0);
// Must prevent code motion for the curr pc pair
genBarrier(cUnit);
@@ -251,7 +251,7 @@ void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
LIR* baseLabel = newLIR0(cUnit, kPseudoTargetLabel);
// Materialize a pointer to the fill data image
- newLIR4(cUnit, kMipsDelta, rARG1, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
+ newLIR4(cUnit, kMipsDelta, rMIPS_ARG1, 0, (intptr_t)baseLabel, (intptr_t)tabRec);
// And go...
oatClobberCalleeSave(cUnit);
@@ -284,9 +284,9 @@ void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
oatFlushAllRegs(cUnit);
- loadValueDirectFixed(cUnit, rlSrc, rARG0); // Get obj
+ loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, rARG0, optFlags);
+ genNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
// Go expensive route - artLockObjectFromCode(self, obj);
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pLockObjectFromCode));
oatClobberCalleeSave(cUnit);
@@ -300,9 +300,9 @@ void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
oatFlushAllRegs(cUnit);
- loadValueDirectFixed(cUnit, rlSrc, rARG0); // Get obj
+ loadValueDirectFixed(cUnit, rlSrc, rMIPS_ARG0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, rARG0, optFlags);
+ genNullCheck(cUnit, rlSrc.sRegLow, rMIPS_ARG0, optFlags);
// Go expensive route - UnlockObjectFromCode(obj);
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
oatClobberCalleeSave(cUnit);
@@ -453,7 +453,7 @@ LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
LIR* opRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc)
{
#ifdef __mips_hard_float
- if (FPREG(rDest) || FPREG(rSrc))
+ if (MIPS_FPREG(rDest) || MIPS_FPREG(rSrc))
return fpRegCopy(cUnit, rDest, rSrc);
#endif
LIR* res = rawLIR(cUnit, cUnit->currentDalvikOffset, kMipsMove,
@@ -475,13 +475,13 @@ void opRegCopyWide(CompilationUnit *cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
#ifdef __mips_hard_float
- bool destFP = FPREG(destLo) && FPREG(destHi);
- bool srcFP = FPREG(srcLo) && FPREG(srcHi);
- assert(FPREG(srcLo) == FPREG(srcHi));
- assert(FPREG(destLo) == FPREG(destHi));
+ bool destFP = MIPS_FPREG(destLo) && MIPS_FPREG(destHi);
+ bool srcFP = MIPS_FPREG(srcLo) && MIPS_FPREG(srcHi);
+ assert(MIPS_FPREG(srcLo) == MIPS_FPREG(srcHi));
+ assert(MIPS_FPREG(destLo) == MIPS_FPREG(destHi));
if (destFP) {
if (srcFP) {
- opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
} else {
/* note the operands are swapped for the mtc1 instr */
newLIR2(cUnit, kMipsMtc1, srcLo, destLo);
@@ -561,7 +561,7 @@ void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
int regCardBase = oatAllocTemp(cUnit);
int regCardNo = oatAllocTemp(cUnit);
LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
- loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(), regCardBase);
+ loadWordDisp(cUnit, rMIPS_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
kUnsignedByte);
@@ -638,8 +638,8 @@ void genDivZeroCheck(CompilationUnit* cUnit, int regLo, int regHi)
// Test suspend flag, return target of taken suspend branch
LIR* opTestSuspend(CompilationUnit* cUnit, LIR* target)
{
- opRegImm(cUnit, kOpSub, rSUSPEND, 1);
- return opCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rSUSPEND, 0, target);
+ opRegImm(cUnit, kOpSub, rMIPS_SUSPEND, 1);
+ return opCmpImmBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, rMIPS_SUSPEND, 0, target);
}
// Decrement register and branch on condition
diff --git a/src/compiler/codegen/mips/Mips32/Ralloc.cc b/src/compiler/codegen/mips/Mips32/Ralloc.cc
index e7ad60c838..b913bfb0f3 100644
--- a/src/compiler/codegen/mips/Mips32/Ralloc.cc
+++ b/src/compiler/codegen/mips/Mips32/Ralloc.cc
@@ -82,7 +82,7 @@ void oatInitializeRegAlloc(CompilationUnit* cUnit)
oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
// Keep special registers from being allocated
for (int i = 0; i < numReserved; i++) {
- if (NO_SUSPEND && (reservedRegs[i] == rSUSPEND)) {
+ if (NO_SUSPEND && (reservedRegs[i] == rMIPS_SUSPEND)) {
//To measure cost of suspend check
continue;
}
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index b8e5801651..c0fde466c1 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -31,8 +31,8 @@ namespace art {
* a0-a3 are scratch (normally hold subroutine arguments)
* t0-t8 are scratch
* t9 is scratch (normally used for function calls)
- * s0 (rSUSPEND) is reserved [holds suspend-check counter]
- * s1 (rSELF) is reserved [holds current &Thread]
+ * s0 (rMIPS_SUSPEND) is reserved [holds suspend-check counter]
+ * s1 (rMIPS_SELF) is reserved [holds current &Thread]
* s2-s7 are callee save (promotion target)
* k0, k1 are reserved for use by interrupt handlers
* gp is reserved for global pointer
@@ -88,18 +88,17 @@ namespace art {
*/
/* Offset to distingish FP regs */
-#define FP_REG_OFFSET 32
+#define MIPS_FP_REG_OFFSET 32
/* Offset to distinguish DP FP regs */
-#define FP_DOUBLE 64
+#define MIPS_FP_DOUBLE 64
/* Offset to distingish the extra regs */
-#define EXTRA_REG_OFFSET 128
+#define MIPS_EXTRA_REG_OFFSET 128
/* Reg types */
-#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
-#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)
-#define EXTRAREG(x) ((x & EXTRA_REG_OFFSET) == EXTRA_REG_OFFSET)
-#define LOWREG(x) ((x & 0x1f) == x)
-#define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE)
-#define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x))
+#define MIPS_REGTYPE(x) (x & (MIPS_FP_REG_OFFSET | MIPS_FP_DOUBLE))
+#define MIPS_FPREG(x) ((x & MIPS_FP_REG_OFFSET) == MIPS_FP_REG_OFFSET)
+#define MIPS_EXTRAREG(x) ((x & MIPS_EXTRA_REG_OFFSET) == MIPS_EXTRA_REG_OFFSET)
+#define MIPS_DOUBLEREG(x) ((x & MIPS_FP_DOUBLE) == MIPS_FP_DOUBLE)
+#define MIPS_SINGLEREG(x) (MIPS_FPREG(x) && !MIPS_DOUBLEREG(x))
/*
* Note: the low register of a floating point pair is sufficient to
* create the name of a double, but require both names to be passed to
@@ -107,13 +106,9 @@ namespace art {
* rework is done in this area. Also, it is a good reminder in the calling
* code that reg locations always describe doubles as a pair of singles.
*/
-#define S2D(x,y) ((x) | FP_DOUBLE)
+#define MIPS_S2D(x,y) ((x) | MIPS_FP_DOUBLE)
/* Mask to strip off fp flags */
-#define FP_REG_MASK (FP_REG_OFFSET-1)
-/* non-existent Dalvik register */
-#define vNone (-1)
-/* non-existant physical register */
-#define rNone (-1)
+#define MIPS_FP_REG_MASK (MIPS_FP_REG_OFFSET-1)
#ifdef HAVE_LITTLE_ENDIAN
#define LOWORD_OFFSET 0
@@ -144,16 +139,17 @@ namespace art {
#define r_FRESULT1 r_F1
/* Regs not used for Mips */
-#define rLR INVALID_REG
+#define rMIPS_LR INVALID_REG
+#define rMIPS_PC INVALID_REG
/* RegisterLocation templates return values (r_V0, or r_V0/r_V1) */
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \
- INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_FLOAT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0, \
- INVALID_REG, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_RESULT0, \
- r_RESULT1, INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE_DOUBLE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0,\
+#define MIPS_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_V0, INVALID_REG, \
+ INVALID_SREG, INVALID_SREG}
+#define MIPS_LOC_C_RETURN_FLOAT {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0, \
+ INVALID_REG, INVALID_SREG, INVALID_SREG}
+#define MIPS_LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_RESULT0, \
+ r_RESULT1, INVALID_SREG, INVALID_SREG}
+#define MIPS_LOC_C_RETURN_DOUBLE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r_FRESULT0,\
r_FRESULT1, INVALID_SREG, INVALID_SREG}
enum MipsResourceEncodingPos {
@@ -177,7 +173,7 @@ enum MipsResourceEncodingPos {
* Annotate special-purpose core registers:
*/
-enum NativeRegisterPool {
+enum MipsNativeRegisterPool {
r_ZERO = 0,
r_AT = 1,
r_V0 = 2,
@@ -211,7 +207,7 @@ enum NativeRegisterPool {
r_FP = 30,
r_RA = 31,
- r_F0 = 0 + FP_REG_OFFSET,
+ r_F0 = 0 + MIPS_FP_REG_OFFSET,
r_F1,
r_F2,
r_F3,
@@ -245,25 +241,25 @@ enum NativeRegisterPool {
r_F30,
r_F31,
#endif
- r_DF0 = r_F0 + FP_DOUBLE,
- r_DF1 = r_F2 + FP_DOUBLE,
- r_DF2 = r_F4 + FP_DOUBLE,
- r_DF3 = r_F6 + FP_DOUBLE,
- r_DF4 = r_F8 + FP_DOUBLE,
- r_DF5 = r_F10 + FP_DOUBLE,
- r_DF6 = r_F12 + FP_DOUBLE,
- r_DF7 = r_F14 + FP_DOUBLE,
+ r_DF0 = r_F0 + MIPS_FP_DOUBLE,
+ r_DF1 = r_F2 + MIPS_FP_DOUBLE,
+ r_DF2 = r_F4 + MIPS_FP_DOUBLE,
+ r_DF3 = r_F6 + MIPS_FP_DOUBLE,
+ r_DF4 = r_F8 + MIPS_FP_DOUBLE,
+ r_DF5 = r_F10 + MIPS_FP_DOUBLE,
+ r_DF6 = r_F12 + MIPS_FP_DOUBLE,
+ r_DF7 = r_F14 + MIPS_FP_DOUBLE,
#if 0 /* only 16 fp regs supported currently */
- r_DF8 = r_F16 + FP_DOUBLE,
- r_DF9 = r_F18 + FP_DOUBLE,
- r_DF10 = r_F20 + FP_DOUBLE,
- r_DF11 = r_F22 + FP_DOUBLE,
- r_DF12 = r_F24 + FP_DOUBLE,
- r_DF13 = r_F26 + FP_DOUBLE,
- r_DF14 = r_F28 + FP_DOUBLE,
- r_DF15 = r_F30 + FP_DOUBLE,
+ r_DF8 = r_F16 + MIPS_FP_DOUBLE,
+ r_DF9 = r_F18 + MIPS_FP_DOUBLE,
+ r_DF10 = r_F20 + MIPS_FP_DOUBLE,
+ r_DF11 = r_F22 + MIPS_FP_DOUBLE,
+ r_DF12 = r_F24 + MIPS_FP_DOUBLE,
+ r_DF13 = r_F26 + MIPS_FP_DOUBLE,
+ r_DF14 = r_F28 + MIPS_FP_DOUBLE,
+ r_DF15 = r_F30 + MIPS_FP_DOUBLE,
#endif
- r_HI = EXTRA_REG_OFFSET,
+ r_HI = MIPS_EXTRA_REG_OFFSET,
r_LO,
r_PC,
};
@@ -272,21 +268,21 @@ enum NativeRegisterPool {
* Target-independent aliases
*/
-#define rSUSPEND r_S0
-#define rSELF r_S1
-#define rSP r_SP
-#define rARG0 r_ARG0
-#define rARG1 r_ARG1
-#define rARG2 r_ARG2
-#define rARG3 r_ARG3
-#define rFARG0 r_FARG0
-#define rFARG1 r_FARG1
-#define rFARG2 r_FARG2
-#define rFARG3 r_FARG3
-#define rRET0 r_RESULT0
-#define rRET1 r_RESULT1
-#define rINVOKE_TGT r_T9
-#define rCOUNT INVALID_REG
+#define rMIPS_SUSPEND r_S0
+#define rMIPS_SELF r_S1
+#define rMIPS_SP r_SP
+#define rMIPS_ARG0 r_ARG0
+#define rMIPS_ARG1 r_ARG1
+#define rMIPS_ARG2 r_ARG2
+#define rMIPS_ARG3 r_ARG3
+#define rMIPS_FARG0 r_FARG0
+#define rMIPS_FARG1 r_FARG1
+#define rMIPS_FARG2 r_FARG2
+#define rMIPS_FARG3 r_FARG3
+#define rMIPS_RET0 r_RESULT0
+#define rMIPS_RET1 r_RESULT1
+#define rMIPS_INVOKE_TGT r_T9
+#define rMIPS_COUNT INVALID_REG
/* Shift encodings */
enum MipsShiftEncodings {
diff --git a/src/compiler/codegen/mips/MipsRallocUtil.cc b/src/compiler/codegen/mips/MipsRallocUtil.cc
index bd9f97eb6f..4979ae023c 100644
--- a/src/compiler/codegen/mips/MipsRallocUtil.cc
+++ b/src/compiler/codegen/mips/MipsRallocUtil.cc
@@ -68,7 +68,7 @@ void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
if (SRegToVReg(cUnit, info2->sReg) < SRegToVReg(cUnit, info1->sReg))
info1 = info2;
int vReg = SRegToVReg(cUnit, info1->sReg);
- oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), info1->reg,
+ oatFlushRegWideImpl(cUnit, rMIPS_SP, oatVRegOffset(cUnit, vReg), info1->reg,
info1->partner);
}
}
@@ -79,17 +79,17 @@ void oatFlushReg(CompilationUnit* cUnit, int reg)
if (info->live && info->dirty) {
info->dirty = false;
int vReg = SRegToVReg(cUnit, info->sReg);
- oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord);
+ oatFlushRegImpl(cUnit, rMIPS_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
}
}
/* Give access to the target-dependent FP register encoding to common code */
bool oatIsFpReg(int reg) {
- return FPREG(reg);
+ return MIPS_FPREG(reg);
}
uint32_t oatFpRegMask() {
- return FP_REG_MASK;
+ return MIPS_FP_REG_MASK;
}
/* Clobber all regs that might be used by an external C call */
@@ -139,39 +139,39 @@ extern void oatClobberCalleeSave(CompilationUnit *cUnit)
extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit)
{
UNIMPLEMENTED(FATAL) << "No oatGetReturnWideAlt for MIPS";
- RegLocation res = LOC_C_RETURN_WIDE;
+ RegLocation res = locCReturnWide();
return res;
}
extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
{
UNIMPLEMENTED(FATAL) << "No oatGetReturnAlt for MIPS";
- RegLocation res = LOC_C_RETURN;
+ RegLocation res = locCReturn();
return res;
}
extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
{
- return FPREG(reg) ? &cUnit->regPool->FPRegs[reg & FP_REG_MASK]
+ return MIPS_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & MIPS_FP_REG_MASK]
: &cUnit->regPool->coreRegs[reg];
}
/* To be used when explicitly managing register use */
extern void oatLockCallTemps(CompilationUnit* cUnit)
{
- oatLockTemp(cUnit, rARG0);
- oatLockTemp(cUnit, rARG1);
- oatLockTemp(cUnit, rARG2);
- oatLockTemp(cUnit, rARG3);
+ oatLockTemp(cUnit, rMIPS_ARG0);
+ oatLockTemp(cUnit, rMIPS_ARG1);
+ oatLockTemp(cUnit, rMIPS_ARG2);
+ oatLockTemp(cUnit, rMIPS_ARG3);
}
/* To be used when explicitly managing register use */
extern void oatFreeCallTemps(CompilationUnit* cUnit)
{
- oatFreeTemp(cUnit, rARG0);
- oatFreeTemp(cUnit, rARG1);
- oatFreeTemp(cUnit, rARG2);
- oatFreeTemp(cUnit, rARG3);
+ oatFreeTemp(cUnit, rMIPS_ARG0);
+ oatFreeTemp(cUnit, rMIPS_ARG1);
+ oatFreeTemp(cUnit, rMIPS_ARG2);
+ oatFreeTemp(cUnit, rMIPS_ARG3);
}
/* Convert an instruction to a NOP */
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-26 09:17:28 +0000