diff options
Diffstat (limited to 'src/compiler/codegen/mips')
| -rw-r--r-- | src/compiler/codegen/mips/codegen_mips.h | 14 | ||||
| -rw-r--r-- | src/compiler/codegen/mips/int_mips.cc | 21 | ||||
| -rw-r--r-- | src/compiler/codegen/mips/utility_mips.cc | 34 |
3 files changed, 52 insertions, 17 deletions
diff --git a/src/compiler/codegen/mips/codegen_mips.h b/src/compiler/codegen/mips/codegen_mips.h index 705ecfa393..a4d44d5c61 100644 --- a/src/compiler/codegen/mips/codegen_mips.h +++ b/src/compiler/codegen/mips/codegen_mips.h @@ -38,8 +38,7 @@ class MipsCodegen : public Codegen { int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg); virtual LIR* LoadConstantNoClobber(CompilationUnit* cu, int r_dest, int value); - virtual LIR* LoadConstantValueWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi, - int val_lo, int val_hi); + virtual LIR* LoadConstantWide(CompilationUnit* cu, int r_dest_lo, int r_dest_hi, int64_t value); virtual LIR* StoreBaseDisp(CompilationUnit* cu, int rBase, int displacement, int r_src, OpSize size); virtual LIR* StoreBaseDispWide(CompilationUnit* cu, int rBase, int displacement, int r_src_lo, @@ -90,12 +89,18 @@ class MipsCodegen : public Codegen { virtual bool IsUnconditionalBranch(LIR* lir); // Required for target - Dalvik-level generators. + virtual bool GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest, + RegLocation rl_src1, RegLocation rl_src2); virtual void GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation rl_array, RegLocation rl_index, RegLocation rl_src, int scale); virtual void GenArrayGet(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_dest, int scale); virtual void GenArrayPut(CompilationUnit* cu, int opt_flags, OpSize size, RegLocation rl_array, RegLocation rl_index, RegLocation rl_src, int scale); + virtual bool GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, + RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_shift); + virtual void GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, + RegLocation rl_src2); virtual bool GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2); virtual bool GenAndLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, @@ -191,7 +196,10 @@ class MipsCodegen : public Codegen { void SpillCoreRegs(CompilationUnit* cu); void UnSpillCoreRegs(CompilationUnit* cu); static const MipsEncodingMap EncodingMap[kMipsLast]; - bool InexpensiveConstant(int reg, int value); + bool InexpensiveConstantInt(int32_t value); + bool InexpensiveConstantFloat(int32_t value); + bool InexpensiveConstantLong(int64_t value); + bool InexpensiveConstantDouble(int64_t value); }; } // namespace art diff --git a/src/compiler/codegen/mips/int_mips.cc b/src/compiler/codegen/mips/int_mips.cc index 7da4cf684b..675cf8d86a 100644 --- a/src/compiler/codegen/mips/int_mips.cc +++ b/src/compiler/codegen/mips/int_mips.cc @@ -341,6 +341,13 @@ LIR* MipsCodegen::OpIT(CompilationUnit* cu, ConditionCode cond, const char* guid return NULL; } +void MipsCodegen::GenMulLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, + RegLocation rl_src2) +{ + LOG(FATAL) << "Unexpected use of GenMulLong for Mips"; + return; +} + bool MipsCodegen::GenAddLong(CompilationUnit* cu, RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) { @@ -635,4 +642,18 @@ void MipsCodegen::GenArrayObjPut(CompilationUnit* cu, int opt_flags, RegLocation MarkGCCard(cu, r_value, r_array); } +bool MipsCodegen::GenShiftImmOpLong(CompilationUnit* cu, Instruction::Code opcode, RegLocation rl_dest, + RegLocation rl_src1, RegLocation rl_shift) +{ + // Default implementation is just to ignore the constant case. + return GenShiftOpLong(cu, opcode, rl_dest, rl_src1, rl_shift); +} + +bool MipsCodegen::GenArithImmOpLong(CompilationUnit* cu, Instruction::Code opcode, + RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) +{ + // Default - bail to non-const handler. + return GenArithOpLong(cu, opcode, rl_dest, rl_src1, rl_src2); +} + } // namespace art diff --git a/src/compiler/codegen/mips/utility_mips.cc b/src/compiler/codegen/mips/utility_mips.cc index 1e217fbe75..12d054cf3c 100644 --- a/src/compiler/codegen/mips/utility_mips.cc +++ b/src/compiler/codegen/mips/utility_mips.cc @@ -52,17 +52,24 @@ LIR* MipsCodegen::OpFpRegCopy(CompilationUnit *cu, int r_dest, int r_src) return res; } -bool MipsCodegen::InexpensiveConstant(int reg, int value) +bool MipsCodegen::InexpensiveConstantInt(int32_t value) { - bool res = false; - if (value == 0) { - res = true; - } else if (IsUint(16, value)) { - res = true; - } else if ((value < 0) && (value >= -32768)) { - res = true; - } - return res; + return ((value == 0) || IsUint(16, value) || ((value < 0) && (value >= -32768))); +} + +bool MipsCodegen::InexpensiveConstantFloat(int32_t value) +{ + return false; // TUNING +} + +bool MipsCodegen::InexpensiveConstantLong(int64_t value) +{ + return false; // TUNING +} + +bool MipsCodegen::InexpensiveConstantDouble(int64_t value) +{ + return false; // TUNING } /* @@ -336,12 +343,11 @@ LIR* MipsCodegen::OpRegReg(CompilationUnit *cu, OpKind op, int r_dest_src1, int return NewLIR2(cu, opcode, r_dest_src1, r_src2); } -LIR* MipsCodegen::LoadConstantValueWide(CompilationUnit *cu, int r_dest_lo, int r_dest_hi, - int val_lo, int val_hi) +LIR* MipsCodegen::LoadConstantWide(CompilationUnit *cu, int r_dest_lo, int r_dest_hi, int64_t value) { LIR *res; - res = LoadConstantNoClobber(cu, r_dest_lo, val_lo); - LoadConstantNoClobber(cu, r_dest_hi, val_hi); + res = LoadConstantNoClobber(cu, r_dest_lo, Low32Bits(value)); + LoadConstantNoClobber(cu, r_dest_hi, High32Bits(value)); return res; } |