summaryrefslogtreecommitdiff
path: root/src/compiler/codegen/mips
diff options
context:
space:
mode:
Diffstat (limited to 'src/compiler/codegen/mips')
-rw-r--r--src/compiler/codegen/mips/ArchFactory.cc8
-rw-r--r--src/compiler/codegen/mips/ArchUtility.cc2
-rw-r--r--src/compiler/codegen/mips/Codegen.h13
-rw-r--r--src/compiler/codegen/mips/FP/MipsFP.cc48
-rw-r--r--src/compiler/codegen/mips/Mips32/Factory.cc10
-rw-r--r--src/compiler/codegen/mips/Mips32/Gen.cc32
6 files changed, 50 insertions, 63 deletions
diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index 83172157bd..4fd127f2eb 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -26,7 +26,7 @@
namespace art {
-bool genAddLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genAddLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
@@ -50,7 +50,7 @@ bool genAddLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
return false;
}
-bool genSubLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genSubLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
@@ -74,7 +74,7 @@ bool genSubLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
return false;
}
-bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc)
{
rlSrc = loadValueWide(cUnit, rlSrc, kCoreReg);
@@ -177,7 +177,7 @@ void genEntrySequence(CompilationUnit* cUnit, BasicBlock* bb)
DCHECK_EQ(cUnit->numFPSpills, 0);
if (!skipOverflowCheck) {
opRegRegImm(cUnit, kOpSub, newSP, rSP, cUnit->frameSize - (spillCount * 4));
- genRegRegCheck(cUnit, kCondCc, newSP, checkReg, NULL, kThrowStackOverflow);
+ genRegRegCheck(cUnit, kCondCc, newSP, checkReg, kThrowStackOverflow);
opRegCopy(cUnit, rSP, newSP); // Establish stack
} else {
opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4));
diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index f1afa78844..ead9ff5cd8 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -127,7 +127,7 @@ std::string buildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
return buf;
}
-// FIXME: need to redo resourse maps for MIPS - fix this at that time
+// FIXME: need to redo resource maps for MIPS - fix this at that time
void oatDumpResourceMask(LIR *lir, u8 mask, const char *prefix)
{
char buf[256];
diff --git a/src/compiler/codegen/mips/Codegen.h b/src/compiler/codegen/mips/Codegen.h
index 6ddc5ac210..6add82ab0d 100644
--- a/src/compiler/codegen/mips/Codegen.h
+++ b/src/compiler/codegen/mips/Codegen.h
@@ -27,11 +27,11 @@
namespace art {
#if defined(_CODEGEN_C)
-bool genAddLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genAddLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2);
-bool genSubLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genSubLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2);
-bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc);
LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
@@ -41,15 +41,16 @@ LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
int checkValue, LIR* target);
/* Forward declaraton the portable versions due to circular dependency */
-bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+bool genArithOpFloatPortable(CompilationUnit* cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+bool genArithOpDoublePortable(CompilationUnit* cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-bool genConversionPortable(CompilationUnit* cUnit, MIR* mir);
+bool genConversionPortable(CompilationUnit* cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc);
int loadHelper(CompilationUnit* cUnit, int offset);
LIR* loadConstant(CompilationUnit* cUnit, int reg, int immVal);
diff --git a/src/compiler/codegen/mips/FP/MipsFP.cc b/src/compiler/codegen/mips/FP/MipsFP.cc
index c101039be7..a57d34a6d0 100644
--- a/src/compiler/codegen/mips/FP/MipsFP.cc
+++ b/src/compiler/codegen/mips/FP/MipsFP.cc
@@ -18,7 +18,7 @@
namespace art {
-bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
+bool genArithOpFloat(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
#ifdef __mips_hard_float
@@ -29,7 +29,7 @@ bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
* Don't attempt to optimize register usage since these opcodes call out to
* the handlers.
*/
- switch (mir->dalvikInsn.opcode) {
+ switch (opcode) {
case Instruction::ADD_FLOAT_2ADDR:
case Instruction::ADD_FLOAT:
op = kMipsFadds;
@@ -49,7 +49,7 @@ bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
case Instruction::REM_FLOAT_2ADDR:
case Instruction::REM_FLOAT:
case Instruction::NEG_FLOAT: {
- return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
+ return genArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
}
default:
return true;
@@ -63,11 +63,11 @@ bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
return false;
#else
- return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
+ return genArithOpFloatPortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
#endif
}
-static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
+static bool genArithOpDouble(CompilationUnit *cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2)
{
@@ -75,7 +75,7 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
int op = kMipsNop;
RegLocation rlResult;
- switch (mir->dalvikInsn.opcode) {
+ switch (opcode) {
case Instruction::ADD_DOUBLE_2ADDR:
case Instruction::ADD_DOUBLE:
op = kMipsFaddd;
@@ -95,7 +95,7 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
case Instruction::REM_DOUBLE_2ADDR:
case Instruction::REM_DOUBLE:
case Instruction::NEG_DOUBLE: {
- return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
+ return genArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
}
default:
return true;
@@ -113,40 +113,28 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
storeValueWide(cUnit, rlDest, rlResult);
return false;
#else
- return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
+ return genArithOpDoublePortable(cUnit, opcode, rlDest, rlSrc1, rlSrc2);
#endif
}
-static bool genConversion(CompilationUnit *cUnit, MIR *mir)
+static bool genConversion(CompilationUnit *cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc)
{
#ifdef __mips_hard_float
- Instruction::Code opcode = mir->dalvikInsn.opcode;
- bool longSrc = false;
- bool longDest = false;
- RegLocation rlSrc;
- RegLocation rlDest;
int op = kMipsNop;
int srcReg;
RegLocation rlResult;
switch (opcode) {
case Instruction::INT_TO_FLOAT:
- longSrc = false;
- longDest = false;
op = kMipsFcvtsw;
break;
case Instruction::DOUBLE_TO_FLOAT:
- longSrc = true;
- longDest = false;
op = kMipsFcvtsd;
break;
case Instruction::FLOAT_TO_DOUBLE:
- longSrc = false;
- longDest = true;
op = kMipsFcvtds;
break;
case Instruction::INT_TO_DOUBLE:
- longSrc = false;
- longDest = true;
op = kMipsFcvtdw;
break;
case Instruction::FLOAT_TO_INT:
@@ -155,44 +143,40 @@ static bool genConversion(CompilationUnit *cUnit, MIR *mir)
case Instruction::FLOAT_TO_LONG:
case Instruction::LONG_TO_FLOAT:
case Instruction::DOUBLE_TO_LONG:
- return genConversionPortable(cUnit, mir);
+ return genConversionPortable(cUnit, opcode, rlDest, rlSrc);
default:
return true;
}
- if (longSrc) {
- rlSrc = oatGetSrcWide(cUnit, mir, 0, 1);
+ if (rlSrc.wide) {
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
} else {
- rlSrc = oatGetSrc(cUnit, mir, 0);
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
- if (longDest) {
- rlDest = oatGetDestWide(cUnit, mir, 0, 1);
+ if (rlDest.wide) {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, (MipsOpCode)op, S2D(rlResult.lowReg, rlResult.highReg),
srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
- rlDest = oatGetDest(cUnit, mir, 0);
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
newLIR2(cUnit, (MipsOpCode)op, rlResult.lowReg, srcReg);
storeValue(cUnit, rlDest, rlResult);
}
return false;
#else
- return genConversionPortable(cUnit, mir);
+ return genConversionPortable(cUnit, opcode, rlDest, rlSrc);
#endif
}
-static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest,
+static bool genCmpFP(CompilationUnit *cUnit, Instruction::Code opcode, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
bool wide = true;
int offset;
- switch (mir->dalvikInsn.opcode) {
+ switch (opcode) {
case Instruction::CMPL_FLOAT:
offset = ENTRYPOINT_OFFSET(pCmplFloat);
wide = false;
diff --git a/src/compiler/codegen/mips/Mips32/Factory.cc b/src/compiler/codegen/mips/Mips32/Factory.cc
index 8f3c1ec37a..ad220f8aba 100644
--- a/src/compiler/codegen/mips/Mips32/Factory.cc
+++ b/src/compiler/codegen/mips/Mips32/Factory.cc
@@ -521,7 +521,7 @@ LIR *storeMultiple(CompilationUnit *cUnit, int rBase, int rMask)
return res; /* NULL always returned which should be ok since no callers use it */
}
-LIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
+LIR *loadBaseDispBody(CompilationUnit *cUnit, int rBase,
int displacement, int rDest, int rDestHi,
OpSize size, int sReg)
/*
@@ -626,17 +626,17 @@ LIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase,
return load;
}
-LIR *loadBaseDisp(CompilationUnit *cUnit, MIR *mir, int rBase,
+LIR *loadBaseDisp(CompilationUnit *cUnit, int rBase,
int displacement, int rDest, OpSize size, int sReg)
{
- return loadBaseDispBody(cUnit, mir, rBase, displacement, rDest, -1,
+ return loadBaseDispBody(cUnit, rBase, displacement, rDest, -1,
size, sReg);
}
-LIR *loadBaseDispWide(CompilationUnit *cUnit, MIR *mir, int rBase,
+LIR *loadBaseDispWide(CompilationUnit *cUnit, int rBase,
int displacement, int rDestLo, int rDestHi, int sReg)
{
- return loadBaseDispBody(cUnit, mir, rBase, displacement, rDestLo, rDestHi,
+ return loadBaseDispBody(cUnit, rBase, displacement, rDestLo, rDestHi,
kLong, sReg);
}
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index 46c90f89ac..090c08650d 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -63,10 +63,10 @@ void genSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
* done:
*
*/
-void genSparseSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
- LIR* labelList)
+void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
+ RegLocation rlSrc, LIR* labelList)
{
- const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
+ const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
dumpSparseSwitchTable(table);
}
@@ -74,7 +74,7 @@ void genSparseSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
true, kAllocData);
tabRec->table = table;
- tabRec->vaddr = mir->offset;
+ tabRec->vaddr = cUnit->currentDalvikOffset;
int elements = table[1];
tabRec->targets = (LIR* *)oatNew(cUnit, elements * sizeof(LIR*), true,
kAllocLIR);
@@ -142,9 +142,10 @@ void genSparseSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc,
* jr r_RA
* done:
*/
-void genPackedSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genPackedSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
+ RegLocation rlSrc)
{
- const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
+ const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
if (cUnit->printMe) {
dumpPackedSwitchTable(table);
}
@@ -152,7 +153,7 @@ void genPackedSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
SwitchTable *tabRec = (SwitchTable *)oatNew(cUnit, sizeof(SwitchTable),
true, kAllocData);
tabRec->table = table;
- tabRec->vaddr = mir->offset;
+ tabRec->vaddr = cUnit->currentDalvikOffset;
int size = table[1];
tabRec->targets = (LIR* *)oatNew(cUnit, size * sizeof(LIR*), true,
kAllocLIR);
@@ -225,14 +226,15 @@ void genPackedSwitch(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void genFillArrayData(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset,
+ RegLocation rlSrc)
{
- const u2* table = cUnit->insns + mir->offset + mir->dalvikInsn.vB;
+ const u2* table = cUnit->insns + cUnit->currentDalvikOffset + tableOffset;
// Add the table to the list - we'll process it later
FillArrayData *tabRec = (FillArrayData *)
oatNew(cUnit, sizeof(FillArrayData), true, kAllocData);
tabRec->table = table;
- tabRec->vaddr = mir->offset;
+ tabRec->vaddr = cUnit->currentDalvikOffset;
u2 width = tabRec->table[1];
u4 size = tabRec->table[2] | (((u4)tabRec->table[3]) << 16);
tabRec->size = (size * width) + 8;
@@ -284,12 +286,12 @@ void genNegDouble(CompilationUnit *cUnit, RegLocation rlDest, RegLocation rlSrc)
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void genMonitorEnter(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
oatFlushAllRegs(cUnit);
loadValueDirectFixed(cUnit, rlSrc, rARG0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, rARG0, mir);
+ genNullCheck(cUnit, rlSrc.sRegLow, rARG0, optFlags);
// Go expensive route - artLockObjectFromCode(self, obj);
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pLockObjectFromCode));
oatClobberCalleeSave(cUnit);
@@ -299,12 +301,12 @@ void genMonitorEnter(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
/*
* TODO: implement fast path to short-circuit thin-lock case
*/
-void genMonitorExit(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
+void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
{
oatFlushAllRegs(cUnit);
loadValueDirectFixed(cUnit, rlSrc, rARG0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
- genNullCheck(cUnit, rlSrc.sRegLow, rARG0, mir);
+ genNullCheck(cUnit, rlSrc.sRegLow, rARG0, optFlags);
// Go expensive route - UnlockObjectFromCode(obj);
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pUnlockObjectFromCode));
oatClobberCalleeSave(cUnit);
@@ -327,7 +329,7 @@ void genMonitorExit(CompilationUnit* cUnit, MIR* mir, RegLocation rlSrc)
* finish:
*
*/
-void genCmpLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+void genCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc1, RegLocation rlSrc2)
{
rlSrc1 = loadValueWide(cUnit, rlSrc1, kCoreReg);
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-12 07:32:21 +0000