summaryrefslogtreecommitdiff
path: root/src/compiler/codegen/arm
diff options
context:
space:
mode:
Diffstat (limited to 'src/compiler/codegen/arm')
-rw-r--r--src/compiler/codegen/arm/ArchFactory.cc30
-rw-r--r--src/compiler/codegen/arm/ArchUtility.cc94
-rw-r--r--src/compiler/codegen/arm/ArmLIR.h178
-rw-r--r--src/compiler/codegen/arm/ArmRallocUtil.cc22
-rw-r--r--src/compiler/codegen/arm/Assemble.cc12
-rw-r--r--src/compiler/codegen/arm/FP/Thumb2VFP.cc20
-rw-r--r--src/compiler/codegen/arm/Thumb2/Factory.cc106
-rw-r--r--src/compiler/codegen/arm/Thumb2/Gen.cc84
-rw-r--r--src/compiler/codegen/arm/Thumb2/Ralloc.cc2
9 files changed, 312 insertions, 236 deletions
diff --git a/src/compiler/codegen/arm/ArchFactory.cc b/src/compiler/codegen/arm/ArchFactory.cc
index f85bd2fff5..f75d8e3580 100644
--- a/src/compiler/codegen/arm/ArchFactory.cc
+++ b/src/compiler/codegen/arm/ArchFactory.cc
@@ -44,8 +44,8 @@ bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
int loadHelper(CompilationUnit* cUnit, int offset)
{
- loadWordDisp(cUnit, rSELF, offset, rLR);
- return rLR;
+ loadWordDisp(cUnit, rARM_SELF, offset, rARM_LR);
+ return rARM_LR;
}
void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
@@ -73,7 +73,7 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
newLIR0(cUnit, kPseudoMethodEntry);
if (!skipOverflowCheck) {
/* Load stack limit */
- loadWordDisp(cUnit, rSELF, Thread::StackEndOffset().Int32Value(), r12);
+ loadWordDisp(cUnit, rARM_SELF, Thread::StackEndOffset().Int32Value(), r12);
}
/* Spill core callee saves */
newLIR1(cUnit, kThumb2Push, cUnit->coreSpillMask);
@@ -87,11 +87,11 @@ void genEntrySequence(CompilationUnit* cUnit, RegLocation* argLocs,
newLIR1(cUnit, kThumb2VPushCS, cUnit->numFPSpills);
}
if (!skipOverflowCheck) {
- opRegRegImm(cUnit, kOpSub, rLR, rSP, cUnit->frameSize - (spillCount * 4));
- genRegRegCheck(cUnit, kCondCc, rLR, r12, kThrowStackOverflow);
- opRegCopy(cUnit, rSP, rLR); // Establish stack
+ opRegRegImm(cUnit, kOpSub, rARM_LR, rARM_SP, cUnit->frameSize - (spillCount * 4));
+ genRegRegCheck(cUnit, kCondCc, rARM_LR, r12, kThrowStackOverflow);
+ opRegCopy(cUnit, rARM_SP, rARM_LR); // Establish stack
} else {
- opRegImm(cUnit, kOpSub, rSP, cUnit->frameSize - (spillCount * 4));
+ opRegImm(cUnit, kOpSub, rARM_SP, cUnit->frameSize - (spillCount * 4));
}
flushIns(cUnit, argLocs, rlMethod);
@@ -113,20 +113,20 @@ void genExitSequence(CompilationUnit* cUnit)
oatLockTemp(cUnit, r1);
newLIR0(cUnit, kPseudoMethodExit);
- opRegImm(cUnit, kOpAdd, rSP, cUnit->frameSize - (spillCount * 4));
+ opRegImm(cUnit, kOpAdd, rARM_SP, cUnit->frameSize - (spillCount * 4));
/* Need to restore any FP callee saves? */
if (cUnit->numFPSpills) {
newLIR1(cUnit, kThumb2VPopCS, cUnit->numFPSpills);
}
- if (cUnit->coreSpillMask & (1 << rLR)) {
- /* Unspill rLR to rPC */
- cUnit->coreSpillMask &= ~(1 << rLR);
- cUnit->coreSpillMask |= (1 << rPC);
+ if (cUnit->coreSpillMask & (1 << rARM_LR)) {
+ /* Unspill rARM_LR to rARM_PC */
+ cUnit->coreSpillMask &= ~(1 << rARM_LR);
+ cUnit->coreSpillMask |= (1 << rARM_PC);
}
newLIR1(cUnit, kThumb2Pop, cUnit->coreSpillMask);
- if (!(cUnit->coreSpillMask & (1 << rPC))) {
- /* We didn't pop to rPC, so must do a bv rLR */
- newLIR1(cUnit, kThumbBx, rLR);
+ if (!(cUnit->coreSpillMask & (1 << rARM_PC))) {
+ /* We didn't pop to rARM_PC, so must do a bv rARM_LR */
+ newLIR1(cUnit, kThumbBx, rARM_LR);
}
}
diff --git a/src/compiler/codegen/arm/ArchUtility.cc b/src/compiler/codegen/arm/ArchUtility.cc
index 8746b6866e..2d4b314d51 100644
--- a/src/compiler/codegen/arm/ArchUtility.cc
+++ b/src/compiler/codegen/arm/ArchUtility.cc
@@ -22,6 +22,92 @@
namespace art {
+RegLocation locCReturn()
+{
+ RegLocation res = ARM_LOC_C_RETURN;
+ return res;
+}
+
+RegLocation locCReturnWide()
+{
+ RegLocation res = ARM_LOC_C_RETURN_WIDE;
+ return res;
+}
+
+RegLocation locCReturnFloat()
+{
+ RegLocation res = ARM_LOC_C_RETURN_FLOAT;
+ return res;
+}
+
+RegLocation locCReturnDouble()
+{
+ RegLocation res = ARM_LOC_C_RETURN_DOUBLE;
+ return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+ int res = INVALID_REG;
+ switch (reg) {
+ case kSelf: res = rARM_SELF; break;
+ case kSuspend: res = rARM_SUSPEND; break;
+ case kLr: res = rARM_LR; break;
+ case kPc: res = rARM_PC; break;
+ case kSp: res = rARM_SP; break;
+ case kArg0: res = rARM_ARG0; break;
+ case kArg1: res = rARM_ARG1; break;
+ case kArg2: res = rARM_ARG2; break;
+ case kArg3: res = rARM_ARG3; break;
+ case kFArg0: res = rARM_FARG0; break;
+ case kFArg1: res = rARM_FARG1; break;
+ case kFArg2: res = rARM_FARG2; break;
+ case kFArg3: res = rARM_FARG3; break;
+ case kRet0: res = rARM_RET0; break;
+ case kRet1: res = rARM_RET1; break;
+ case kInvokeTgt: res = rARM_INVOKE_TGT; break;
+ case kCount: res = rARM_COUNT; break;
+ }
+ return res;
+}
+
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+ return ARM_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+ return ARM_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+ return ARM_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+ return ARM_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+ return ARM_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+ return (ARM_REGTYPE(reg1) == ARM_REGTYPE(reg2));
+}
+
/*
* Decode the register id.
*/
@@ -34,9 +120,9 @@ u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
regId = reg & 0x1f;
/* Each double register is equal to a pair of single-precision FP registers */
- seed = DOUBLEREG(reg) ? 3 : 1;
+ seed = ARM_DOUBLEREG(reg) ? 3 : 1;
/* FP register starts at bit position 16 */
- shift = FPREG(reg) ? kArmFPReg0 : 0;
+ shift = ARM_FPREG(reg) ? kArmFPReg0 : 0;
/* Expand the double register id into single offset */
shift += regId;
return (seed << shift);
@@ -306,10 +392,10 @@ std::string buildInsnString(const char* fmt, LIR* lir, unsigned char* baseAddr)
sprintf(tbuf,"%d [%#x]", operand, operand);
break;
case 's':
- sprintf(tbuf,"s%d",operand & FP_REG_MASK);
+ sprintf(tbuf,"s%d",operand & ARM_FP_REG_MASK);
break;
case 'S':
- sprintf(tbuf,"d%d",(operand & FP_REG_MASK) >> 1);
+ sprintf(tbuf,"d%d",(operand & ARM_FP_REG_MASK) >> 1);
break;
case 'h':
sprintf(tbuf,"%04x", operand);
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index 05082ed8d8..7eebc835ec 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -30,12 +30,12 @@ namespace art {
* pointer in r0 as a hidden arg0. Otherwise used as codegen scratch
* registers.
* r0-r1: As in C/C++ r0 is 32-bit return register and r0/r1 is 64-bit
- * r4 : (rSUSPEND) is reserved (suspend check/debugger assist)
+ * r4 : (rARM_SUSPEND) is reserved (suspend check/debugger assist)
* r5 : Callee save (promotion target)
* r6 : Callee save (promotion target)
* r7 : Callee save (promotion target)
* r8 : Callee save (promotion target)
- * r9 : (rSELF) is reserved (pointer to thread-local storage)
+ * r9 : (rARM_SELF) is reserved (pointer to thread-local storage)
* r10 : Callee save (promotion target)
* r11 : Callee save (promotion target)
* r12 : Scratch, may be trashed by linkage stubs
@@ -95,17 +95,17 @@ namespace art {
*/
/* Offset to distingish FP regs */
-#define FP_REG_OFFSET 32
+#define ARM_FP_REG_OFFSET 32
/* Offset to distinguish DP FP regs */
-#define FP_DOUBLE 64
+#define ARM_FP_DOUBLE 64
/* First FP callee save */
-#define FP_CALLEE_SAVE_BASE 16
+#define ARM_FP_CALLEE_SAVE_BASE 16
/* Reg types */
-#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
-#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)
-#define LOWREG(x) ((x & 0x7) == x)
-#define DOUBLEREG(x) ((x & FP_DOUBLE) == FP_DOUBLE)
-#define SINGLEREG(x) (FPREG(x) && !DOUBLEREG(x))
+#define ARM_REGTYPE(x) (x & (ARM_FP_REG_OFFSET | ARM_FP_DOUBLE))
+#define ARM_FPREG(x) ((x & ARM_FP_REG_OFFSET) == ARM_FP_REG_OFFSET)
+#define ARM_LOWREG(x) ((x & 0x7) == x)
+#define ARM_DOUBLEREG(x) ((x & ARM_FP_DOUBLE) == ARM_FP_DOUBLE)
+#define ARM_SINGLEREG(x) (ARM_FPREG(x) && !ARM_DOUBLEREG(x))
/*
* Note: the low register of a floating point pair is sufficient to
* create the name of a double, but require both names to be passed to
@@ -113,21 +113,17 @@ namespace art {
* rework is done in this area. Also, it is a good reminder in the calling
* code that reg locations always describe doubles as a pair of singles.
*/
-#define S2D(x,y) ((x) | FP_DOUBLE)
+#define ARM_S2D(x,y) ((x) | ARM_FP_DOUBLE)
/* Mask to strip off fp flags */
-#define FP_REG_MASK (FP_REG_OFFSET-1)
-/* non-existent Dalvik register */
-#define vNone (-1)
-/* non-existant physical register */
-#define rNone (-1)
+#define ARM_FP_REG_MASK (ARM_FP_REG_OFFSET-1)
/* RegisterLocation templates return values (r0, or r0/r1) */
-#define LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
- INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, \
- INVALID_SREG, INVALID_SREG}
-#define LOC_C_RETURN_FLOAT LOC_C_RETURN
-#define LOC_C_RETURN_WIDE_DOUBLE LOC_C_RETURN_WIDE
+#define ARM_LOC_C_RETURN {kLocPhysReg, 0, 0, 0, 0, 0, 0, 0, 1, r0, INVALID_REG,\
+ INVALID_SREG, INVALID_SREG}
+#define ARM_LOC_C_RETURN_WIDE {kLocPhysReg, 1, 0, 0, 0, 0, 0, 0, 1, r0, r1, \
+ INVALID_SREG, INVALID_SREG}
+#define ARM_LOC_C_RETURN_FLOAT ARM_LOC_C_RETURN
+#define ARM_LOC_C_RETURN_DOUBLE ARM_LOC_C_RETURN_WIDE
enum ArmResourceEncodingPos {
kArmGPReg0 = 0,
@@ -145,95 +141,89 @@ enum ArmResourceEncodingPos {
#define ENCODE_ARM_REG_PC (1ULL << kArmRegPC)
#define ENCODE_ARM_REG_FPCS_LIST(N) ((u8)N << kArmFPReg16)
-/*
- * Annotate special-purpose core registers:
- * - ARM architecture: r13sp, r14lr, and r15pc
- *
- * rPC, rFP, and rSELF are for architecture-independent code to use.
- */
-enum NativeRegisterPool {
+enum ArmNativeRegisterPool {
r0 = 0,
r1 = 1,
r2 = 2,
r3 = 3,
- rSUSPEND = 4,
+ rARM_SUSPEND = 4,
r5 = 5,
r6 = 6,
r7 = 7,
r8 = 8,
- rSELF = 9,
+ rARM_SELF = 9,
r10 = 10,
r11 = 11,
r12 = 12,
r13sp = 13,
- rSP = 13,
+ rARM_SP = 13,
r14lr = 14,
- rLR = 14,
+ rARM_LR = 14,
r15pc = 15,
- rPC = 15,
- fr0 = 0 + FP_REG_OFFSET,
- fr1 = 1 + FP_REG_OFFSET,
- fr2 = 2 + FP_REG_OFFSET,
- fr3 = 3 + FP_REG_OFFSET,
- fr4 = 4 + FP_REG_OFFSET,
- fr5 = 5 + FP_REG_OFFSET,
- fr6 = 6 + FP_REG_OFFSET,
- fr7 = 7 + FP_REG_OFFSET,
- fr8 = 8 + FP_REG_OFFSET,
- fr9 = 9 + FP_REG_OFFSET,
- fr10 = 10 + FP_REG_OFFSET,
- fr11 = 11 + FP_REG_OFFSET,
- fr12 = 12 + FP_REG_OFFSET,
- fr13 = 13 + FP_REG_OFFSET,
- fr14 = 14 + FP_REG_OFFSET,
- fr15 = 15 + FP_REG_OFFSET,
- fr16 = 16 + FP_REG_OFFSET,
- fr17 = 17 + FP_REG_OFFSET,
- fr18 = 18 + FP_REG_OFFSET,
- fr19 = 19 + FP_REG_OFFSET,
- fr20 = 20 + FP_REG_OFFSET,
- fr21 = 21 + FP_REG_OFFSET,
- fr22 = 22 + FP_REG_OFFSET,
- fr23 = 23 + FP_REG_OFFSET,
- fr24 = 24 + FP_REG_OFFSET,
- fr25 = 25 + FP_REG_OFFSET,
- fr26 = 26 + FP_REG_OFFSET,
- fr27 = 27 + FP_REG_OFFSET,
- fr28 = 28 + FP_REG_OFFSET,
- fr29 = 29 + FP_REG_OFFSET,
- fr30 = 30 + FP_REG_OFFSET,
- fr31 = 31 + FP_REG_OFFSET,
- dr0 = fr0 + FP_DOUBLE,
- dr1 = fr2 + FP_DOUBLE,
- dr2 = fr4 + FP_DOUBLE,
- dr3 = fr6 + FP_DOUBLE,
- dr4 = fr8 + FP_DOUBLE,
- dr5 = fr10 + FP_DOUBLE,
- dr6 = fr12 + FP_DOUBLE,
- dr7 = fr14 + FP_DOUBLE,
- dr8 = fr16 + FP_DOUBLE,
- dr9 = fr18 + FP_DOUBLE,
- dr10 = fr20 + FP_DOUBLE,
- dr11 = fr22 + FP_DOUBLE,
- dr12 = fr24 + FP_DOUBLE,
- dr13 = fr26 + FP_DOUBLE,
- dr14 = fr28 + FP_DOUBLE,
- dr15 = fr30 + FP_DOUBLE,
+ rARM_PC = 15,
+ fr0 = 0 + ARM_FP_REG_OFFSET,
+ fr1 = 1 + ARM_FP_REG_OFFSET,
+ fr2 = 2 + ARM_FP_REG_OFFSET,
+ fr3 = 3 + ARM_FP_REG_OFFSET,
+ fr4 = 4 + ARM_FP_REG_OFFSET,
+ fr5 = 5 + ARM_FP_REG_OFFSET,
+ fr6 = 6 + ARM_FP_REG_OFFSET,
+ fr7 = 7 + ARM_FP_REG_OFFSET,
+ fr8 = 8 + ARM_FP_REG_OFFSET,
+ fr9 = 9 + ARM_FP_REG_OFFSET,
+ fr10 = 10 + ARM_FP_REG_OFFSET,
+ fr11 = 11 + ARM_FP_REG_OFFSET,
+ fr12 = 12 + ARM_FP_REG_OFFSET,
+ fr13 = 13 + ARM_FP_REG_OFFSET,
+ fr14 = 14 + ARM_FP_REG_OFFSET,
+ fr15 = 15 + ARM_FP_REG_OFFSET,
+ fr16 = 16 + ARM_FP_REG_OFFSET,
+ fr17 = 17 + ARM_FP_REG_OFFSET,
+ fr18 = 18 + ARM_FP_REG_OFFSET,
+ fr19 = 19 + ARM_FP_REG_OFFSET,
+ fr20 = 20 + ARM_FP_REG_OFFSET,
+ fr21 = 21 + ARM_FP_REG_OFFSET,
+ fr22 = 22 + ARM_FP_REG_OFFSET,
+ fr23 = 23 + ARM_FP_REG_OFFSET,
+ fr24 = 24 + ARM_FP_REG_OFFSET,
+ fr25 = 25 + ARM_FP_REG_OFFSET,
+ fr26 = 26 + ARM_FP_REG_OFFSET,
+ fr27 = 27 + ARM_FP_REG_OFFSET,
+ fr28 = 28 + ARM_FP_REG_OFFSET,
+ fr29 = 29 + ARM_FP_REG_OFFSET,
+ fr30 = 30 + ARM_FP_REG_OFFSET,
+ fr31 = 31 + ARM_FP_REG_OFFSET,
+ dr0 = fr0 + ARM_FP_DOUBLE,
+ dr1 = fr2 + ARM_FP_DOUBLE,
+ dr2 = fr4 + ARM_FP_DOUBLE,
+ dr3 = fr6 + ARM_FP_DOUBLE,
+ dr4 = fr8 + ARM_FP_DOUBLE,
+ dr5 = fr10 + ARM_FP_DOUBLE,
+ dr6 = fr12 + ARM_FP_DOUBLE,
+ dr7 = fr14 + ARM_FP_DOUBLE,
+ dr8 = fr16 + ARM_FP_DOUBLE,
+ dr9 = fr18 + ARM_FP_DOUBLE,
+ dr10 = fr20 + ARM_FP_DOUBLE,
+ dr11 = fr22 + ARM_FP_DOUBLE,
+ dr12 = fr24 + ARM_FP_DOUBLE,
+ dr13 = fr26 + ARM_FP_DOUBLE,
+ dr14 = fr28 + ARM_FP_DOUBLE,
+ dr15 = fr30 + ARM_FP_DOUBLE,
};
/* Target-independent aliases */
-#define rARG0 r0
-#define rARG1 r1
-#define rARG2 r2
-#define rARG3 r3
-#define rFARG0 r0
-#define rFARG1 r1
-#define rFARG2 r2
-#define rFARG3 r3
-#define rRET0 r0
-#define rRET1 r1
-#define rINVOKE_TGT rLR
-#define rCOUNT INVALID_REG
+#define rARM_ARG0 r0
+#define rARM_ARG1 r1
+#define rARM_ARG2 r2
+#define rARM_ARG3 r3
+#define rARM_FARG0 r0
+#define rARM_FARG1 r1
+#define rARM_FARG2 r2
+#define rARM_FARG3 r3
+#define rARM_RET0 r0
+#define rARM_RET1 r1
+#define rARM_INVOKE_TGT rARM_LR
+#define rARM_COUNT INVALID_REG
/* Shift encodings */
enum ArmShiftEncodings {
diff --git a/src/compiler/codegen/arm/ArmRallocUtil.cc b/src/compiler/codegen/arm/ArmRallocUtil.cc
index bf7c1c759a..05fe7faa5e 100644
--- a/src/compiler/codegen/arm/ArmRallocUtil.cc
+++ b/src/compiler/codegen/arm/ArmRallocUtil.cc
@@ -35,7 +35,7 @@ namespace art {
void oatAdjustSpillMask(CompilationUnit* cUnit)
{
- cUnit->coreSpillMask |= (1 << rLR);
+ cUnit->coreSpillMask |= (1 << rARM_LR);
cUnit->numCoreSpills++;
}
@@ -47,8 +47,8 @@ void oatAdjustSpillMask(CompilationUnit* cUnit)
*/
void oatMarkPreservedSingle(CompilationUnit* cUnit, int vReg, int reg)
{
- DCHECK_GE(reg, FP_REG_MASK + FP_CALLEE_SAVE_BASE);
- reg = (reg & FP_REG_MASK) - FP_CALLEE_SAVE_BASE;
+ DCHECK_GE(reg, ARM_FP_REG_MASK + ARM_FP_CALLEE_SAVE_BASE);
+ reg = (reg & ARM_FP_REG_MASK) - ARM_FP_CALLEE_SAVE_BASE;
// Ensure fpVmapTable is large enough
int tableSize = cUnit->fpVmapTable.size();
for (int i = tableSize; i < (reg + 1); i++) {
@@ -58,7 +58,7 @@ void oatMarkPreservedSingle(CompilationUnit* cUnit, int vReg, int reg)
cUnit->fpVmapTable[reg] = vReg;
// Size of fpVmapTable is high-water mark, use to set mask
cUnit->numFPSpills = cUnit->fpVmapTable.size();
- cUnit->fpSpillMask = ((1 << cUnit->numFPSpills) - 1) << FP_CALLEE_SAVE_BASE;
+ cUnit->fpSpillMask = ((1 << cUnit->numFPSpills) - 1) << ARM_FP_CALLEE_SAVE_BASE;
}
void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
@@ -80,7 +80,7 @@ void oatFlushRegWide(CompilationUnit* cUnit, int reg1, int reg2)
SRegToVReg(cUnit, info1->sReg))
info1 = info2;
int vReg = SRegToVReg(cUnit, info1->sReg);
- oatFlushRegWideImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg),
+ oatFlushRegWideImpl(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg),
info1->reg, info1->partner);
}
}
@@ -91,17 +91,17 @@ void oatFlushReg(CompilationUnit* cUnit, int reg)
if (info->live && info->dirty) {
info->dirty = false;
int vReg = SRegToVReg(cUnit, info->sReg);
- oatFlushRegImpl(cUnit, rSP, oatVRegOffset(cUnit, vReg), reg, kWord);
+ oatFlushRegImpl(cUnit, rARM_SP, oatVRegOffset(cUnit, vReg), reg, kWord);
}
}
/* Give access to the target-dependent FP register encoding to common code */
bool oatIsFpReg(int reg) {
- return FPREG(reg);
+ return ARM_FPREG(reg);
}
uint32_t oatFpRegMask() {
- return FP_REG_MASK;
+ return ARM_FP_REG_MASK;
}
/* Clobber all regs that might be used by an external C call */
@@ -133,7 +133,7 @@ void oatClobberCalleeSave(CompilationUnit *cUnit)
extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit)
{
- RegLocation res = LOC_C_RETURN_WIDE;
+ RegLocation res = locCReturnWide();
res.lowReg = r2;
res.highReg = r3;
oatClobber(cUnit, r2);
@@ -146,7 +146,7 @@ extern RegLocation oatGetReturnWideAlt(CompilationUnit* cUnit)
extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
{
- RegLocation res = LOC_C_RETURN;
+ RegLocation res = locCReturn();
res.lowReg = r1;
oatClobber(cUnit, r1);
oatMarkInUse(cUnit, r1);
@@ -155,7 +155,7 @@ extern RegLocation oatGetReturnAlt(CompilationUnit* cUnit)
extern RegisterInfo* oatGetRegInfo(CompilationUnit* cUnit, int reg)
{
- return FPREG(reg) ? &cUnit->regPool->FPRegs[reg & FP_REG_MASK]
+ return ARM_FPREG(reg) ? &cUnit->regPool->FPRegs[reg & ARM_FP_REG_MASK]
: &cUnit->regPool->coreRegs[reg];
}
diff --git a/src/compiler/codegen/arm/Assemble.cc b/src/compiler/codegen/arm/Assemble.cc
index 759ffd3bd2..765a8ffc66 100644
--- a/src/compiler/codegen/arm/Assemble.cc
+++ b/src/compiler/codegen/arm/Assemble.cc
@@ -1051,12 +1051,12 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit* cUnit,
((lir->opcode == kThumb2Vldrs) && (delta > 1020)) ||
((lir->opcode == kThumb2Vldrd) && (delta > 1020))) {
/*
- * Note: because rLR may be used to fix up out-of-range
+ * Note: because rARM_LR may be used to fix up out-of-range
* vldrs/vldrd we include REG_DEF_LR in the resource
* masks for these instructions.
*/
int baseReg = (lir->opcode == kThumb2LdrPcRel12) ?
- lir->operands[0] : rLR;
+ lir->operands[0] : rARM_LR;
// Add new Adr to generate the address
LIR* newAdr = rawLIR(cUnit, lir->dalvikOffset, kThumb2Adr,
@@ -1219,7 +1219,7 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit* cUnit,
0, lir->target);
oatInsertLIRBefore((LIR*)lir, (LIR*)newMov16H);
lir->opcode = kThumb2AddRRR;
- lir->operands[1] = rPC;
+ lir->operands[1] = rARM_PC;
lir->operands[2] = lir->operands[0];
oatSetupResourceMasks(cUnit, lir);
res = kRetryAll;
@@ -1304,9 +1304,9 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit* cUnit,
bits |= value;
break;
case kFmtDfp: {
- DCHECK(DOUBLEREG(operand));
+ DCHECK(ARM_DOUBLEREG(operand));
DCHECK_EQ((operand & 0x1), 0U);
- int regName = (operand & FP_REG_MASK) >> 1;
+ int regName = (operand & ARM_FP_REG_MASK) >> 1;
/* Snag the 1-bit slice and position it */
value = ((regName & 0x10) >> 4) << encoder->fieldLoc[i].end;
/* Extract and position the 4-bit slice */
@@ -1315,7 +1315,7 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit* cUnit,
break;
}
case kFmtSfp:
- DCHECK(SINGLEREG(operand));
+ DCHECK(ARM_SINGLEREG(operand));
/* Snag the 1-bit slice and position it */
value = (operand & 0x1) << encoder->fieldLoc[i].end;
/* Extract and position the 4-bit slice */
diff --git a/src/compiler/codegen/arm/FP/Thumb2VFP.cc b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
index 3ea28c9f42..1774a5b23a 100644
--- a/src/compiler/codegen/arm/FP/Thumb2VFP.cc
+++ b/src/compiler/codegen/arm/FP/Thumb2VFP.cc
@@ -98,9 +98,9 @@ bool genArithOpDouble(CompilationUnit* cUnit, Instruction::Code opcode,
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
DCHECK(rlDest.wide);
DCHECK(rlResult.wide);
- newLIR3(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlSrc1.lowReg, rlSrc1.highReg),
- S2D(rlSrc2.lowReg, rlSrc2.highReg));
+ newLIR3(cUnit, (ArmOpcode)op, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlSrc1.lowReg, rlSrc1.highReg),
+ s2d(rlSrc2.lowReg, rlSrc2.highReg));
storeValueWide(cUnit, rlDest, rlResult);
return false;
}
@@ -141,14 +141,14 @@ bool genConversion(CompilationUnit* cUnit, Instruction::Code opcode,
}
if (rlSrc.wide) {
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
- srcReg = S2D(rlSrc.lowReg, rlSrc.highReg);
+ srcReg = s2d(rlSrc.lowReg, rlSrc.highReg);
} else {
rlSrc = loadValue(cUnit, rlSrc, kFPReg);
srcReg = rlSrc.lowReg;
}
if (rlDest.wide) {
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, (ArmOpcode)op, S2D(rlResult.lowReg, rlResult.highReg),
+ newLIR2(cUnit, (ArmOpcode)op, s2d(rlResult.lowReg, rlResult.highReg),
srcReg);
storeValueWide(cUnit, rlDest, rlResult);
} else {
@@ -171,8 +171,8 @@ void genFusedFPCmpBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
rlSrc2 = oatGetSrcWide(cUnit, mir, 2);
rlSrc1 = loadValueWide(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValueWide(cUnit, rlSrc2, kFPReg);
- newLIR2(cUnit, kThumb2Vcmpd, S2D(rlSrc1.lowReg, r1Src2.highReg),
- S2D(rlSrc2.lowReg, rlSrc2.highReg));
+ newLIR2(cUnit, kThumb2Vcmpd, s2d(rlSrc1.lowReg, rlSrc2.highReg),
+ s2d(rlSrc2.lowReg, rlSrc2.highReg));
} else {
rlSrc1 = oatGetSrc(cUnit, mir, 0);
rlSrc2 = oatGetSrc(cUnit, mir, 1);
@@ -246,8 +246,8 @@ bool genCmpFP(CompilationUnit* cUnit, Instruction::Code opcode, RegLocation rlDe
oatClobberSReg(cUnit, rlDest.sRegLow);
rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true);
loadConstant(cUnit, rlResult.lowReg, defaultResult);
- newLIR2(cUnit, kThumb2Vcmpd, S2D(rlSrc1.lowReg, r1Src2.highReg),
- S2D(rlSrc2.lowReg, rlSrc2.highReg));
+ newLIR2(cUnit, kThumb2Vcmpd, s2d(rlSrc1.lowReg, rlSrc2.highReg),
+ s2d(rlSrc2.lowReg, rlSrc2.highReg));
} else {
rlSrc1 = loadValue(cUnit, rlSrc1, kFPReg);
rlSrc2 = loadValue(cUnit, rlSrc2, kFPReg);
@@ -256,7 +256,7 @@ bool genCmpFP(CompilationUnit* cUnit, Instruction::Code opcode, RegLocation rlDe
loadConstant(cUnit, rlResult.lowReg, defaultResult);
newLIR2(cUnit, kThumb2Vcmps, rlSrc1.lowReg, rlSrc2.lowReg);
}
- DCHECK(!FPREG(rlResult.lowReg));
+ DCHECK(!ARM_FPREG(rlResult.lowReg));
newLIR0(cUnit, kThumb2Fmstat);
opIT(cUnit, (defaultResult == -1) ? kArmCondGt : kArmCondMi, "");
diff --git a/src/compiler/codegen/arm/Thumb2/Factory.cc b/src/compiler/codegen/arm/Thumb2/Factory.cc
index c373e35286..fc3aaa0e95 100644
--- a/src/compiler/codegen/arm/Thumb2/Factory.cc
+++ b/src/compiler/codegen/arm/Thumb2/Factory.cc
@@ -18,9 +18,9 @@ namespace art {
/* This file contains codegen for the Thumb ISA. */
-static int coreRegs[] = {r0, r1, r2, r3, rSUSPEND, r5, r6, r7, r8, rSELF, r10,
- r11, r12, rSP, rLR, rPC};
-static int reservedRegs[] = {rSUSPEND, rSELF, rSP, rLR, rPC};
+static int coreRegs[] = {r0, r1, r2, r3, rARM_SUSPEND, r5, r6, r7, r8, rARM_SELF, r10,
+ r11, r12, rARM_SP, rARM_LR, rARM_PC};
+static int reservedRegs[] = {rARM_SUSPEND, rARM_SELF, rARM_SP, rARM_LR, rARM_PC};
static int fpRegs[] = {fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
@@ -54,7 +54,7 @@ int encodeImmSingle(int value)
LIR* loadFPConstantValue(CompilationUnit* cUnit, int rDest, int value)
{
int encodedImm = encodeImmSingle(value);
- DCHECK(SINGLEREG(rDest));
+ DCHECK(ARM_SINGLEREG(rDest));
if (encodedImm >= 0) {
return newLIR2(cUnit, kThumb2Vmovs_IMM8, rDest, encodedImm);
}
@@ -136,12 +136,12 @@ LIR* loadConstantNoClobber(CompilationUnit* cUnit, int rDest, int value)
LIR* res;
int modImm;
- if (FPREG(rDest)) {
+ if (ARM_FPREG(rDest)) {
return loadFPConstantValue(cUnit, rDest, value);
}
/* See if the value can be constructed cheaply */
- if (LOWREG(rDest) && (value >= 0) && (value <= 255)) {
+ if (ARM_LOWREG(rDest) && (value >= 0) && (value <= 255)) {
return newLIR2(cUnit, kThumbMovImm, rDest, value);
}
/* Check Modified immediate special cases */
@@ -212,7 +212,7 @@ LIR* opReg(CompilationUnit* cUnit, OpKind op, int rDestSrc)
LIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
int rSrc2, int shift)
{
- bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2));
+ bool thumbForm = ((shift == 0) && ARM_LOWREG(rDestSrc1) && ARM_LOWREG(rSrc2));
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdc:
@@ -231,9 +231,9 @@ LIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
case kOpCmp:
if (thumbForm)
opcode = kThumbCmpRR;
- else if ((shift == 0) && !LOWREG(rDestSrc1) && !LOWREG(rSrc2))
+ else if ((shift == 0) && !ARM_LOWREG(rDestSrc1) && !ARM_LOWREG(rSrc2))
opcode = kThumbCmpHH;
- else if ((shift == 0) && LOWREG(rDestSrc1))
+ else if ((shift == 0) && ARM_LOWREG(rDestSrc1))
opcode = kThumbCmpLH;
else if (shift == 0)
opcode = kThumbCmpHL;
@@ -245,11 +245,11 @@ LIR* opRegRegShift(CompilationUnit* cUnit, OpKind op, int rDestSrc1,
break;
case kOpMov:
DCHECK_EQ(shift, 0);
- if (LOWREG(rDestSrc1) && LOWREG(rSrc2))
+ if (ARM_LOWREG(rDestSrc1) && ARM_LOWREG(rSrc2))
opcode = kThumbMovRR;
- else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2))
+ else if (!ARM_LOWREG(rDestSrc1) && !ARM_LOWREG(rSrc2))
opcode = kThumbMovRR_H2H;
- else if (LOWREG(rDestSrc1))
+ else if (ARM_LOWREG(rDestSrc1))
opcode = kThumbMovRR_H2L;
else
opcode = kThumbMovRR_L2H;
@@ -334,8 +334,8 @@ LIR* opRegRegRegShift(CompilationUnit* cUnit, OpKind op, int rDest, int rSrc1,
int rSrc2, int shift)
{
ArmOpcode opcode = kThumbBkpt;
- bool thumbForm = (shift == 0) && LOWREG(rDest) && LOWREG(rSrc1) &&
- LOWREG(rSrc2);
+ bool thumbForm = (shift == 0) && ARM_LOWREG(rDest) && ARM_LOWREG(rSrc1) &&
+ ARM_LOWREG(rSrc2);
switch (op) {
case kOpAdd:
opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR;
@@ -411,7 +411,7 @@ LIR* opRegRegImm(CompilationUnit* cUnit, OpKind op, int rDest, int rSrc1,
int absValue = (neg) ? -value : value;
ArmOpcode opcode = kThumbBkpt;
ArmOpcode altOpcode = kThumbBkpt;
- bool allLowRegs = (LOWREG(rDest) && LOWREG(rSrc1));
+ bool allLowRegs = (ARM_LOWREG(rDest) && ARM_LOWREG(rSrc1));
int modImm = modifiedImmediate(value);
int modImmNeg = modifiedImmediate(-value);
@@ -434,10 +434,10 @@ LIR* opRegRegImm(CompilationUnit* cUnit, OpKind op, int rDest, int rSrc1,
case kOpRor:
return newLIR3(cUnit, kThumb2RorRRI5, rDest, rSrc1, value);
case kOpAdd:
- if (LOWREG(rDest) && (rSrc1 == r13sp) &&
+ if (ARM_LOWREG(rDest) && (rSrc1 == r13sp) &&
(value <= 1020) && ((value & 0x3)==0)) {
return newLIR3(cUnit, kThumbAddSpRel, rDest, rSrc1, value >> 2);
- } else if (LOWREG(rDest) && (rSrc1 == r15pc) &&
+ } else if (ARM_LOWREG(rDest) && (rSrc1 == r15pc) &&
(value <= 1020) && ((value & 0x3)==0)) {
return newLIR3(cUnit, kThumbAddPcRel, rDest, rSrc1, value >> 2);
}
@@ -529,7 +529,7 @@ LIR* opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value)
{
bool neg = (value < 0);
int absValue = (neg) ? -value : value;
- bool shortForm = (((absValue & 0xff) == absValue) && LOWREG(rDestSrc1));
+ bool shortForm = (((absValue & 0xff) == absValue) && ARM_LOWREG(rDestSrc1));
ArmOpcode opcode = kThumbBkpt;
switch (op) {
case kOpAdd:
@@ -549,9 +549,9 @@ LIR* opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value)
}
break;
case kOpCmp:
- if (LOWREG(rDestSrc1) && shortForm)
+ if (ARM_LOWREG(rDestSrc1) && shortForm)
opcode = (shortForm) ? kThumbCmpRI8 : kThumbCmpRR;
- else if (LOWREG(rDestSrc1))
+ else if (ARM_LOWREG(rDestSrc1))
opcode = kThumbCmpRR;
else {
shortForm = false;
@@ -609,9 +609,9 @@ LIR* loadConstantValueWide(CompilationUnit* cUnit, int rDestLo, int rDestHi,
{
int encodedImm = encodeImmDouble(valLo, valHi);
LIR* res;
- if (FPREG(rDestLo)) {
+ if (ARM_FPREG(rDestLo)) {
if (encodedImm >= 0) {
- res = newLIR2(cUnit, kThumb2Vmovd_IMM8, S2D(rDestLo, rDestHi),
+ res = newLIR2(cUnit, kThumb2Vmovd_IMM8, s2d(rDestLo, rDestHi),
encodedImm);
} else {
LIR* dataTarget = scanLiteralPoolWide(cUnit->literalList, valLo, valHi);
@@ -620,7 +620,7 @@ LIR* loadConstantValueWide(CompilationUnit* cUnit, int rDestLo, int rDestHi,
}
LIR* loadPcRel =
rawLIR(cUnit, cUnit->currentDalvikOffset, kThumb2Vldrd,
- S2D(rDestLo, rDestHi), r15pc, 0, 0, 0, dataTarget);
+ s2d(rDestLo, rDestHi), r15pc, 0, 0, 0, dataTarget);
setMemRefType(loadPcRel, true, kLiteral);
loadPcRel->aliasInfo = (intptr_t)dataTarget;
oatAppendLIR(cUnit, (LIR* ) loadPcRel);
@@ -640,19 +640,19 @@ int encodeShift(int code, int amount) {
LIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rDest,
int scale, OpSize size)
{
- bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest);
+ bool allLowRegs = ARM_LOWREG(rBase) && ARM_LOWREG(rIndex) && ARM_LOWREG(rDest);
LIR* load;
ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (allLowRegs && (scale == 0));
int regPtr;
- if (FPREG(rDest)) {
- if (SINGLEREG(rDest)) {
+ if (ARM_FPREG(rDest)) {
+ if (ARM_SINGLEREG(rDest)) {
DCHECK((size == kWord) || (size == kSingle));
opcode = kThumb2Vldrs;
size = kSingle;
} else {
- DCHECK(DOUBLEREG(rDest));
+ DCHECK(ARM_DOUBLEREG(rDest));
DCHECK((size == kLong) || (size == kDouble));
DCHECK_EQ((rDest & 0x1), 0);
opcode = kThumb2Vldrd;
@@ -705,19 +705,19 @@ LIR* loadBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rDest,
LIR* storeBaseIndexed(CompilationUnit* cUnit, int rBase, int rIndex, int rSrc,
int scale, OpSize size)
{
- bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc);
+ bool allLowRegs = ARM_LOWREG(rBase) && ARM_LOWREG(rIndex) && ARM_LOWREG(rSrc);
LIR* store;
ArmOpcode opcode = kThumbBkpt;
bool thumbForm = (allLowRegs && (scale == 0));
int regPtr;
- if (FPREG(rSrc)) {
- if (SINGLEREG(rSrc)) {
+ if (ARM_FPREG(rSrc)) {
+ if (ARM_SINGLEREG(rSrc)) {
DCHECK((size == kWord) || (size == kSingle));
opcode = kThumb2Vstrs;
size = kSingle;
} else {
- DCHECK(DOUBLEREG(rSrc));
+ DCHECK(ARM_DOUBLEREG(rSrc));
DCHECK((size == kLong) || (size == kDouble));
DCHECK_EQ((rSrc & 0x1), 0);
opcode = kThumb2Vstrd;
@@ -777,17 +777,17 @@ LIR* loadBaseDispBody(CompilationUnit* cUnit, int rBase,
ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
- bool allLowRegs = (LOWREG(rBase) && LOWREG(rDest));
+ bool allLowRegs = (ARM_LOWREG(rBase) && ARM_LOWREG(rDest));
int encodedDisp = displacement;
bool is64bit = false;
switch (size) {
case kDouble:
case kLong:
is64bit = true;
- if (FPREG(rDest)) {
- if (SINGLEREG(rDest)) {
- DCHECK(FPREG(rDestHi));
- rDest = S2D(rDest, rDestHi);
+ if (ARM_FPREG(rDest)) {
+ if (ARM_SINGLEREG(rDest)) {
+ DCHECK(ARM_FPREG(rDestHi));
+ rDest = s2d(rDest, rDestHi);
}
opcode = kThumb2Vldrd;
if (displacement <= 1020) {
@@ -804,7 +804,7 @@ LIR* loadBaseDispBody(CompilationUnit* cUnit, int rBase,
}
case kSingle:
case kWord:
- if (FPREG(rDest)) {
+ if (ARM_FPREG(rDest)) {
opcode = kThumb2Vldrs;
if (displacement <= 1020) {
shortForm = true;
@@ -812,12 +812,12 @@ LIR* loadBaseDispBody(CompilationUnit* cUnit, int rBase,
}
break;
}
- if (LOWREG(rDest) && (rBase == r15pc) &&
+ if (ARM_LOWREG(rDest) && (rBase == r15pc) &&
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
opcode = kThumbLdrPcRel;
- } else if (LOWREG(rDest) && (rBase == r13sp) &&
+ } else if (ARM_LOWREG(rDest) && (rBase == r13sp) &&
(displacement <= 1020) && (displacement >= 0)) {
shortForm = true;
encodedDisp >>= 2;
@@ -878,7 +878,7 @@ LIR* loadBaseDispBody(CompilationUnit* cUnit, int rBase,
}
// TODO: in future may need to differentiate Dalvik accesses w/ spills
- if (rBase == rSP) {
+ if (rBase == rARM_SP) {
annotateDalvikRegAccess(load, displacement >> 2, true /* isLoad */, is64bit);
}
return load;
@@ -906,21 +906,21 @@ LIR* storeBaseDispBody(CompilationUnit* cUnit, int rBase, int displacement,
ArmOpcode opcode = kThumbBkpt;
bool shortForm = false;
bool thumb2Form = (displacement < 4092 && displacement >= 0);
- bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc));
+ bool allLowRegs = (ARM_LOWREG(rBase) && ARM_LOWREG(rSrc));
int encodedDisp = displacement;
bool is64bit = false;
switch (size) {
case kLong:
case kDouble:
is64bit = true;
- if (!FPREG(rSrc)) {
+ if (!ARM_FPREG(rSrc)) {
res = storeBaseDispBody(cUnit, rBase, displacement, rSrc, -1, kWord);
storeBaseDispBody(cUnit, rBase, displacement + 4, rSrcHi, -1, kWord);
return res;
}
- if (SINGLEREG(rSrc)) {
- DCHECK(FPREG(rSrcHi));
- rSrc = S2D(rSrc, rSrcHi);
+ if (ARM_SINGLEREG(rSrc)) {
+ DCHECK(ARM_FPREG(rSrcHi));
+ rSrc = s2d(rSrc, rSrcHi);
}
opcode = kThumb2Vstrd;
if (displacement <= 1020) {
@@ -930,8 +930,8 @@ LIR* storeBaseDispBody(CompilationUnit* cUnit, int rBase, int displacement,
break;
case kSingle:
case kWord:
- if (FPREG(rSrc)) {
- DCHECK(SINGLEREG(rSrc));
+ if (ARM_FPREG(rSrc)) {
+ DCHECK(ARM_SINGLEREG(rSrc));
opcode = kThumb2Vstrs;
if (displacement <= 1020) {
shortForm = true;
@@ -984,7 +984,7 @@ LIR* storeBaseDispBody(CompilationUnit* cUnit, int rBase, int displacement,
}
// TODO: In future, may need to differentiate Dalvik & spill accesses
- if (rBase == rSP) {
+ if (rBase == rARM_SP) {
annotateDalvikRegAccess(store, displacement >> 2, false /* isLoad */,
is64bit);
}
@@ -1011,14 +1011,14 @@ void loadPair(CompilationUnit* cUnit, int base, int lowReg, int highReg)
LIR* fpRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
{
int opcode;
- DCHECK_EQ(DOUBLEREG(rDest), DOUBLEREG(rSrc));
- if (DOUBLEREG(rDest)) {
+ DCHECK_EQ(ARM_DOUBLEREG(rDest), ARM_DOUBLEREG(rSrc));
+ if (ARM_DOUBLEREG(rDest)) {
opcode = kThumb2Vmovd;
} else {
- if (SINGLEREG(rDest)) {
- opcode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
+ if (ARM_SINGLEREG(rDest)) {
+ opcode = ARM_SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr;
} else {
- DCHECK(SINGLEREG(rSrc));
+ DCHECK(ARM_SINGLEREG(rSrc));
opcode = kThumb2Fmrs;
}
}
diff --git a/src/compiler/codegen/arm/Thumb2/Gen.cc b/src/compiler/codegen/arm/Thumb2/Gen.cc
index cbe6b14b0e..0a8e579477 100644
--- a/src/compiler/codegen/arm/Thumb2/Gen.cc
+++ b/src/compiler/codegen/arm/Thumb2/Gen.cc
@@ -42,7 +42,7 @@ RegLocation argLoc(CompilationUnit* cUnit, RegLocation loc)
// Bad case - half in register, half in frame. Just punt
loc.location = kLocInvalid;
} else if (argNum < 2) {
- loc.lowReg = rARG1 + argNum;
+ loc.lowReg = rARM_ARG1 + argNum;
loc.highReg = loc.lowReg + 1;
loc.location = kLocPhysReg;
} else {
@@ -50,7 +50,7 @@ RegLocation argLoc(CompilationUnit* cUnit, RegLocation loc)
}
} else {
if (argNum < 3) {
- loc.lowReg = rARG1 + argNum;
+ loc.lowReg = rARM_ARG1 + argNum;
loc.location = kLocPhysReg;
} else {
loc.location = kLocDalvikFrame;
@@ -69,10 +69,10 @@ RegLocation loadArg(CompilationUnit* cUnit, RegLocation loc)
if (loc.location == kLocDalvikFrame) {
int start = (inPosition(cUnit, loc.sRegLow) + 1) * sizeof(uint32_t);
loc.lowReg = oatAllocTemp(cUnit);
- loadWordDisp(cUnit, rSP, start, loc.lowReg);
+ loadWordDisp(cUnit, rARM_SP, start, loc.lowReg);
if (loc.wide) {
loc.highReg = oatAllocTemp(cUnit);
- loadWordDisp(cUnit, rSP, start + sizeof(uint32_t), loc.highReg);
+ loadWordDisp(cUnit, rARM_SP, start + sizeof(uint32_t), loc.highReg);
}
loc.location = kLocPhysReg;
}
@@ -88,7 +88,7 @@ void lockLiveArgs(CompilationUnit* cUnit, MIR* mir)
int vReg = SRegToVReg(cUnit, mir->ssaRep->uses[i]);
int inPosition = vReg - firstIn;
if (inPosition < numArgRegs) {
- oatLockTemp(cUnit, rARG1 + inPosition);
+ oatLockTemp(cUnit, rARM_ARG1 + inPosition);
}
}
}
@@ -239,7 +239,7 @@ void genSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
break;
case kConstFunction:
genPrintLabel(cUnit, mir);
- loadConstant(cUnit, rRET0, mir->dalvikInsn.vB);
+ loadConstant(cUnit, rARM_RET0, mir->dalvikInsn.vB);
nextMir = getNextMir(cUnit, &bb, mir);
break;
case kIGet:
@@ -291,7 +291,7 @@ void genSpecialCase(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir,
if (specialCase != kIdentity) {
genPrintLabel(cUnit, nextMir);
}
- newLIR1(cUnit, kThumbBx, rLR);
+ newLIR1(cUnit, kThumbBx, rARM_LR);
cUnit->coreSpillMask = 0;
cUnit->numCoreSpills = 0;
cUnit->fpSpillMask = 0;
@@ -356,14 +356,14 @@ LIR* opIT(CompilationUnit* cUnit, ArmConditionCode code, const char* guide)
* The test loop will look something like:
*
* adr rBase, <table>
- * ldr rVal, [rSP, vRegOff]
+ * ldr rVal, [rARM_SP, vRegOff]
* mov rIdx, #tableSize
* lp:
* ldmia rBase!, {rKey, rDisp}
* sub rIdx, #1
* cmp rVal, rKey
* ifeq
- * add rPC, rDisp ; This is the branch from which we compute displacement
+ * add rARM_PC, rDisp ; This is the branch from which we compute displacement
* cbnz rIdx, lp
*/
void genSparseSwitch(CompilationUnit* cUnit, uint32_t tableOffset,
@@ -488,12 +488,12 @@ void genFillArrayData(CompilationUnit* cUnit, uint32_t tableOffset, RegLocation
// Making a call - use explicit registers
oatFlushAllRegs(cUnit); /* Everything to home location */
loadValueDirectFixed(cUnit, rlSrc, r0);
- loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode),
- rLR);
+ loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pHandleFillArrayDataFromCode),
+ rARM_LR);
// Materialize a pointer to the fill data image
newLIR3(cUnit, kThumb2Adr, r1, 0, (intptr_t)tabRec);
oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+ LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
}
@@ -511,8 +511,8 @@ void genNegDouble(CompilationUnit* cUnit, RegLocation rlDest, RegLocation rlSrc)
RegLocation rlResult;
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, kThumb2Vnegd, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlSrc.lowReg, rlSrc.highReg));
+ newLIR2(cUnit, kThumb2Vnegd, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlSrc.lowReg, rlSrc.highReg));
storeValueWide(cUnit, rlDest, rlResult);
}
@@ -549,7 +549,7 @@ void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
loadValueDirectFixed(cUnit, rlSrc, r0); // Get obj
oatLockCallTemps(cUnit); // Prepare for explicit register usage
genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
- loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
+ loadWordDisp(cUnit, rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
newLIR3(cUnit, kThumb2Ldrex, r1, r0,
Object::MonitorOffset().Int32Value() >> 2); // Get object->lock
// Align owner
@@ -564,9 +564,9 @@ void genMonitorEnter(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
opRegImm(cUnit, kOpCmp, r1, 0);
opIT(cUnit, kArmCondNe, "T");
// Go expensive route - artLockObjectFromCode(self, obj);
- loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pLockObjectFromCode), rLR);
+ loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pLockObjectFromCode), rARM_LR);
oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+ LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
oatGenMemBarrier(cUnit, kSY);
}
@@ -585,7 +585,7 @@ void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
oatLockCallTemps(cUnit); // Prepare for explicit register usage
genNullCheck(cUnit, rlSrc.sRegLow, r0, optFlags);
loadWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r1); // Get lock
- loadWordDisp(cUnit, rSELF, Thread::ThinLockIdOffset().Int32Value(), r2);
+ loadWordDisp(cUnit, rARM_SELF, Thread::ThinLockIdOffset().Int32Value(), r2);
// Is lock unheld on lock or held by us (==threadId) on unlock?
opRegRegImm(cUnit, kOpAnd, r3, r1,
(LW_HASH_STATE_MASK << LW_HASH_STATE_SHIFT));
@@ -596,9 +596,9 @@ void genMonitorExit(CompilationUnit* cUnit, int optFlags, RegLocation rlSrc)
opIT(cUnit, kArmCondEq, "EE");
storeWordDisp(cUnit, r0, Object::MonitorOffset().Int32Value(), r3);
// Go expensive route - UnlockObjectFromCode(obj);
- loadWordDisp(cUnit, rSELF, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rLR);
+ loadWordDisp(cUnit, rARM_SELF, ENTRYPOINT_OFFSET(pUnlockObjectFromCode), rARM_LR);
oatClobberCalleeSave(cUnit);
- LIR* callInst = opReg(cUnit, kOpBlx, rLR);
+ LIR* callInst = opReg(cUnit, kOpBlx, rARM_LR);
markSafepointPC(cUnit, callInst);
oatGenMemBarrier(cUnit, kSY);
}
@@ -643,7 +643,7 @@ void genCmpLong(CompilationUnit* cUnit, RegLocation rlDest,
target1 = newLIR0(cUnit, kPseudoTargetLabel);
- RegLocation rlTemp = LOC_C_RETURN; // Just using as template, will change
+ RegLocation rlTemp = locCReturn(); // Just using as template, will change
rlTemp.lowReg = tReg;
storeValue(cUnit, rlDest, rlTemp);
oatFreeTemp(cUnit, tReg);
@@ -708,13 +708,13 @@ LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
LIR* branch;
int modImm;
ArmConditionCode armCond = oatArmConditionEncoding(cond);
- if ((LOWREG(reg)) && (checkValue == 0) &&
+ if ((ARM_LOWREG(reg)) && (checkValue == 0) &&
((armCond == kArmCondEq) || (armCond == kArmCondNe))) {
branch = newLIR2(cUnit, (armCond == kArmCondEq) ? kThumb2Cbz : kThumb2Cbnz,
reg, 0);
} else {
modImm = modifiedImmediate(checkValue);
- if (LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
+ if (ARM_LOWREG(reg) && ((checkValue & 0xff) == checkValue)) {
newLIR2(cUnit, kThumbCmpRI8, reg, checkValue);
} else if (modImm >= 0) {
newLIR2(cUnit, kThumb2CmpRI8, reg, modImm);
@@ -732,13 +732,13 @@ LIR* opRegCopyNoInsert(CompilationUnit* cUnit, int rDest, int rSrc)
{
LIR* res;
int opcode;
- if (FPREG(rDest) || FPREG(rSrc))
+ if (ARM_FPREG(rDest) || ARM_FPREG(rSrc))
return fpRegCopy(cUnit, rDest, rSrc);
- if (LOWREG(rDest) && LOWREG(rSrc))
+ if (ARM_LOWREG(rDest) && ARM_LOWREG(rSrc))
opcode = kThumbMovRR;
- else if (!LOWREG(rDest) && !LOWREG(rSrc))
+ else if (!ARM_LOWREG(rDest) && !ARM_LOWREG(rSrc))
opcode = kThumbMovRR_H2H;
- else if (LOWREG(rDest))
+ else if (ARM_LOWREG(rDest))
opcode = kThumbMovRR_H2L;
else
opcode = kThumbMovRR_L2H;
@@ -759,19 +759,19 @@ LIR* opRegCopy(CompilationUnit* cUnit, int rDest, int rSrc)
void opRegCopyWide(CompilationUnit* cUnit, int destLo, int destHi,
int srcLo, int srcHi)
{
- bool destFP = FPREG(destLo) && FPREG(destHi);
- bool srcFP = FPREG(srcLo) && FPREG(srcHi);
- DCHECK_EQ(FPREG(srcLo), FPREG(srcHi));
- DCHECK_EQ(FPREG(destLo), FPREG(destHi));
+ bool destFP = ARM_FPREG(destLo) && ARM_FPREG(destHi);
+ bool srcFP = ARM_FPREG(srcLo) && ARM_FPREG(srcHi);
+ DCHECK_EQ(ARM_FPREG(srcLo), ARM_FPREG(srcHi));
+ DCHECK_EQ(ARM_FPREG(destLo), ARM_FPREG(destHi));
if (destFP) {
if (srcFP) {
- opRegCopy(cUnit, S2D(destLo, destHi), S2D(srcLo, srcHi));
+ opRegCopy(cUnit, s2d(destLo, destHi), s2d(srcLo, srcHi));
} else {
- newLIR3(cUnit, kThumb2Fmdrr, S2D(destLo, destHi), srcLo, srcHi);
+ newLIR3(cUnit, kThumb2Fmdrr, s2d(destLo, destHi), srcLo, srcHi);
}
} else {
if (srcFP) {
- newLIR3(cUnit, kThumb2Fmrrd, destLo, destHi, S2D(srcLo, srcHi));
+ newLIR3(cUnit, kThumb2Fmrrd, destLo, destHi, s2d(srcLo, srcHi));
} else {
// Handle overlap
if (srcHi == destLo) {
@@ -872,7 +872,7 @@ void markGCCard(CompilationUnit* cUnit, int valReg, int tgtAddrReg)
int regCardBase = oatAllocTemp(cUnit);
int regCardNo = oatAllocTemp(cUnit);
LIR* branchOver = opCmpImmBranch(cUnit, kCondEq, valReg, 0, NULL);
- loadWordDisp(cUnit, rSELF, Thread::CardTableOffset().Int32Value(), regCardBase);
+ loadWordDisp(cUnit, rARM_SELF, Thread::CardTableOffset().Int32Value(), regCardBase);
opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, CardTable::kCardShift);
storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
kUnsignedByte);
@@ -994,18 +994,18 @@ bool genInlinedSqrt(CompilationUnit* cUnit, CallInfo* info) {
RegLocation rlDest = inlineTargetWide(cUnit, info); // double place for result
rlSrc = loadValueWide(cUnit, rlSrc, kFPReg);
RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kFPReg, true);
- newLIR2(cUnit, kThumb2Vsqrtd, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlSrc.lowReg, rlSrc.highReg));
- newLIR2(cUnit, kThumb2Vcmpd, S2D(rlResult.lowReg, rlResult.highReg),
- S2D(rlResult.lowReg, rlResult.highReg));
+ newLIR2(cUnit, kThumb2Vsqrtd, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlSrc.lowReg, rlSrc.highReg));
+ newLIR2(cUnit, kThumb2Vcmpd, s2d(rlResult.lowReg, rlResult.highReg),
+ s2d(rlResult.lowReg, rlResult.highReg));
newLIR0(cUnit, kThumb2Fmstat);
branch = newLIR2(cUnit, kThumbBCond, 0, kArmCondEq);
oatClobberCalleeSave(cUnit);
oatLockCallTemps(cUnit); // Using fixed registers
int rTgt = loadHelper(cUnit, ENTRYPOINT_OFFSET(pSqrt));
- newLIR3(cUnit, kThumb2Fmrrd, r0, r1, S2D(rlSrc.lowReg, rlSrc.highReg));
+ newLIR3(cUnit, kThumb2Fmrrd, r0, r1, s2d(rlSrc.lowReg, rlSrc.highReg));
newLIR1(cUnit, kThumbBlxR, rTgt);
- newLIR3(cUnit, kThumb2Fmdrr, S2D(rlResult.lowReg, rlResult.highReg), r0, r1);
+ newLIR3(cUnit, kThumb2Fmdrr, s2d(rlResult.lowReg, rlResult.highReg), r0, r1);
branch->target = newLIR0(cUnit, kPseudoTargetLabel);
storeValueWide(cUnit, rlDest, rlResult);
return true;
@@ -1048,7 +1048,7 @@ void genDivZeroCheck(CompilationUnit* cUnit, int regLo, int regHi)
// Test suspend flag, return target of taken suspend branch
LIR* opTestSuspend(CompilationUnit* cUnit, LIR* target)
{
- newLIR2(cUnit, kThumbSubRI8, rSUSPEND, 1);
+ newLIR2(cUnit, kThumbSubRI8, rARM_SUSPEND, 1);
return opCondBranch(cUnit, (target == NULL) ? kCondEq : kCondNe, target);
}
diff --git a/src/compiler/codegen/arm/Thumb2/Ralloc.cc b/src/compiler/codegen/arm/Thumb2/Ralloc.cc
index 894488a073..ab5cf337bb 100644
--- a/src/compiler/codegen/arm/Thumb2/Ralloc.cc
+++ b/src/compiler/codegen/arm/Thumb2/Ralloc.cc
@@ -68,7 +68,7 @@ void oatInitializeRegAlloc(CompilationUnit* cUnit)
oatInitPool(pool->FPRegs, fpRegs, pool->numFPRegs);
// Keep special registers from being allocated
for (int i = 0; i < numReserved; i++) {
- if (NO_SUSPEND && (reservedRegs[i] == rSUSPEND)) {
+ if (NO_SUSPEND && (reservedRegs[i] == rARM_SUSPEND)) {
//To measure cost of suspend check
continue;
}
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-27 09:17:48 +0000