diff options
Diffstat (limited to 'disassembler')
| -rw-r--r-- | disassembler/Android.bp | 58 | ||||
| -rw-r--r-- | disassembler/Android.mk | 115 | ||||
| -rw-r--r-- | disassembler/disassembler.cc | 20 | ||||
| -rw-r--r-- | disassembler/disassembler.h | 22 | ||||
| -rw-r--r-- | disassembler/disassembler_arm.cc | 2056 | ||||
| -rw-r--r-- | disassembler/disassembler_arm.h | 27 | ||||
| -rw-r--r-- | disassembler/disassembler_arm64.cc | 58 | ||||
| -rw-r--r-- | disassembler/disassembler_arm64.h | 27 | ||||
| -rw-r--r-- | disassembler/disassembler_mips.cc | 223 | ||||
| -rw-r--r-- | disassembler/disassembler_mips.h | 5 | ||||
| -rw-r--r-- | disassembler/disassembler_x86.cc | 131 | ||||
| -rw-r--r-- | disassembler/disassembler_x86.h | 1 |
12 files changed, 644 insertions, 2099 deletions
diff --git a/disassembler/Android.bp b/disassembler/Android.bp new file mode 100644 index 0000000000..8dfada223b --- /dev/null +++ b/disassembler/Android.bp @@ -0,0 +1,58 @@ +// +// Copyright (C) 2012 The Android Open Source Project +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +art_cc_defaults { + name: "libart-disassembler-defaults", + defaults: ["art_defaults"], + host_supported: true, + clang: true, + srcs: [ + "disassembler.cc", + "disassembler_arm.cc", + "disassembler_arm64.cc", + "disassembler_mips.cc", + "disassembler_x86.cc", + ], + include_dirs: ["art/runtime"], + + shared_libs: [ + "libbase", + ], + export_include_dirs: ["."], +} + +art_cc_library { + name: "libart-disassembler", + defaults: ["libart-disassembler-defaults"], + shared_libs: [ + // For disassembler_arm*. + "libvixl-arm", + "libvixl-arm64", + ], +} + +art_cc_library { + name: "libartd-disassembler", + defaults: [ + "libart-disassembler-defaults", + "art_debug_defaults", + ], + shared_libs: [ + // For disassembler_arm*. + "libvixld-arm", + "libvixld-arm64", + ], +} diff --git a/disassembler/Android.mk b/disassembler/Android.mk deleted file mode 100644 index bf563c7660..0000000000 --- a/disassembler/Android.mk +++ /dev/null @@ -1,115 +0,0 @@ -# -# Copyright (C) 2012 The Android Open Source Project -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# - -LOCAL_PATH := $(call my-dir) - -include art/build/Android.common_build.mk - -LIBART_DISASSEMBLER_SRC_FILES := \ - disassembler.cc \ - disassembler_arm.cc \ - disassembler_arm64.cc \ - disassembler_mips.cc \ - disassembler_x86.cc - -# $(1): target or host -# $(2): ndebug or debug -define build-libart-disassembler - ifneq ($(1),target) - ifneq ($(1),host) - $$(error expected target or host for argument 1, received $(1)) - endif - endif - ifneq ($(2),ndebug) - ifneq ($(2),debug) - $$(error expected ndebug or debug for argument 2, received $(2)) - endif - endif - - art_target_or_host := $(1) - art_ndebug_or_debug := $(2) - - include $(CLEAR_VARS) - ifeq ($$(art_target_or_host),host) - LOCAL_IS_HOST_MODULE := true - endif - LOCAL_CPP_EXTENSION := $(ART_CPP_EXTENSION) - ifeq ($$(art_ndebug_or_debug),ndebug) - LOCAL_MODULE := libart-disassembler - else # debug - LOCAL_MODULE := libartd-disassembler - endif - - LOCAL_MODULE_TAGS := optional - LOCAL_MODULE_CLASS := SHARED_LIBRARIES - - LOCAL_SRC_FILES := $$(LIBART_DISASSEMBLER_SRC_FILES) - - ifeq ($$(art_target_or_host),target) - $(call set-target-local-clang-vars) - $(call set-target-local-cflags-vars,$(2)) - else # host - LOCAL_CLANG := $(ART_HOST_CLANG) - LOCAL_LDLIBS := $(ART_HOST_LDLIBS) - LOCAL_CFLAGS += $(ART_HOST_CFLAGS) - LOCAL_ASFLAGS += $(ART_HOST_ASFLAGS) - ifeq ($$(art_ndebug_or_debug),debug) - LOCAL_CFLAGS += $(ART_HOST_DEBUG_CFLAGS) - else - LOCAL_CFLAGS += $(ART_HOST_NON_DEBUG_CFLAGS) - endif - endif - - LOCAL_SHARED_LIBRARIES += liblog - ifeq ($$(art_ndebug_or_debug),debug) - LOCAL_SHARED_LIBRARIES += libartd - else - LOCAL_SHARED_LIBRARIES += libart - endif - - LOCAL_C_INCLUDES += $(ART_C_INCLUDES) art/runtime - LOCAL_EXPORT_C_INCLUDE_DIRS := $(LOCAL_PATH) - LOCAL_MULTILIB := both - - LOCAL_ADDITIONAL_DEPENDENCIES := art/build/Android.common_build.mk - LOCAL_ADDITIONAL_DEPENDENCIES += $(LOCAL_PATH)/Android.mk - LOCAL_NATIVE_COVERAGE := $(ART_COVERAGE) - # For disassembler_arm64. - ifeq ($$(art_ndebug_or_debug),debug) - LOCAL_SHARED_LIBRARIES += libvixl - else - LOCAL_SHARED_LIBRARIES += libvixl - endif - ifeq ($$(art_target_or_host),target) - include $(BUILD_SHARED_LIBRARY) - else # host - include $(BUILD_HOST_SHARED_LIBRARY) - endif -endef - -ifeq ($(ART_BUILD_TARGET_NDEBUG),true) - $(eval $(call build-libart-disassembler,target,ndebug)) -endif -ifeq ($(ART_BUILD_TARGET_DEBUG),true) - $(eval $(call build-libart-disassembler,target,debug)) -endif -# We always build dex2oat and dependencies, even if the host build is otherwise disabled, since they are used to cross compile for the target. -ifeq ($(ART_BUILD_HOST_NDEBUG),true) - $(eval $(call build-libart-disassembler,host,ndebug)) -endif -ifeq ($(ART_BUILD_HOST_DEBUG),true) - $(eval $(call build-libart-disassembler,host,debug)) -endif diff --git a/disassembler/disassembler.cc b/disassembler/disassembler.cc index e604c1f629..8eecc62cd5 100644 --- a/disassembler/disassembler.cc +++ b/disassembler/disassembler.cc @@ -18,30 +18,36 @@ #include <ostream> -#include "base/logging.h" -#include "base/stringprintf.h" +#include "android-base/logging.h" +#include "android-base/stringprintf.h" + #include "disassembler_arm.h" #include "disassembler_arm64.h" #include "disassembler_mips.h" #include "disassembler_x86.h" +using android::base::StringPrintf; + namespace art { +Disassembler::Disassembler(DisassemblerOptions* disassembler_options) + : disassembler_options_(disassembler_options) { + CHECK(disassembler_options_ != nullptr); +} + Disassembler* Disassembler::Create(InstructionSet instruction_set, DisassemblerOptions* options) { if (instruction_set == kArm || instruction_set == kThumb2) { return new arm::DisassemblerArm(options); } else if (instruction_set == kArm64) { return new arm64::DisassemblerArm64(options); - } else if (instruction_set == kMips) { - return new mips::DisassemblerMips(options, false); - } else if (instruction_set == kMips64) { - return new mips::DisassemblerMips(options, true); + } else if (instruction_set == kMips || instruction_set == kMips64) { + return new mips::DisassemblerMips(options); } else if (instruction_set == kX86) { return new x86::DisassemblerX86(options, false); } else if (instruction_set == kX86_64) { return new x86::DisassemblerX86(options, true); } else { - UNIMPLEMENTED(FATAL) << "no disassembler for " << instruction_set; + UNIMPLEMENTED(FATAL) << static_cast<uint32_t>(instruction_set); return nullptr; } } diff --git a/disassembler/disassembler.h b/disassembler/disassembler.h index b08031587f..1ef456cefd 100644 --- a/disassembler/disassembler.h +++ b/disassembler/disassembler.h @@ -21,15 +21,17 @@ #include <iosfwd> +#include "android-base/macros.h" + #include "arch/instruction_set.h" -#include "base/macros.h" namespace art { class DisassemblerOptions { public: - // Should the disassembler print absolute or relative addresses. - const bool absolute_addresses_; + using ThreadOffsetNameFunction = void (*)(std::ostream& os, uint32_t offset); + + ThreadOffsetNameFunction thread_offset_name_function_; // Base address for calculating relative code offsets when absolute_addresses_ is false. const uint8_t* const base_address_; @@ -37,6 +39,9 @@ class DisassemblerOptions { // End address (exclusive); const uint8_t* const end_address_; + // Should the disassembler print absolute or relative addresses. + const bool absolute_addresses_; + // If set, the disassembler is allowed to look at load targets in literal // pools. const bool can_read_literals_; @@ -44,10 +49,12 @@ class DisassemblerOptions { DisassemblerOptions(bool absolute_addresses, const uint8_t* base_address, const uint8_t* end_address, - bool can_read_literals) - : absolute_addresses_(absolute_addresses), + bool can_read_literals, + ThreadOffsetNameFunction fn) + : thread_offset_name_function_(fn), base_address_(base_address), end_address_(end_address), + absolute_addresses_(absolute_addresses), can_read_literals_(can_read_literals) {} private: @@ -75,10 +82,7 @@ class Disassembler { } protected: - explicit Disassembler(DisassemblerOptions* disassembler_options) - : disassembler_options_(disassembler_options) { - CHECK(disassembler_options_ != nullptr); - } + explicit Disassembler(DisassemblerOptions* disassembler_options); std::string FormatInstructionPointer(const uint8_t* begin); diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc index 286faf215a..3347dac535 100644 --- a/disassembler/disassembler_arm.cc +++ b/disassembler/disassembler_arm.cc @@ -16,1933 +16,223 @@ #include "disassembler_arm.h" -#include <inttypes.h> +#include <memory> +#include <string> -#include <ostream> -#include <sstream> +#include "android-base/logging.h" #include "arch/arm/registers_arm.h" #include "base/bit_utils.h" -#include "base/logging.h" -#include "base/stringprintf.h" -#include "thread.h" + +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wshadow" +#include "aarch32/instructions-aarch32.h" +#include "aarch32/disasm-aarch32.h" +#pragma GCC diagnostic pop namespace art { namespace arm { -size_t DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin) { - if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { - DumpArm(os, begin); - return 4; - } else { - // remove thumb specifier bits - begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); - return DumpThumb16(os, begin); - } -} - -void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { - if ((reinterpret_cast<intptr_t>(begin) & 1) == 0) { - for (const uint8_t* cur = begin; cur < end; cur += 4) { - DumpArm(os, cur); - } - } else { - // remove thumb specifier bits - begin = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(begin) & ~1); - end = reinterpret_cast<const uint8_t*>(reinterpret_cast<uintptr_t>(end) & ~1); - for (const uint8_t* cur = begin; cur < end;) { - cur += DumpThumb16(os, cur); +using vixl::aarch32::MemOperand; +using vixl::aarch32::PrintDisassembler; +using vixl::aarch32::pc; + +static const vixl::aarch32::Register tr(TR); + +class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler { + class CustomDisassemblerStream FINAL : public DisassemblerStream { + public: + CustomDisassemblerStream(std::ostream& os, + const CustomDisassembler* disasm, + const DisassemblerOptions* options) + : DisassemblerStream(os), disasm_(disasm), options_(options) {} + + DisassemblerStream& operator<<(const PrintLabel& label) OVERRIDE { + const LocationType type = label.GetLocationType(); + + switch (type) { + case kLoadByteLocation: + case kLoadHalfWordLocation: + case kLoadWordLocation: + case kLoadDoubleWordLocation: + case kLoadSignedByteLocation: + case kLoadSignedHalfWordLocation: + case kLoadSinglePrecisionLocation: + case kLoadDoublePrecisionLocation: + case kVld1Location: + case kVld2Location: + case kVld3Location: + case kVld4Location: { + const uintptr_t pc_delta = label.GetLabel()->GetPcOffset(); + const int32_t offset = label.GetLabel()->GetLocation(); + + os() << "[pc, #" << offset - pc_delta << "]"; + PrintLiteral(type, offset); + return *this; + } + default: + return DisassemblerStream::operator<<(label); + } } - } -} - -static const char* kConditionCodeNames[] = { - "eq", // 0000 - equal - "ne", // 0001 - not-equal - "cs", // 0010 - carry-set, greater than, equal or unordered - "cc", // 0011 - carry-clear, less than - "mi", // 0100 - minus, negative - "pl", // 0101 - plus, positive or zero - "vs", // 0110 - overflow - "vc", // 0111 - no overflow - "hi", // 1000 - unsigned higher - "ls", // 1001 - unsigned lower or same - "ge", // 1010 - signed greater than or equal - "lt", // 1011 - signed less than - "gt", // 1100 - signed greater than - "le", // 1101 - signed less than or equal - "", // 1110 - always - "nv", // 1111 - never (mostly obsolete, but might be a clue that we're mistranslating) -}; - -void DisassemblerArm::DumpCond(std::ostream& os, uint32_t cond) { - if (cond < 15) { - os << kConditionCodeNames[cond]; - } else { - os << "Unexpected condition: " << cond; - } -} - -void DisassemblerArm::DumpMemoryDomain(std::ostream& os, uint32_t domain) { - switch (domain) { - case 15U /* 0b1111 */: os << "sy"; break; - case 14U /* 0b1110 */: os << "st"; break; - case 11U /* 0b1011 */: os << "ish"; break; - case 10U /* 0b1010 */: os << "ishst"; break; - case 7U /* 0b0111 */: os << "nsh"; break; - case 6U /* 0b0110 */: os << "nshst"; break; - case 3U /* 0b0011 */: os << "osh"; break; - case 2U /* 0b0010 */: os << "oshst"; break; - } -} - -void DisassemblerArm::DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32) { - os << StringPrintf("%+d (", imm32) << FormatInstructionPointer(instr_ptr + imm32) << ")"; -} - -static uint32_t ReadU16(const uint8_t* ptr) { - return ptr[0] | (ptr[1] << 8); -} - -static uint32_t ReadU32(const uint8_t* ptr) { - return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); -} - -static const char* kDataProcessingOperations[] = { - "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", - "tst", "teq", "cmp", "cmn", "orr", "mov", "bic", "mvn", -}; - -static const char* kThumbDataProcessingOperations[] = { - "and", "eor", "lsl", "lsr", "asr", "adc", "sbc", "ror", - "tst", "rsb", "cmp", "cmn", "orr", "mul", "bic", "mvn", -}; - -static const char* const kThumb2ShiftOperations[] = { - "lsl", "lsr", "asr", "ror" -}; - -static const char* kThumbReverseOperations[] = { - "rev", "rev16", "rbit", "revsh" -}; - -struct ArmRegister { - explicit ArmRegister(uint32_t r_in) : r(r_in) { CHECK_LE(r_in, 15U); } - ArmRegister(uint32_t instruction, uint32_t at_bit) : r((instruction >> at_bit) & 0xf) { - CHECK_LE(r, 15U); - } - uint32_t r; -}; -std::ostream& operator<<(std::ostream& os, const ArmRegister& r) { - if (r.r == 13) { - os << "sp"; - } else if (r.r == 14) { - os << "lr"; - } else if (r.r == 15) { - os << "pc"; - } else { - os << "r" << r.r; - } - return os; -} - -struct ThumbRegister : ArmRegister { - ThumbRegister(uint16_t instruction, uint16_t at_bit) : ArmRegister((instruction >> at_bit) & 0x7) {} -}; -struct RmLslImm2 { - explicit RmLslImm2(uint32_t instr) : imm2((instr >> 4) & 0x3), rm(instr & 0xf) {} - uint32_t imm2; - ArmRegister rm; -}; -std::ostream& operator<<(std::ostream& os, const RmLslImm2& r) { - os << r.rm; - if (r.imm2 != 0) { - os << ", lsl #" << r.imm2; - } - return os; -} - -struct ShiftedImmediate { - explicit ShiftedImmediate(uint32_t instruction) { - uint32_t rotate = ((instruction >> 8) & 0xf); - uint32_t imm = (instruction & 0xff); - value = (imm >> (2 * rotate)) | (imm << (32 - (2 * rotate))); - } - uint32_t value; -}; -std::ostream& operator<<(std::ostream& os, const ShiftedImmediate& rhs) { - os << "#" << rhs.value; - return os; -} - -struct RegisterList { - explicit RegisterList(uint32_t instruction) : register_list(instruction & 0xffff) {} - uint32_t register_list; -}; -std::ostream& operator<<(std::ostream& os, const RegisterList& rhs) { - if (rhs.register_list == 0) { - os << "<no register list?>"; - return os; - } - os << "{"; - bool first = true; - for (size_t i = 0; i < 16; i++) { - if ((rhs.register_list & (1 << i)) != 0) { - if (first) { - first = false; + DisassemblerStream& operator<<(vixl::aarch32::Register reg) OVERRIDE { + if (reg.Is(tr)) { + os() << "tr"; + return *this; } else { - os << ", "; + return DisassemblerStream::operator<<(reg); } - os << ArmRegister(i); } - } - os << "}"; - return os; -} -struct FpRegister { - FpRegister(uint32_t instr, uint16_t at_bit, uint16_t extra_at_bit) { - size = (instr >> 8) & 1; - uint32_t Vn = (instr >> at_bit) & 0xF; - uint32_t N = (instr >> extra_at_bit) & 1; - r = (size != 0 ? ((N << 4) | Vn) : ((Vn << 1) | N)); - } - FpRegister(uint32_t instr, uint16_t at_bit, uint16_t extra_at_bit, uint32_t forced_size) { - size = forced_size; - uint32_t Vn = (instr >> at_bit) & 0xF; - uint32_t N = (instr >> extra_at_bit) & 1; - r = (size != 0 ? ((N << 4) | Vn) : ((Vn << 1) | N)); - } - FpRegister(const FpRegister& other, uint32_t offset) - : size(other.size), r(other.r + offset) {} - - uint32_t size; // 0 = f32, 1 = f64 - uint32_t r; -}; -std::ostream& operator<<(std::ostream& os, const FpRegister& rhs) { - return os << ((rhs.size != 0) ? "d" : "s") << rhs.r; -} + DisassemblerStream& operator<<(const MemOperand& operand) OVERRIDE { + // VIXL must use a PrintLabel object whenever the base register is PC; + // the following check verifies this invariant, and guards against bugs. + DCHECK(!operand.GetBaseRegister().Is(pc)); + DisassemblerStream::operator<<(operand); -struct FpRegisterRange { - explicit FpRegisterRange(uint32_t instr) - : first(instr, 12, 22), imm8(instr & 0xFF) {} - FpRegister first; - uint32_t imm8; -}; -std::ostream& operator<<(std::ostream& os, const FpRegisterRange& rhs) { - os << "{" << rhs.first; - int count = (rhs.first.size != 0 ? ((rhs.imm8 + 1u) >> 1) : rhs.imm8); - if (count > 1) { - os << "-" << FpRegister(rhs.first, count - 1); - } - if (rhs.imm8 == 0) { - os << " (EMPTY)"; - } else if (rhs.first.size != 0 && (rhs.imm8 & 1) != 0) { - os << rhs.first << " (HALF)"; - } - os << "}"; - return os; -} - -void DisassemblerArm::DumpArm(std::ostream& os, const uint8_t* instr_ptr) { - uint32_t instruction = ReadU32(instr_ptr); - uint32_t cond = (instruction >> 28) & 0xf; - uint32_t op1 = (instruction >> 25) & 0x7; - std::string opcode; - std::string suffixes; - std::ostringstream args; - switch (op1) { - case 0: - case 1: // Data processing instructions. - { - if ((instruction & 0x0ff000f0) == 0x01200070) { // BKPT - opcode = "bkpt"; - uint32_t imm12 = (instruction >> 8) & 0xfff; - uint32_t imm4 = (instruction & 0xf); - args << '#' << ((imm12 << 4) | imm4); - break; - } - if ((instruction & 0x0fffffd0) == 0x012fff10) { // BX and BLX (register) - opcode = (((instruction >> 5) & 1) ? "blx" : "bx"); - args << ArmRegister(instruction & 0xf); - break; - } - bool i = (instruction & (1 << 25)) != 0; - bool s = (instruction & (1 << 20)) != 0; - uint32_t op = (instruction >> 21) & 0xf; - opcode = kDataProcessingOperations[op]; - bool implicit_s = ((op & ~3) == 8); // TST, TEQ, CMP, and CMN. - bool is_mov = op == 13U /* 0b1101 */ || op == 15U /* 0b1111 */; - if (is_mov) { - // Show only Rd and Rm. - if (s) { - suffixes += 's'; - } - args << ArmRegister(instruction, 12) << ", "; - if (i) { - args << ShiftedImmediate(instruction); - } else { - // TODO: Shifted register. - args << ArmRegister(instruction, 16) << ", " << ArmRegister(instruction, 0); - } - } else { - if (implicit_s) { - // Rd is unused (and not shown), and we don't show the 's' suffix either. - } else { - if (s) { - suffixes += 's'; - } - args << ArmRegister(instruction, 12) << ", "; - } - if (i) { - args << ArmRegister(instruction, 16) << ", " << ShiftedImmediate(instruction); - } else { - // TODO: Shifted register. - args << ArmRegister(instruction, 16) << ", " << ArmRegister(instruction, 0); - } - } - } - break; - case 2: // Load/store word and unsigned byte. - { - bool p = (instruction & (1 << 24)) != 0; - bool b = (instruction & (1 << 22)) != 0; - bool w = (instruction & (1 << 21)) != 0; - bool l = (instruction & (1 << 20)) != 0; - opcode = StringPrintf("%s%s", (l ? "ldr" : "str"), (b ? "b" : "")); - args << ArmRegister(instruction, 12) << ", "; - ArmRegister rn(instruction, 16); - if (rn.r == 0xf) { - UNIMPLEMENTED(FATAL) << "literals"; - } else { - bool wback = !p || w; - uint32_t offset = (instruction & 0xfff); - if (p && !wback) { - args << "[" << rn << ", #" << offset << "]"; - } else if (p && wback) { - args << "[" << rn << ", #" << offset << "]!"; - } else if (!p && wback) { - args << "[" << rn << "], #" << offset; - } else { - LOG(FATAL) << p << " " << w; - } - if (rn.r == 9) { - args << " ; "; - Thread::DumpThreadOffset<4>(args, offset); - } - } + if (operand.GetBaseRegister().Is(tr) && operand.IsImmediate()) { + os() << " ; "; + options_->thread_offset_name_function_(os(), operand.GetOffsetImmediate()); } - break; - case 4: // Load/store multiple. - { - bool p = (instruction & (1 << 24)) != 0; - bool u = (instruction & (1 << 23)) != 0; - bool w = (instruction & (1 << 21)) != 0; - bool l = (instruction & (1 << 20)) != 0; - opcode = StringPrintf("%s%c%c", (l ? "ldm" : "stm"), (u ? 'i' : 'd'), (p ? 'b' : 'a')); - args << ArmRegister(instruction, 16) << (w ? "!" : "") << ", " << RegisterList(instruction); - } - break; - case 5: // Branch/branch with link. - { - bool bl = (instruction & (1 << 24)) != 0; - opcode = (bl ? "bl" : "b"); - int32_t imm26 = (instruction & 0xffffff) << 2; - int32_t imm32 = (imm26 << 6) >> 6; // Sign extend. - DumpBranchTarget(args, instr_ptr + 8, imm32); - } - break; - default: - opcode = "???"; - break; + + return *this; } - opcode += kConditionCodeNames[cond]; - opcode += suffixes; - // TODO: a more complete ARM disassembler could generate wider opcodes. - os << FormatInstructionPointer(instr_ptr) - << StringPrintf(": %08x\t%-7s ", instruction, opcode.c_str()) - << args.str() << '\n'; -} -int32_t ThumbExpand(int32_t imm12) { - if ((imm12 & 0xC00) == 0) { - switch ((imm12 >> 8) & 3) { - case 0: - return imm12 & 0xFF; - case 1: - return ((imm12 & 0xFF) << 16) | (imm12 & 0xFF); - case 2: - return ((imm12 & 0xFF) << 24) | ((imm12 & 0xFF) << 8); - default: // 3 - return ((imm12 & 0xFF) << 24) | ((imm12 & 0xFF) << 16) | ((imm12 & 0xFF) << 8) | - (imm12 & 0xFF); + DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) OVERRIDE { + // VIXL must use a PrintLabel object whenever the base register is PC; + // the following check verifies this invariant, and guards against bugs. + DCHECK(!operand.GetBaseRegister().Is(pc)); + return DisassemblerStream::operator<<(operand); } - } else { - uint32_t val = 0x80 | (imm12 & 0x7F); - int32_t rotate = (imm12 >> 7) & 0x1F; - return (val >> rotate) | (val << (32 - rotate)); - } -} -uint32_t VFPExpand32(uint32_t imm8) { - CHECK_EQ(imm8 & 0xffu, imm8); - uint32_t bit_a = (imm8 >> 7) & 1; - uint32_t bit_b = (imm8 >> 6) & 1; - uint32_t slice = imm8 & 0x3f; - return (bit_a << 31) | ((1 << 30) - (bit_b << 25)) | (slice << 19); -} + private: + void PrintLiteral(LocationType type, int32_t offset); -static uint64_t VFPExpand64(uint32_t imm8) { - CHECK_EQ(imm8 & 0xffu, imm8); - uint64_t bit_a = (imm8 >> 7) & 1; - uint64_t bit_b = (imm8 >> 6) & 1; - uint64_t slice = imm8 & 0x3f; - return (bit_a << 63) | ((UINT64_C(1) << 62) - (bit_b << 54)) | (slice << 48); -} + const CustomDisassembler* disasm_; + const DisassemblerOptions* options_; + }; + + public: + CustomDisassembler(std::ostream& os, const DisassemblerOptions* options) + : PrintDisassembler(&disassembler_stream_), disassembler_stream_(os, this, options) {} -enum T2LitType { - kT2LitInvalid, - kT2LitUByte, - kT2LitSByte, - kT2LitUHalf, - kT2LitSHalf, - kT2LitUWord, - kT2LitSWord, - kT2LitHexWord, - kT2LitULong, - kT2LitSLong, - kT2LitHexLong, + void PrintCodeAddress(uint32_t prog_ctr) OVERRIDE { + os() << "0x" << std::hex << std::setw(8) << std::setfill('0') << prog_ctr << ": "; + } + + private: + CustomDisassemblerStream disassembler_stream_; }; -std::ostream& operator<<(std::ostream& os, T2LitType type) { - return os << static_cast<int>(type); -} -void DumpThumb2Literal(std::ostream& args, - const uint8_t* instr_ptr, - const uintptr_t lo_adr, - const uintptr_t hi_adr, - uint32_t U, - uint32_t imm32, - T2LitType type) { - // Literal offsets (imm32) are not required to be aligned so we may need unaligned access. +void DisassemblerArm::CustomDisassembler::CustomDisassemblerStream::PrintLiteral(LocationType type, + int32_t offset) { + // Literal offsets are not required to be aligned, so we may need unaligned access. typedef const int16_t unaligned_int16_t __attribute__ ((aligned (1))); typedef const uint16_t unaligned_uint16_t __attribute__ ((aligned (1))); typedef const int32_t unaligned_int32_t __attribute__ ((aligned (1))); - typedef const uint32_t unaligned_uint32_t __attribute__ ((aligned (1))); typedef const int64_t unaligned_int64_t __attribute__ ((aligned (1))); - typedef const uint64_t unaligned_uint64_t __attribute__ ((aligned (1))); + typedef const float unaligned_float __attribute__ ((aligned (1))); + typedef const double unaligned_double __attribute__ ((aligned (1))); - // Get address of literal. Bail if not within expected buffer range to - // avoid trying to fetch invalid literals (we can encounter this when - // interpreting raw data as instructions). - uintptr_t pc = RoundDown(reinterpret_cast<intptr_t>(instr_ptr) + 4, 4); - uintptr_t lit_adr = U ? pc + imm32 : pc - imm32; - if (lit_adr < lo_adr || lit_adr >= hi_adr) { - args << " ; (?)"; - return; - } + // Zeros are used for the LocationType values this function does not care about. + const size_t literal_size[kVst4Location + 1] = { + 0, 0, 0, 0, sizeof(uint8_t), sizeof(unaligned_uint16_t), sizeof(unaligned_int32_t), + sizeof(unaligned_int64_t), sizeof(int8_t), sizeof(unaligned_int16_t), + sizeof(unaligned_float), sizeof(unaligned_double)}; + const uintptr_t begin = reinterpret_cast<uintptr_t>(options_->base_address_); + const uintptr_t end = reinterpret_cast<uintptr_t>(options_->end_address_); + uintptr_t literal_addr = RoundDown(disasm_->GetCodeAddress(), vixl::aarch32::kRegSizeInBytes) + offset; - args << " ; "; - switch (type) { - case kT2LitUByte: - args << *reinterpret_cast<const uint8_t*>(lit_adr); - break; - case kT2LitSByte: - args << *reinterpret_cast<const int8_t*>(lit_adr); - break; - case kT2LitUHalf: - args << *reinterpret_cast<const unaligned_uint16_t*>(lit_adr); - break; - case kT2LitSHalf: - args << *reinterpret_cast<const unaligned_int16_t*>(lit_adr); - break; - case kT2LitUWord: - args << *reinterpret_cast<const unaligned_uint32_t*>(lit_adr); - break; - case kT2LitSWord: - args << *reinterpret_cast<const unaligned_int32_t*>(lit_adr); - break; - case kT2LitHexWord: - args << StringPrintf("0x%08x", *reinterpret_cast<const unaligned_uint32_t*>(lit_adr)); - break; - case kT2LitULong: - args << *reinterpret_cast<const unaligned_uint64_t*>(lit_adr); - break; - case kT2LitSLong: - args << *reinterpret_cast<const unaligned_int64_t*>(lit_adr); - break; - case kT2LitHexLong: - args << StringPrintf("0x%" PRIx64, *reinterpret_cast<unaligned_int64_t*>(lit_adr)); - break; - default: - LOG(FATAL) << "Invalid type: " << type; - break; + if (!options_->absolute_addresses_) { + literal_addr += begin; } -} - -size_t DisassemblerArm::DumpThumb32(std::ostream& os, const uint8_t* instr_ptr) { - uint32_t instr = (ReadU16(instr_ptr) << 16) | ReadU16(instr_ptr + 2); - // |111|1 1|1000000|0000|1111110000000000| - // |5 3|2 1|0987654|3 0|5 0 5 0| - // |---|---|-------|----|----------------| - // |332|2 2|2222222|1111|1111110000000000| - // |1 9|8 7|6543210|9 6|5 0 5 0| - // |---|---|-------|----|----------------| - // |111|op1| op2 | | | - uint32_t op1 = (instr >> 27) & 3; - if (op1 == 0) { - return DumpThumb16(os, instr_ptr); - } - - // Set valid address range of backing buffer. - const uintptr_t lo_adr = reinterpret_cast<intptr_t>(GetDisassemblerOptions()->base_address_); - const uintptr_t hi_adr = reinterpret_cast<intptr_t>(GetDisassemblerOptions()->end_address_); - - uint32_t op2 = (instr >> 20) & 0x7F; - std::ostringstream opcode; - std::ostringstream args; - switch (op1) { - case 0: - break; - case 1: - if ((op2 & 0x64) == 0) { // 00x x0xx - // |111|11|10|00|0|00|0000|1111110000000000| - // |5 3|21|09|87|6|54|3 0|5 0 5 0| - // |---|--|--|--|-|--|----|----------------| - // |332|22|22|22|2|22|1111|1111110000000000| - // |1 9|87|65|43|2|10|9 6|5 0 5 0| - // |---|--|--|--|-|--|----|----------------| - // |111|01|00|op|0|WL| Rn | | - // |111|01| op2 | | | - // STM - 111 01 00-01-0-W0 nnnn rrrrrrrrrrrrrrrr - // LDM - 111 01 00-01-0-W1 nnnn rrrrrrrrrrrrrrrr - // PUSH- 111 01 00-01-0-10 1101 0M0rrrrrrrrrrrrr - // POP - 111 01 00-01-0-11 1101 PM0rrrrrrrrrrrrr - uint32_t op = (instr >> 23) & 3; - uint32_t W = (instr >> 21) & 1; - uint32_t L = (instr >> 20) & 1; - ArmRegister Rn(instr, 16); - if (op == 1 || op == 2) { - if (op == 1) { - if (L == 0) { - opcode << "stm"; - args << Rn << (W == 0 ? "" : "!") << ", "; - } else { - if (Rn.r != 13) { - opcode << "ldm"; - args << Rn << (W == 0 ? "" : "!") << ", "; - } else { - opcode << "pop"; - } - } - } else { - if (L == 0) { - if (Rn.r != 13) { - opcode << "stmdb"; - args << Rn << (W == 0 ? "" : "!") << ", "; - } else { - opcode << "push"; - } - } else { - opcode << "ldmdb"; - args << Rn << (W == 0 ? "" : "!") << ", "; - } - } - args << RegisterList(instr); - } - } else if ((op2 & 0x64) == 4) { // 00x x1xx - uint32_t op3 = (instr >> 23) & 3; - uint32_t op4 = (instr >> 20) & 3; - // uint32_t op5 = (instr >> 4) & 0xF; - ArmRegister Rn(instr, 16); - ArmRegister Rt(instr, 12); - ArmRegister Rd(instr, 8); - uint32_t imm8 = instr & 0xFF; - if ((op3 & 2) == 2) { // 1x - int W = (instr >> 21) & 1; - int U = (instr >> 23) & 1; - int P = (instr >> 24) & 1; - - if ((op4 & 1) == 1) { - opcode << "ldrd"; - } else { - opcode << "strd"; - } - args << Rt << "," << Rd << ", [" << Rn; - const char *sign = U ? "+" : "-"; - if (P == 0 && W == 1) { - args << "], #" << sign << (imm8 << 2); - } else { - args << ", #" << sign << (imm8 << 2) << "]"; - if (W == 1) { - args << "!"; - } - } - } else { // 0x - switch (op4) { - case 0: - if (op3 == 0) { // op3 is 00, op4 is 00 - opcode << "strex"; - args << Rd << ", " << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]"; - if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || - Rd.r == Rn.r || Rd.r == Rt.r) { - args << " (UNPREDICTABLE)"; - } - } else { // op3 is 01, op4 is 00 - // this is one of strexb, strexh or strexd - int op5 = (instr >> 4) & 0xf; - switch (op5) { - case 4: - case 5: - opcode << ((op5 == 4) ? "strexb" : "strexh"); - Rd = ArmRegister(instr, 0); - args << Rd << ", " << Rt << ", [" << Rn << "]"; - if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || - Rd.r == Rn.r || Rd.r == Rt.r || (instr & 0xf00) != 0xf00) { - args << " (UNPREDICTABLE)"; - } - break; - case 7: - opcode << "strexd"; - ArmRegister Rt2 = Rd; - Rd = ArmRegister(instr, 0); - args << Rd << ", " << Rt << ", " << Rt2 << ", [" << Rn << "]"; - if (Rd.r == 13 || Rd.r == 15 || Rt.r == 13 || Rt.r == 15 || - Rt2.r == 13 || Rt2.r == 15 || Rn.r == 15 || - Rd.r == Rn.r || Rd.r == Rt.r || Rd.r == Rt2.r) { - args << " (UNPREDICTABLE)"; - } - break; - } - } - break; - case 1: - if (op3 == 0) { // op3 is 00, op4 is 01 - opcode << "ldrex"; - args << Rt << ", [" << Rn << ", #" << (imm8 << 2) << "]"; - if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf00) != 0xf00) { - args << " (UNPREDICTABLE)"; - } - } else { // op3 is 01, op4 is 01 - // this is one of strexb, strexh or strexd - int op5 = (instr >> 4) & 0xf; - switch (op5) { - case 0: - opcode << "tbb"; - break; - case 1: - opcode << "tbh"; - break; - case 4: - case 5: - opcode << ((op5 == 4) ? "ldrexb" : "ldrexh"); - args << Rt << ", [" << Rn << "]"; - if (Rt.r == 13 || Rt.r == 15 || Rn.r == 15 || (instr & 0xf0f) != 0xf0f) { - args << " (UNPREDICTABLE)"; - } - break; - case 7: - opcode << "ldrexd"; - args << Rt << ", " << Rd /* Rt2 */ << ", [" << Rn << "]"; - if (Rt.r == 13 || Rt.r == 15 || Rd.r == 13 /* Rt2 */ || Rd.r == 15 /* Rt2 */ || - Rn.r == 15 || (instr & 0x00f) != 0x00f) { - args << " (UNPREDICTABLE)"; - } - break; - } - } - break; - case 2: // op3 is 0x, op4 is 10 - case 3: // op3 is 0x, op4 is 11 - if (op4 == 2) { - opcode << "strd"; - } else { - opcode << "ldrd"; - } - int W = (instr >> 21) & 1; - int U = (instr >> 23) & 1; - int P = (instr >> 24) & 1; - args << Rt << "," << Rd << ", [" << Rn; - const char *sign = U ? "+" : "-"; - if (P == 0 && W == 1) { - args << "], #" << sign << imm8; - } else { - args << ", #" << sign << imm8 << "]"; - if (W == 1) { - args << "!"; - } - } - break; - } - } - - } else if ((op2 & 0x60) == 0x20) { // 01x xxxx - // Data-processing (shifted register) - // |111|1110|0000|0|0000|1111|1100|00|00|0000| - // |5 3|2109|8765|4|3 0|5 |10 8|7 |5 |3 0| - // |---|----|----|-|----|----|----|--|--|----| - // |332|2222|2222|2|1111|1111|1100|00|00|0000| - // |1 9|8765|4321|0|9 6|5 |10 8|7 |5 |3 0| - // |---|----|----|-|----|----|----|--|--|----| - // |111|0101| op3|S| Rn |imm3| Rd |i2|ty| Rm | - uint32_t op3 = (instr >> 21) & 0xF; - uint32_t S = (instr >> 20) & 1; - uint32_t imm3 = ((instr >> 12) & 0x7); - uint32_t imm2 = ((instr >> 6) & 0x3); - uint32_t imm5 = ((imm3 << 2) | imm2); - uint32_t shift_type = ((instr >> 4) & 0x3); - ArmRegister Rd(instr, 8); - ArmRegister Rn(instr, 16); - ArmRegister Rm(instr, 0); - switch (op3) { - case 0x0: - if (Rd.r != 0xF) { - opcode << "and"; - } else { - if (S != 1U) { - opcode << "UNKNOWN TST-" << S; - break; - } - opcode << "tst"; - S = 0; // don't print 's' - } - break; - case 0x1: opcode << "bic"; break; - case 0x2: - if (Rn.r != 0xF) { - opcode << "orr"; - } else { - // TODO: use canonical form if there is a shift (lsl, ...). - opcode << "mov"; - } - break; - case 0x3: - if (Rn.r != 0xF) { - opcode << "orn"; - } else { - opcode << "mvn"; - } - break; - case 0x4: - if (Rd.r != 0xF) { - opcode << "eor"; - } else { - if (S != 1U) { - opcode << "UNKNOWN TEQ-" << S; - break; - } - opcode << "teq"; - S = 0; // don't print 's' - } - break; - case 0x6: opcode << "pkh"; break; - case 0x8: - if (Rd.r != 0xF) { - opcode << "add"; - } else { - if (S != 1U) { - opcode << "UNKNOWN CMN-" << S; - break; - } - opcode << "cmn"; - S = 0; // don't print 's' - } - break; - case 0xA: opcode << "adc"; break; - case 0xB: opcode << "sbc"; break; - case 0xD: - if (Rd.r != 0xF) { - opcode << "sub"; - } else { - if (S != 1U) { - opcode << "UNKNOWN CMP-" << S; - break; - } - opcode << "cmp"; - S = 0; // don't print 's' - } - break; - case 0xE: opcode << "rsb"; break; - default: opcode << "UNKNOWN DPSR-" << op3; break; - } - - if (S == 1) { - opcode << "s"; - } - opcode << ".w"; - - if (Rd.r != 0xF) { - args << Rd << ", "; - } - if (Rn.r != 0xF) { - args << Rn << ", "; - } - args << Rm; - - // Shift operand. - bool noShift = (imm5 == 0 && shift_type != 0x3); - if (!noShift) { - args << ", "; - switch (shift_type) { - case 0x0: args << "lsl"; break; - case 0x1: args << "lsr"; break; - case 0x2: args << "asr"; break; - case 0x3: - if (imm5 == 0) { - args << "rrx"; - } else { - args << "ror #" << imm5; - } - break; - } - if (shift_type != 0x3 /* rrx */) { - args << StringPrintf(" #%d", (0 != imm5 || 0 == shift_type) ? imm5 : 32); - } - } + os() << " ; "; - } else if ((op2 & 0x40) == 0x40) { // 1xx xxxx - // Co-processor instructions - // |111|1|11|000000|0000|1111|1100|000|0 |0000| - // |5 3|2|10|987654|3 0|54 2|10 8|7 5|4 | 0| - // |---|-|--|------|----|----|----|---|---|----| - // |332|2|22|222222|1111|1111|1100|000|0 |0000| - // |1 9|8|76|543210|9 6|54 2|10 8|7 5|4 | 0| - // |---|-|--|------|----|----|----|---|---|----| - // |111| |11| op3 | Rn | |copr| |op4| | - uint32_t op3 = (instr >> 20) & 0x3F; - uint32_t coproc = (instr >> 8) & 0xF; - uint32_t op4 = (instr >> 4) & 0x1; - - if (coproc == 0xA || coproc == 0xB) { // 101x - if (op3 < 0x20 && (op3 & ~5) != 0) { // 0xxxxx and not 000x0x - // Extension register load/store instructions - // |1111|110|00000|0000|1111|110|0|00000000| - // |5 2|1 9|87654|3 0|5 2|1 9|8|7 0| - // |----|---|-----|----|----|---|-|--------| - // |3322|222|22222|1111|1111|110|0|00000000| - // |1 8|7 5|4 0|9 6|5 2|1 9|8|7 0| - // |----|---|-----|----|----|---|-|--------| - // |1110|110|PUDWL| Rn | Vd |101|S| imm8 | - uint32_t P = (instr >> 24) & 1; - uint32_t U = (instr >> 23) & 1; - uint32_t W = (instr >> 21) & 1; - if (P == U && W == 1) { - opcode << "UNDEFINED"; - } else { - uint32_t L = (instr >> 20) & 1; - uint32_t S = (instr >> 8) & 1; - ArmRegister Rn(instr, 16); - if (P == 1 && W == 0) { // VLDR - FpRegister d(instr, 12, 22); - uint32_t imm8 = instr & 0xFF; - opcode << (L == 1 ? "vldr" : "vstr"); - args << d << ", [" << Rn << ", #" << ((U == 1) ? "" : "-") - << (imm8 << 2) << "]"; - if (Rn.r == 15 && U == 1) { - DumpThumb2Literal(args, instr_ptr, lo_adr, hi_adr, U, imm8 << 2, kT2LitHexLong); - } - } else if (Rn.r == 13 && W == 1 && U == L) { // VPUSH/VPOP - opcode << (L == 1 ? "vpop" : "vpush"); - args << FpRegisterRange(instr); - } else { // VLDM - opcode << (L == 1 ? "vldm" : "vstm"); - args << Rn << ((W == 1) ? "!" : "") << ", " - << FpRegisterRange(instr); - } - opcode << (S == 1 ? ".f64" : ".f32"); - } - } else if ((op3 >> 1) == 2) { // 00010x - if ((instr & 0xD0) == 0x10) { - // 64bit transfers between ARM core and extension registers. - uint32_t L = (instr >> 20) & 1; - uint32_t S = (instr >> 8) & 1; - ArmRegister Rt2(instr, 16); - ArmRegister Rt(instr, 12); - FpRegister m(instr, 0, 5); - opcode << "vmov" << (S ? ".f64" : ".f32"); - if (L == 1) { - args << Rt << ", " << Rt2 << ", "; - } - if (S) { - args << m; - } else { - args << m << ", " << FpRegister(m, 1); - } - if (L == 0) { - args << ", " << Rt << ", " << Rt2; - } - if (Rt.r == 15 || Rt.r == 13 || Rt2.r == 15 || Rt2.r == 13 || - (S == 0 && m.r == 31) || (L == 1 && Rt.r == Rt2.r)) { - args << " (UNPREDICTABLE)"; - } - } - } else if ((op3 >> 4) == 2 && op4 == 0) { // 10xxxx, op = 0 - // fp data processing - // VMLA, VMLS, VMUL, VNMUL, VADD, VSUB, VDIV, VMOV, ... - // |1111|1100|0|0|00|0000|1111|110|0|0|0|0|0|0000| - // |5 2|1 8|7|6|54|3 0|5 2|1 9|8|7|6|5|4|3 0| - // |----|----|-|-|--|----|----|---|-|-|-|-|-|----| - // |3322|2222|2|2|22|1111|1111|110|0|0|0|0|0|0000| - // |1 8|7 4|3|2|10|9 6|5 2|1 9|8|7|6|5|4|3 0| - // |----|----|-|-|--|----|----|---|-|-|-|-|-|----| - // |1110|1110| op3 | Vn | Vd |101|S|N|Q|M|0| Vm | - // |1110|1110|0|D|00| Vn | Vd |101|S|N|0|M|0| Vm | VMLA - // |1110|1110|0|D|00| Vn | Vd |101|S|N|1|M|0| Vm | VMLS - // |1110|1110|0|D|10| Vn | Vd |101|S|N|0|M|0| Vm | VMUL - // |1110|1110|0|D|10| Vn | Vd |101|S|N|1|M|0| Vm | VNMUL - // |1110|1110|0|D|11| Vn | Vd |101|S|N|0|M|0| Vm | VADD - // |1110|1110|0|D|11| Vn | Vd |101|S|N|1|M|0| Vm | VSUB - // |1110|1110|1|D|00| Vn | Vd |101|S|N|0|M|0| Vm | VDIV - // |1110|1110|1|D|11| iH | Vd |101|S|0|0|0|0| iL | VMOV (imm) - // |1110|1110|1|D|11|op5 | Vd |101|S|.|1|M|0| Vm | ... (see below) - uint32_t S = (instr >> 8) & 1; - uint32_t Q = (instr >> 6) & 1; - FpRegister d(instr, 12, 22); - FpRegister n(instr, 16, 7); - FpRegister m(instr, 0, 5); - if ((op3 & 0xB) == 0) { // 100x00 - opcode << (Q == 0 ? "vmla" : "vmls") << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << n << ", " << m; - } else if ((op3 & 0xB) == 0x2) { // 100x10 - opcode << (Q == 0 ? "vmul" : "vnmul") << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << n << ", " << m; - } else if ((op3 & 0xB) == 0x3) { // 100x11 - opcode << (Q == 0 ? "vadd" : "vsub") << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << n << ", " << m; - } else if ((op3 & 0xB) == 0x8 && Q == 0) { // 101x00, Q == 0 - opcode << "vdiv" << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << n << ", " << m; - } else if ((op3 & 0xB) == 0xB && Q == 0) { // 101x11, Q == 0 - uint32_t imm8 = ((instr & 0xf0000u) >> 12) | (instr & 0xfu); - opcode << "vmov" << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << (S != 0 ? StringPrintf("0x%016" PRIx64, VFPExpand64(imm8)) - : StringPrintf("0x%08x", VFPExpand32(imm8))); - if ((instr & 0xa0) != 0) { - args << " (UNPREDICTABLE)"; - } - } else if ((op3 & 0xB) == 0xB && Q == 1) { // 101x11, Q == 1 - // VNEG, VSQRT, VCMP, VCMPE, VCVT (floating-point conversion) - // |1111|1100|0|0|00|0000|1111|110|0|0 |0|0|0|0000| - // |5 2|1 8|7|6|54|3 0|5 2|1 9|8|7 |6|5|4|3 0| - // |----|----|-|-|--|----|----|---|-|- |-|-|-|----| - // |3322|2222|2|2|22|1111|1111|110|0|0 |0|0|0|0000| - // |1 8|7 4|3|2|10|9 6|5 2|1 9|8|7 |6|5|4|3 0| - // |----|----|-|-|--|----|----|---|-|- |-|-|-|----| - // |1110|1110|1|D|11|0000| Vd |101|S|0 |1|M|0| Vm | VMOV (reg) - // |1110|1110|1|D|11|0000| Vd |101|S|1 |1|M|0| Vm | VABS - // |1110|1110|1|D|11|0001| Vd |101|S|0 |1|M|0| Vm | VNEG - // |1110|1110|1|D|11|0001| Vd |101|S|1 |1|M|0| Vm | VSQRT - // |1110|1110|1|D|11|0100| Vd |101|S|op|1|M|0| Vm | VCMP - // |1110|1110|1|D|11|0101| Vd |101|S|op|1|0|0|0000| VCMPE - // |1110|1110|1|D|11|op5 | Vd |101|S|op|1|M|0| Vm | VCVT - uint32_t op5 = (instr >> 16) & 0xF; - uint32_t op = (instr >> 7) & 1; - // Register types in VCVT instructions rely on the combination of op5 and S. - FpRegister Dd(instr, 12, 22, 1); - FpRegister Sd(instr, 12, 22, 0); - FpRegister Dm(instr, 0, 5, 1); - FpRegister Sm(instr, 0, 5, 0); - if (op5 == 0) { - opcode << (op == 0 ? "vmov" : "vabs") << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << m; - } else if (op5 == 1) { - opcode << (op != 0 ? "vsqrt" : "vneg") << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << m; - } else if (op5 == 4) { - opcode << "vcmp" << (S != 0 ? ".f64" : ".f32"); - args << d << ", " << m; - if (op != 0) { - args << " (quiet nan)"; - } - } else if (op5 == 5) { - opcode << "vcmpe" << (S != 0 ? ".f64" : ".f32"); - args << d << ", #0.0"; - if (op != 0) { - args << " (quiet nan)"; - } - if ((instr & 0x2f) != 0) { - args << " (UNPREDICTABLE)"; - } - } else if (op5 == 0xD) { - if (S == 1) { - // vcvt{r}.s32.f64 - opcode << "vcvt" << (op == 0 ? "r" : "") << ".s32.f64"; - args << Sd << ", " << Dm; - } else { - // vcvt{r}.s32.f32 - opcode << "vcvt" << (op == 0 ? "r" : "") << ".s32.f32"; - args << Sd << ", " << Sm; - } - } else if (op5 == 0xC) { - if (S == 1) { - // vcvt{r}.u32.f64 - opcode << "vcvt" << (op == 0 ? "r" : "") << ".u32.f64"; - args << Sd << ", " << Dm; - } else { - // vcvt{r}.u32.f32 - opcode << "vcvt" << (op == 0 ? "r" : "") << ".u32.f32"; - args << Sd << ", " << Sm; - } - } else if (op5 == 0x8) { - if (S == 1) { - // vcvt.f64.<Tm> - opcode << "vcvt.f64." << (op == 0 ? "u" : "s") << "32"; - args << Dd << ", " << Sm; - } else { - // vcvt.f32.<Tm> - opcode << "vcvt.f32." << (op == 0 ? "u" : "s") << "32"; - args << Sd << ", " << Sm; - } - } else if (op5 == 0x7) { - if (op == 1) { - if (S == 1) { - // vcvt.f64.f32 - opcode << "vcvt.f64.f32"; - args << Dd << ", " << Sm; - } else { - // vcvt.f32.f64 - opcode << "vcvt.f32.f64"; - args << Sd << ", " << Dm; - } - } - } else if ((op5 & 0xa) == 0xa) { - opcode << "vcvt"; - args << "[undecoded: floating <-> fixed]"; - } - } - } else if ((op3 >> 4) == 2 && op4 == 1) { // 10xxxx, op = 1 - if (coproc == 10 && (op3 & 0xE) == 0) { - // VMOV (between ARM core register and single-precision register) - // |1111|1100|000|0 |0000|1111|1100|0|00|0|0000| - // |5 |1 8|7 5|4 |3 0|5 2|1 8|7|65|4|3 0| - // |----|----|---|- |----|----|----|-|--|-|----| - // |3322|2222|222|2 |1111|1111|1100|0|00|0|0000| - // |1 8|7 4|3 1|0 |9 6|5 2|1 8|7|65|4|3 0| - // |----|----|---|- |----|----|----|-|--|-|----| - // |1110|1110|000|op| Vn | Rt |1010|N|00|1|0000| - uint32_t op = op3 & 1; - ArmRegister Rt(instr, 12); - FpRegister n(instr, 16, 7); - opcode << "vmov.f32"; - if (op) { - args << Rt << ", " << n; - } else { - args << n << ", " << Rt; - } - if (Rt.r == 13 || Rt.r == 15 || (instr & 0x6F) != 0) { - args << " (UNPREDICTABLE)"; - } - } else if (coproc == 10 && op3 == 0x2F) { - // VMRS - // |1111|11000000|0000|1111|1100|000|0|0000| - // |5 |1 4|3 0|5 2|1 8|7 5|4|3 0| - // |----|--------|----|----|----|---|-|----| - // |3322|22222222|1111|1111|1100|000|0|0000| - // |1 8|7 0|9 6|5 2|1 8|7 5|4|3 0| - // |----|--------|----|----|----|---|-|----| - // |1110|11101111|reg | Rt |1010|000|1|0000| - last 7 0s are (0) - uint32_t spec_reg = (instr >> 16) & 0xF; - ArmRegister Rt(instr, 12); - opcode << "vmrs"; - if (spec_reg == 1) { - if (Rt.r == 15) { - args << "APSR_nzcv, FPSCR"; - } else if (Rt.r == 13) { - args << Rt << ", FPSCR (UNPREDICTABLE)"; - } else { - args << Rt << ", FPSCR"; - } - } else { - args << "(PRIVILEGED)"; - } - } else if (coproc == 11 && (op3 & 0x9) != 8) { - // VMOV (ARM core register to scalar or vice versa; 8/16/32-bit) - } - } - } - } - break; - case 2: - if ((instr & 0x8000) == 0 && (op2 & 0x20) == 0) { - // Data-processing (modified immediate) - // |111|11|10|0000|0|0000|1|111|1100|00000000| - // |5 3|21|09|8765|4|3 0|5|4 2|10 8|7 5 0| - // |---|--|--|----|-|----|-|---|----|--------| - // |332|22|22|2222|2|1111|1|111|1100|00000000| - // |1 9|87|65|4321|0|9 6|5|4 2|10 8|7 5 0| - // |---|--|--|----|-|----|-|---|----|--------| - // |111|10|i0| op3|S| Rn |0|iii| Rd |iiiiiiii| - // 111 10 x0 xxxx x xxxx opxxx xxxx xxxxxxxx - uint32_t i = (instr >> 26) & 1; - uint32_t op3 = (instr >> 21) & 0xF; - uint32_t S = (instr >> 20) & 1; - ArmRegister Rn(instr, 16); - uint32_t imm3 = (instr >> 12) & 7; - ArmRegister Rd(instr, 8); - uint32_t imm8 = instr & 0xFF; - int32_t imm32 = (i << 11) | (imm3 << 8) | imm8; - if (Rn.r == 0xF && (op3 == 0x2 || op3 == 0x3)) { - if (op3 == 0x2) { - opcode << "mov"; - if (S == 1) { - opcode << "s"; - } - opcode << ".w"; - } else { - opcode << "mvn"; - if (S == 1) { - opcode << "s"; - } - } - args << Rd << ", #" << ThumbExpand(imm32); - } else if (Rd.r == 0xF && S == 1 && - (op3 == 0x0 || op3 == 0x4 || op3 == 0x8 || op3 == 0xD)) { - if (op3 == 0x0) { - opcode << "tst"; - } else if (op3 == 0x4) { - opcode << "teq"; - } else if (op3 == 0x8) { - opcode << "cmn.w"; - } else { - opcode << "cmp.w"; - } - args << Rn << ", #" << ThumbExpand(imm32); - } else { - switch (op3) { - case 0x0: opcode << "and"; break; - case 0x1: opcode << "bic"; break; - case 0x2: opcode << "orr"; break; - case 0x3: opcode << "orn"; break; - case 0x4: opcode << "eor"; break; - case 0x8: opcode << "add"; break; - case 0xA: opcode << "adc"; break; - case 0xB: opcode << "sbc"; break; - case 0xD: opcode << "sub"; break; - case 0xE: opcode << "rsb"; break; - default: opcode << "UNKNOWN DPMI-" << op3; break; - } - if (S == 1) { - opcode << "s"; - } - args << Rd << ", " << Rn << ", #" << ThumbExpand(imm32); - } - } else if ((instr & 0x8000) == 0 && (op2 & 0x20) != 0) { - // Data-processing (plain binary immediate) - // |111|11|10|00000|0000|1|111110000000000| - // |5 3|21|09|87654|3 0|5|4 0 5 0| - // |---|--|--|-----|----|-|---------------| - // |332|22|22|22222|1111|1|111110000000000| - // |1 9|87|65|43210|9 6|5|4 0 5 0| - // |---|--|--|-----|----|-|---------------| - // |111|10|x1| op3 | Rn |0|xxxxxxxxxxxxxxx| - uint32_t op3 = (instr >> 20) & 0x1F; - switch (op3) { - case 0x00: case 0x0A: { - // ADD/SUB.W Rd, Rn #imm12 - 111 10 i1 0101 0 nnnn 0 iii dddd iiiiiiii - ArmRegister Rd(instr, 8); - ArmRegister Rn(instr, 16); - uint32_t i = (instr >> 26) & 1; - uint32_t imm3 = (instr >> 12) & 0x7; - uint32_t imm8 = instr & 0xFF; - uint32_t imm12 = (i << 11) | (imm3 << 8) | imm8; - if (Rn.r != 0xF) { - opcode << (op3 == 0 ? "addw" : "subw"); - args << Rd << ", " << Rn << ", #" << imm12; - } else { - opcode << "adr"; - args << Rd << ", "; - DumpBranchTarget(args, instr_ptr + 4, (op3 == 0) ? imm12 : -imm12); - } - break; - } - case 0x04: case 0x0C: { - // MOVW/T Rd, #imm16 - 111 10 i0 0010 0 iiii 0 iii dddd iiiiiiii - ArmRegister Rd(instr, 8); - uint32_t i = (instr >> 26) & 1; - uint32_t imm3 = (instr >> 12) & 0x7; - uint32_t imm8 = instr & 0xFF; - uint32_t Rn = (instr >> 16) & 0xF; - uint32_t imm16 = (Rn << 12) | (i << 11) | (imm3 << 8) | imm8; - opcode << (op3 == 0x04 ? "movw" : "movt"); - args << Rd << ", #" << imm16; - break; - } - case 0x16: case 0x14: case 0x1C: { - // BFI Rd, Rn, #lsb, #width - 111 10 0 11 011 0 nnnn 0 iii dddd ii 0 iiiii - // SBFX Rd, Rn, #lsb, #width - 111 10 0 11 010 0 nnnn 0 iii dddd ii 0 iiiii - // UBFX Rd, Rn, #lsb, #width - 111 10 0 11 110 0 nnnn 0 iii dddd ii 0 iiiii - ArmRegister Rd(instr, 8); - ArmRegister Rn(instr, 16); - uint32_t msb = instr & 0x1F; - uint32_t imm2 = (instr >> 6) & 0x3; - uint32_t imm3 = (instr >> 12) & 0x7; - uint32_t lsb = (imm3 << 2) | imm2; - uint32_t width = msb - lsb + 1; - if (op3 == 0x16) { - if (Rn.r != 0xF) { - opcode << "bfi"; - args << Rd << ", " << Rn << ", #" << lsb << ", #" << width; - } else { - opcode << "bfc"; - args << Rd << ", #" << lsb << ", #" << width; - } - } else { - opcode << ((op3 & 0x8) != 0u ? "ubfx" : "sbfx"); - args << Rd << ", " << Rn << ", #" << lsb << ", #" << width; - if (Rd.r == 13 || Rd.r == 15 || Rn.r == 13 || Rn.r == 15 || - (instr & 0x04000020) != 0u) { - args << " (UNPREDICTABLE)"; - } - } - break; - } - default: - break; - } - } else { - // Branches and miscellaneous control - // |111|11|1000000|0000|1|111|1100|00000000| - // |5 3|21|0987654|3 0|5|4 2|10 8|7 5 0| - // |---|--|-------|----|-|---|----|--------| - // |332|22|2222222|1111|1|111|1100|00000000| - // |1 9|87|6543210|9 6|5|4 2|10 8|7 5 0| - // |---|--|-------|----|-|---|----|--------| - // |111|10| op2 | |1|op3|op4 | | - - uint32_t op3 = (instr >> 12) & 7; - // uint32_t op4 = (instr >> 8) & 0xF; - switch (op3) { - case 0: - if ((op2 & 0x38) != 0x38) { - // Conditional branch - // |111|11|1|0000|000000|1|1|1 |1|1 |10000000000| - // |5 3|21|0|9876|543 0|5|4|3 |2|1 |0 5 0| - // |---|--|-|----|------|-|-|--|-|--|-----------| - // |332|22|2|2222|221111|1|1|1 |1|1 |10000000000| - // |1 9|87|6|5432|109 6|5|4|3 |2|1 |0 5 0| - // |---|--|-|----|------|-|-|--|-|--|-----------| - // |111|10|S|cond| imm6 |1|0|J1|0|J2| imm11 | - uint32_t S = (instr >> 26) & 1; - uint32_t J2 = (instr >> 11) & 1; - uint32_t J1 = (instr >> 13) & 1; - uint32_t imm6 = (instr >> 16) & 0x3F; - uint32_t imm11 = instr & 0x7FF; - uint32_t cond = (instr >> 22) & 0xF; - int32_t imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); - imm32 = (imm32 << 11) >> 11; // sign extend 21bit immediate - opcode << "b"; - DumpCond(opcode, cond); - opcode << ".w"; - DumpBranchTarget(args, instr_ptr + 4, imm32); - } else if (op2 == 0x3B) { - // Miscellaneous control instructions - uint32_t op5 = (instr >> 4) & 0xF; - switch (op5) { - case 4: opcode << "dsb"; DumpMemoryDomain(args, instr & 0xF); break; - case 5: opcode << "dmb"; DumpMemoryDomain(args, instr & 0xF); break; - case 6: opcode << "isb"; DumpMemoryDomain(args, instr & 0xF); break; - } - } - break; - case 2: - if ((op2 & 0x38) == 0x38) { - if (op2 == 0x7F) { - opcode << "udf"; - } - break; - } - FALLTHROUGH_INTENDED; // Else deliberate fall-through to B. - case 1: case 3: { - // B - // |111|11|1|0000|000000|11|1 |1|1 |10000000000| - // |5 3|21|0|9876|543 0|54|3 |2|1 |0 5 0| - // |---|--|-|----|------|--|--|-|--|-----------| - // |332|22|2|2222|221111|11|1 |1|1 |10000000000| - // |1 9|87|6|5 2|10 6|54|3 |2|1 |0 5 0| - // |---|--|-|----|------|--|--|-|--|-----------| - // |111|10|S|cond| imm6 |10|J1|0|J2| imm11 | - // |111|10|S| imm10 |10|J1|1|J2| imm11 | - uint32_t S = (instr >> 26) & 1; - uint32_t cond = (instr >> 22) & 0xF; - uint32_t J2 = (instr >> 11) & 1; - uint32_t form = (instr >> 12) & 1; - uint32_t J1 = (instr >> 13) & 1; - uint32_t imm10 = (instr >> 16) & 0x3FF; - uint32_t imm6 = (instr >> 16) & 0x3F; - uint32_t imm11 = instr & 0x7FF; - opcode << "b"; - int32_t imm32; - if (form == 0) { - DumpCond(opcode, cond); - imm32 = (S << 20) | (J2 << 19) | (J1 << 18) | (imm6 << 12) | (imm11 << 1); - imm32 = (imm32 << 11) >> 11; // sign extend 21 bit immediate. - } else { - uint32_t I1 = (J1 ^ S) ^ 1; - uint32_t I2 = (J2 ^ S) ^ 1; - imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); - imm32 = (imm32 << 7) >> 7; // sign extend 25 bit immediate. - } - opcode << ".w"; - DumpBranchTarget(args, instr_ptr + 4, imm32); - break; - } - case 4: case 6: case 5: case 7: { - // BL, BLX (immediate) - // |111|11|1|0000000000|11|1 |1|1 |10000000000| - // |5 3|21|0|9876543 0|54|3 |2|1 |0 5 0| - // |---|--|-|----------|--|--|-|--|-----------| - // |332|22|2|2222221111|11|1 |1|1 |10000000000| - // |1 9|87|6|5 0 6|54|3 |2|1 |0 5 0| - // |---|--|-|----------|--|--|-|--|-----------| - // |111|10|S| imm10 |11|J1|L|J2| imm11 | - uint32_t S = (instr >> 26) & 1; - uint32_t J2 = (instr >> 11) & 1; - uint32_t L = (instr >> 12) & 1; - uint32_t J1 = (instr >> 13) & 1; - uint32_t imm10 = (instr >> 16) & 0x3FF; - uint32_t imm11 = instr & 0x7FF; - if (L == 0) { - opcode << "bx"; - } else { - opcode << "blx"; - } - uint32_t I1 = ~(J1 ^ S); - uint32_t I2 = ~(J2 ^ S); - int32_t imm32 = (S << 24) | (I1 << 23) | (I2 << 22) | (imm10 << 12) | (imm11 << 1); - imm32 = (imm32 << 8) >> 8; // sign extend 24 bit immediate. - DumpBranchTarget(args, instr_ptr + 4, imm32); - break; - } - } + // Bail out if not within expected buffer range to avoid trying to fetch invalid literals + // (we can encounter them when interpreting raw data as instructions). + if (literal_addr < begin || literal_addr > end - literal_size[type]) { + os() << "(?)"; + } else { + switch (type) { + case kLoadByteLocation: + os() << *reinterpret_cast<const uint8_t*>(literal_addr); + break; + case kLoadHalfWordLocation: + os() << *reinterpret_cast<unaligned_uint16_t*>(literal_addr); + break; + case kLoadWordLocation: { + const int32_t value = *reinterpret_cast<unaligned_int32_t*>(literal_addr); + os() << "0x" << std::hex << std::setw(8) << std::setfill('0') << value; + break; } - break; - case 3: - switch (op2) { - case 0x07: case 0x0F: case 0x17: case 0x1F: { // Explicitly UNDEFINED, A6.3. - opcode << "UNDEFINED"; - break; - } - case 0x06: case 0x0E: { // "Store single data item" undefined opcodes, A6.3.10. - opcode << "UNDEFINED [store]"; - break; - } - case 0x15: case 0x1D: { // "Load word" undefined opcodes, A6.3.7. - opcode << "UNDEFINED [load]"; - break; - } - case 0x10: case 0x12: case 0x14: case 0x16: case 0x18: case 0x1A: case 0x1C: case 0x1E: { - opcode << "UNKNOWN " << op2 << " [SIMD]"; - break; - } - case 0x01: case 0x00: case 0x09: case 0x08: // {LD,ST}RB{,T} - case 0x03: case 0x02: case 0x0B: case 0x0A: // {LD,ST}RH{,T} - case 0x05: case 0x04: case 0x0D: case 0x0C: // {LD,ST}R{,T} - case 0x11: case 0x19: // LDRSB{,T} (no signed store) - case 0x13: case 0x1B: { // LDRSH{,T} (no signed store) - // Load: - // (Store is the same except that l==0 and always s==0 below.) - // 00s.whl (sign, word, half, load) - // LDR{S}B imm12: 11111|00s1001| Rn | Rt |imm12 (0x09) - // LDR{S}B imm8: 11111|00s0001| Rn | Rt |1PUW|imm8 (0x01) - // LDR{S}BT imm8: 11111|00s0001| Rn | Rt |1110|imm8 (0x01) - // LDR{S}B lit: 11111|00sU001|1111| Rt |imm12 (0x01/0x09) - // LDR{S}B reg: 11111|00s0001| Rn | Rt |000000|imm2| Rm (0x01) - // LDR{S}H imm12: 11111|00s1011| Rn | Rt |imm12 (0x0B) - // LDR{S}H imm8: 11111|00s0011| Rn | Rt |1PUW|imm8 (0x03) - // LDR{S}HT imm8: 11111|00s0011| Rn | Rt |1110|imm8 (0x03) - // LDR{S}H lit: 11111|00sU011|1111| Rt |imm12 (0x03/0x0B) - // LDR{S}H reg: 11111|00s0011| Rn | Rt |000000|imm2| Rm (0x03) - // LDR imm12: 11111|0001101| Rn | Rt |imm12 (0x0D) - // LDR imm8: 11111|0000101| Rn | Rt |1PUW|imm8 (0x05) - // LDRT imm8: 11111|0000101| Rn | Rt |1110|imm8 (0x05) - // LDR lit: 11111|000U101|1111| Rt |imm12 (0x05/0x0D) - // LDR reg: 11111|0000101| Rn | Rt |000000|imm2| Rm (0x05) - // - // If Rt == 15, instead of load we have preload: - // PLD{W} imm12: 11111|00010W1| Rn |1111|imm12 (0x09/0x0B) - // PLD{W} imm8: 11111|00000W1| Rn |1111|1100|imm8 (0x01/0x03); -imm8 - // PLD lit: 11111|000U001|1111|1111|imm12 (0x01/0x09) - // PLD{W} reg: 11111|00000W1| Rn |1111|000000|imm2| Rm (0x01/0x03) - // PLI imm12: 11111|0011001| Rn |1111|imm12 (0x19) - // PLI imm8: 11111|0010001| Rn |1111|1100|imm8 (0x11); -imm8 - // PLI lit: 11111|001U001|1111|1111|imm12 (0x01/0x09) - // PLI reg: 11111|0010001| Rn |1111|000000|imm2| Rm (0x01/0x03) - - bool is_load = HasBitSet(instr, 20); - bool is_half = HasBitSet(instr, 21); // W for PLD/PLDW. - bool is_word = HasBitSet(instr, 22); - bool is_signed = HasBitSet(instr, 24); - ArmRegister Rn(instr, 16); - ArmRegister Rt(instr, 12); - uint32_t imm12 = instr & 0xFFF; - uint32_t U = (instr >> 23) & 1; // U for imm12 - uint32_t imm8 = instr & 0xFF; - uint32_t op4 = (instr >> 8) & 0xF; // 1PUW for imm8 - if (Rt.r == PC && is_load && !is_word) { - // PLD, PLDW, PLI - const char* pld_pli = (is_signed ? "pli" : "pld"); - const char* w = (is_half ? "w" : ""); - if (is_signed && !is_half) { - opcode << "UNDEFINED [PLI+W]"; - } else if (Rn.r == PC || U != 0u) { - opcode << pld_pli << w; - args << "[" << Rn << ", #" << (U != 0u ? "" : "-") << imm12 << "]"; - if (Rn.r == PC && is_half) { - args << " (UNPREDICTABLE)"; - } - } else if ((instr & 0xFC0) == 0) { - opcode << pld_pli << w; - RmLslImm2 Rm(instr); - args << "[" << Rn << ", " << Rm << "]"; - } else if (op4 == 0xC) { - opcode << pld_pli << w; - args << "[" << Rn << ", #-" << imm8 << "]"; - } else { - opcode << "UNDEFINED [~" << pld_pli << "]"; - } - break; - } - const char* ldr_str = is_load ? "ldr" : "str"; - const char* sign = is_signed ? "s" : ""; - const char* type = is_word ? "" : is_half ? "h" : "b"; - bool unpred = (Rt.r == SP && !is_word) || (Rt.r == PC && !is_load); - if (Rn.r == PC && !is_load) { - opcode << "UNDEFINED [STR-lit]"; - unpred = false; - } else if (Rn.r == PC || U != 0u) { - // Load/store with imm12 (load literal if Rn.r == PC; there's no store literal). - opcode << ldr_str << sign << type << ".w"; - args << Rt << ", [" << Rn << ", #" << (U != 0u ? "" : "-") << imm12 << "]"; - if (Rn.r == TR && is_load) { - args << " ; "; - Thread::DumpThreadOffset<4>(args, imm12); - } else if (Rn.r == PC) { - T2LitType lit_type[] = { - kT2LitUByte, kT2LitUHalf, kT2LitHexWord, kT2LitInvalid, - kT2LitUByte, kT2LitUHalf, kT2LitHexWord, kT2LitInvalid, - kT2LitSByte, kT2LitSHalf, kT2LitInvalid, kT2LitInvalid, - kT2LitSByte, kT2LitSHalf, kT2LitInvalid, kT2LitInvalid, - }; - DCHECK_LT(op2 >> 1, arraysize(lit_type)); - DCHECK_NE(lit_type[op2 >> 1], kT2LitInvalid); - DumpThumb2Literal(args, instr_ptr, lo_adr, hi_adr, U, imm12, lit_type[op2 >> 1]); - } - } else if ((instr & 0xFC0) == 0) { - opcode << ldr_str << sign << type << ".w"; - RmLslImm2 Rm(instr); - args << Rt << ", [" << Rn << ", " << Rm << "]"; - unpred = unpred || (Rm.rm.r == SP) || (Rm.rm.r == PC); - } else if (is_word && Rn.r == SP && imm8 == 4 && op4 == (is_load ? 0xB : 0xD)) { - opcode << (is_load ? "pop" : "push") << ".w"; - args << Rn; - unpred = unpred || (Rn.r == SP); - } else if ((op4 & 5) == 0) { - opcode << "UNDEFINED [P = W = 0 for " << ldr_str << "]"; - unpred = false; - } else { - uint32_t P = (instr >> 10) & 1; - U = (instr >> 9) & 1; - uint32_t W = (instr >> 8) & 1; - bool pre_index = (P != 0 && W == 1); - bool post_index = (P == 0 && W == 1); - const char* t = (P != 0 && U != 0 && W == 0) ? "t" : ""; // Unprivileged load/store? - opcode << ldr_str << sign << type << t << ".w"; - args << Rt << ", [" << Rn << (post_index ? "]" : "") << ", #" << (U != 0 ? "" : "-") - << imm8 << (post_index ? "" : "]") << (pre_index ? "!" : ""); - unpred = (W != 0 && Rn.r == Rt.r); - } - if (unpred) { - args << " (UNPREDICTABLE)"; - } - break; - } - case 0x29: { // 0101001 - // |111|11|1000000|0000|1111|1100|00|0 0|0000| - // |5 3|21|0 4|3 0|5 2|1 8|76|5 4|3 0| - // |---|--|-------|----|----|----|--|---|----| - // |332|22|2222222|1111|1111|1100|00|0 0|0000| - // |1 9|87|6 0|9 6|5 2|1 8|76|5 4|3 0| - // |---|--|-------|----|----|----|--|---|----| - // |111|11|0101001| Rm |1111| Rd |11|op3| Rm | - // REV - 111 11 0101001 mmmm 1111 dddd 1000 mmmm - // REV16 - 111 11 0101001 mmmm 1111 dddd 1001 mmmm - // RBIT - 111 11 0101001 mmmm 1111 dddd 1010 mmmm - // REVSH - 111 11 0101001 mmmm 1111 dddd 1011 mmmm - if ((instr & 0xf0c0) == 0xf080) { - uint32_t op3 = (instr >> 4) & 3; - opcode << kThumbReverseOperations[op3]; - ArmRegister Rm(instr, 0); - ArmRegister Rd(instr, 8); - args << Rd << ", " << Rm; - ArmRegister Rm2(instr, 16); - if (Rm.r != Rm2.r || Rm.r == 13 || Rm.r == 15 || Rd.r == 13 || Rd.r == 15) { - args << " (UNPREDICTABLE)"; - } - } // else unknown instruction - break; - } - case 0x2B: { // 0101011 - // CLZ - 111 11 0101011 mmmm 1111 dddd 1000 mmmm - if ((instr & 0xf0f0) == 0xf080) { - opcode << "clz"; - ArmRegister Rm(instr, 0); - ArmRegister Rd(instr, 8); - args << Rd << ", " << Rm; - ArmRegister Rm2(instr, 16); - if (Rm.r != Rm2.r || Rm.r == 13 || Rm.r == 15 || Rd.r == 13 || Rd.r == 15) { - args << " (UNPREDICTABLE)"; - } - } - break; - } - default: // more formats - if ((op2 >> 4) == 2) { // 010xxxx - // data processing (register) - if ((instr & 0x0080f0f0) == 0x0000f000) { - // LSL, LSR, ASR, ROR - uint32_t shift_op = (instr >> 21) & 3; - uint32_t S = (instr >> 20) & 1; - ArmRegister Rd(instr, 8); - ArmRegister Rn(instr, 16); - ArmRegister Rm(instr, 0); - opcode << kThumb2ShiftOperations[shift_op] << (S != 0 ? "s" : ""); - args << Rd << ", " << Rn << ", " << Rm; - } - } else if ((op2 >> 3) == 6) { // 0110xxx - // Multiply, multiply accumulate, and absolute difference - op1 = (instr >> 20) & 0x7; - op2 = (instr >> 4) & 0x1; - ArmRegister Ra(instr, 12); - ArmRegister Rn(instr, 16); - ArmRegister Rm(instr, 0); - ArmRegister Rd(instr, 8); - switch (op1) { - case 0: - if (op2 == 0) { - if (Ra.r == 0xf) { - opcode << "mul"; - args << Rd << ", " << Rn << ", " << Rm; - } else { - opcode << "mla"; - args << Rd << ", " << Rn << ", " << Rm << ", " << Ra; - } - } else { - opcode << "mls"; - args << Rd << ", " << Rn << ", " << Rm << ", " << Ra; - } - break; - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - break; // do these sometime - } - } else if ((op2 >> 3) == 7) { // 0111xxx - // Long multiply, long multiply accumulate, and divide - op1 = (instr >> 20) & 0x7; - op2 = (instr >> 4) & 0xf; - ArmRegister Rn(instr, 16); - ArmRegister Rm(instr, 0); - ArmRegister Rd(instr, 8); - ArmRegister RdHi(instr, 8); - ArmRegister RdLo(instr, 12); - switch (op1) { - case 0: - opcode << "smull"; - args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm; - break; - case 1: - opcode << "sdiv"; - args << Rd << ", " << Rn << ", " << Rm; - break; - case 2: - opcode << "umull"; - args << RdLo << ", " << RdHi << ", " << Rn << ", " << Rm; - break; - case 3: - opcode << "udiv"; - args << Rd << ", " << Rn << ", " << Rm; - break; - case 4: - case 5: - case 6: - break; // TODO: when we generate these... - } - } + case kLoadDoubleWordLocation: { + const int64_t value = *reinterpret_cast<unaligned_int64_t*>(literal_addr); + os() << "0x" << std::hex << std::setw(16) << std::setfill('0') << value; + break; } - break; - default: - break; - } - - // Apply any IT-block conditions to the opcode if necessary. - if (!it_conditions_.empty()) { - opcode << it_conditions_.back(); - it_conditions_.pop_back(); - } - if (opcode.str().size() == 0) { - opcode << "UNKNOWN " << op2; + case kLoadSignedByteLocation: + os() << *reinterpret_cast<const int8_t*>(literal_addr); + break; + case kLoadSignedHalfWordLocation: + os() << *reinterpret_cast<unaligned_int16_t*>(literal_addr); + break; + case kLoadSinglePrecisionLocation: + os() << *reinterpret_cast<unaligned_float*>(literal_addr); + break; + case kLoadDoublePrecisionLocation: + os() << *reinterpret_cast<unaligned_double*>(literal_addr); + break; + default: + UNIMPLEMENTED(FATAL) << "Unexpected literal type: " << type; + } } +} - os << FormatInstructionPointer(instr_ptr) - << StringPrintf(": %08x\t%-7s ", instr, opcode.str().c_str()) - << args.str() << '\n'; - return 4; -} // NOLINT(readability/fn_size) +DisassemblerArm::DisassemblerArm(DisassemblerOptions* options) + : Disassembler(options), disasm_(std::make_unique<CustomDisassembler>(output_, options)) {} -size_t DisassemblerArm::DumpThumb16(std::ostream& os, const uint8_t* instr_ptr) { - uint16_t instr = ReadU16(instr_ptr); - bool is_32bit = ((instr & 0xF000) == 0xF000) || ((instr & 0xF800) == 0xE800); - if (is_32bit) { - return DumpThumb32(os, instr_ptr); +size_t DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin) { + uintptr_t next; + // Remove the Thumb specifier bit; no effect if begin does not point to T32 code. + const uintptr_t instr_ptr = reinterpret_cast<uintptr_t>(begin) & ~1; + + const bool is_t32 = (reinterpret_cast<uintptr_t>(begin) & 1) != 0; + disasm_->SetCodeAddress(GetPc(instr_ptr)); + + if (is_t32) { + const uint16_t* const ip = reinterpret_cast<const uint16_t*>(instr_ptr); + const uint16_t* const end_address = reinterpret_cast<const uint16_t*>( + GetDisassemblerOptions()->end_address_); + next = reinterpret_cast<uintptr_t>(disasm_->DecodeT32At(ip, end_address)); } else { - std::ostringstream opcode; - std::ostringstream args; - uint16_t opcode1 = instr >> 10; - if (opcode1 < 0x10) { - // shift (immediate), add, subtract, move, and compare - uint16_t opcode2 = instr >> 9; - switch (opcode2) { - case 0x0: case 0x1: case 0x2: case 0x3: case 0x4: case 0x5: case 0x6: case 0x7: - case 0x8: case 0x9: case 0xA: case 0xB: { - // Logical shift left - 00 000xx iii mmm ddd - // Logical shift right - 00 001xx iii mmm ddd - // Arithmetic shift right - 00 010xx iii mmm ddd - uint16_t imm5 = (instr >> 6) & 0x1F; - ThumbRegister rm(instr, 3); - ThumbRegister Rd(instr, 0); - if (opcode2 <= 3) { - opcode << "lsls"; - } else if (opcode2 <= 7) { - opcode << "lsrs"; - } else { - opcode << "asrs"; - } - args << Rd << ", " << rm << ", #" << imm5; - break; - } - case 0xC: case 0xD: case 0xE: case 0xF: { - // Add register - 00 01100 mmm nnn ddd - // Sub register - 00 01101 mmm nnn ddd - // Add 3-bit immediate - 00 01110 iii nnn ddd - // Sub 3-bit immediate - 00 01111 iii nnn ddd - uint16_t imm3_or_Rm = (instr >> 6) & 7; - ThumbRegister Rn(instr, 3); - ThumbRegister Rd(instr, 0); - if ((opcode2 & 2) != 0 && imm3_or_Rm == 0) { - opcode << "mov"; - } else { - if ((opcode2 & 1) == 0) { - opcode << "adds"; - } else { - opcode << "subs"; - } - } - args << Rd << ", " << Rn; - if ((opcode2 & 2) == 0) { - ArmRegister Rm(imm3_or_Rm); - args << ", " << Rm; - } else if (imm3_or_Rm != 0) { - args << ", #" << imm3_or_Rm; - } - break; - } - case 0x10: case 0x11: case 0x12: case 0x13: - case 0x14: case 0x15: case 0x16: case 0x17: - case 0x18: case 0x19: case 0x1A: case 0x1B: - case 0x1C: case 0x1D: case 0x1E: case 0x1F: { - // MOVS Rd, #imm8 - 00100 ddd iiiiiiii - // CMP Rn, #imm8 - 00101 nnn iiiiiiii - // ADDS Rn, #imm8 - 00110 nnn iiiiiiii - // SUBS Rn, #imm8 - 00111 nnn iiiiiiii - ThumbRegister Rn(instr, 8); - uint16_t imm8 = instr & 0xFF; - switch (opcode2 >> 2) { - case 4: opcode << "movs"; break; - case 5: opcode << "cmp"; break; - case 6: opcode << "adds"; break; - case 7: opcode << "subs"; break; - } - args << Rn << ", #" << imm8; - break; - } - default: - break; - } - } else if (opcode1 == 0x10) { - // Data-processing - uint16_t opcode2 = (instr >> 6) & 0xF; - ThumbRegister rm(instr, 3); - ThumbRegister rdn(instr, 0); - opcode << kThumbDataProcessingOperations[opcode2]; - args << rdn << ", " << rm; - } else if (opcode1 == 0x11) { - // Special data instructions and branch and exchange - uint16_t opcode2 = (instr >> 6) & 0x0F; - switch (opcode2) { - case 0x0: case 0x1: case 0x2: case 0x3: { - // Add low registers - 010001 0000 xxxxxx - // Add high registers - 010001 0001/001x xxxxxx - uint16_t DN = (instr >> 7) & 1; - ArmRegister rm(instr, 3); - uint16_t Rdn = instr & 7; - ArmRegister DN_Rdn((DN << 3) | Rdn); - opcode << "add"; - args << DN_Rdn << ", " << rm; - break; - } - case 0x8: case 0x9: case 0xA: case 0xB: { - // Move low registers - 010001 1000 xxxxxx - // Move high registers - 010001 1001/101x xxxxxx - uint16_t DN = (instr >> 7) & 1; - ArmRegister rm(instr, 3); - uint16_t Rdn = instr & 7; - ArmRegister DN_Rdn((DN << 3) | Rdn); - opcode << "mov"; - args << DN_Rdn << ", " << rm; - break; - } - case 0x5: case 0x6: case 0x7: { - // Compare high registers - 010001 0101/011x xxxxxx - uint16_t N = (instr >> 7) & 1; - ArmRegister rm(instr, 3); - uint16_t Rn = instr & 7; - ArmRegister N_Rn((N << 3) | Rn); - opcode << "cmp"; - args << N_Rn << ", " << rm; - break; - } - case 0xC: case 0xD: case 0xE: case 0xF: { - // Branch and exchange - 010001 110x xxxxxx - // Branch with link and exchange - 010001 111x xxxxxx - ArmRegister rm(instr, 3); - opcode << ((opcode2 & 0x2) == 0 ? "bx" : "blx"); - args << rm; - break; - } - default: - break; - } - } else if (opcode1 == 0x12 || opcode1 == 0x13) { // 01001x - const uintptr_t lo_adr = reinterpret_cast<intptr_t>(GetDisassemblerOptions()->base_address_); - const uintptr_t hi_adr = reinterpret_cast<intptr_t>(GetDisassemblerOptions()->end_address_); - ThumbRegister Rt(instr, 8); - uint16_t imm8 = instr & 0xFF; - opcode << "ldr"; - args << Rt << ", [pc, #" << (imm8 << 2) << "]"; - DumpThumb2Literal(args, instr_ptr, lo_adr, hi_adr, /*U*/ 1u, imm8 << 2, kT2LitHexWord); - } else if ((opcode1 >= 0x14 && opcode1 <= 0x17) || // 0101xx - (opcode1 >= 0x18 && opcode1 <= 0x1f) || // 011xxx - (opcode1 >= 0x20 && opcode1 <= 0x27)) { // 100xxx - // Load/store single data item - uint16_t opA = (instr >> 12) & 0xF; - if (opA == 0x5) { - uint16_t opB = (instr >> 9) & 0x7; - ThumbRegister Rm(instr, 6); - ThumbRegister Rn(instr, 3); - ThumbRegister Rt(instr, 0); - switch (opB) { - case 0: opcode << "str"; break; - case 1: opcode << "strh"; break; - case 2: opcode << "strb"; break; - case 3: opcode << "ldrsb"; break; - case 4: opcode << "ldr"; break; - case 5: opcode << "ldrh"; break; - case 6: opcode << "ldrb"; break; - case 7: opcode << "ldrsh"; break; - } - args << Rt << ", [" << Rn << ", " << Rm << "]"; - } else if (opA == 9) { - uint16_t opB = (instr >> 11) & 1; - ThumbRegister Rt(instr, 8); - uint16_t imm8 = instr & 0xFF; - opcode << (opB == 0 ? "str" : "ldr"); - args << Rt << ", [sp, #" << (imm8 << 2) << "]"; - } else { - uint16_t imm5 = (instr >> 6) & 0x1F; - uint16_t opB = (instr >> 11) & 1; - ThumbRegister Rn(instr, 3); - ThumbRegister Rt(instr, 0); - switch (opA) { - case 6: - imm5 <<= 2; - opcode << (opB == 0 ? "str" : "ldr"); - break; - case 7: - imm5 <<= 0; - opcode << (opB == 0 ? "strb" : "ldrb"); - break; - case 8: - imm5 <<= 1; - opcode << (opB == 0 ? "strh" : "ldrh"); - break; - } - args << Rt << ", [" << Rn << ", #" << imm5 << "]"; - } - } else if (opcode1 >= 0x34 && opcode1 <= 0x37) { // 1101xx - int8_t imm8 = instr & 0xFF; - uint32_t cond = (instr >> 8) & 0xF; - opcode << "b"; - DumpCond(opcode, cond); - DumpBranchTarget(args, instr_ptr + 4, (imm8 << 1)); - } else if ((instr & 0xF800) == 0xA800) { - // Generate SP-relative address - ThumbRegister rd(instr, 8); - int imm8 = instr & 0xFF; - opcode << "add"; - args << rd << ", sp, #" << (imm8 << 2); - } else if ((instr & 0xF000) == 0xB000) { - // Miscellaneous 16-bit instructions - uint16_t opcode2 = (instr >> 5) & 0x7F; - switch (opcode2) { - case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: case 0x06: case 0x07: { - // Add immediate to SP - 1011 00000 ii iiiii - // Subtract immediate from SP - 1011 00001 ii iiiii - int imm7 = instr & 0x7F; - opcode << ((opcode2 & 4) == 0 ? "add" : "sub"); - args << "sp, sp, #" << (imm7 << 2); - break; - } - case 0x08: case 0x09: case 0x0A: case 0x0B: // 0001xxx - case 0x0C: case 0x0D: case 0x0E: case 0x0F: - case 0x18: case 0x19: case 0x1A: case 0x1B: // 0011xxx - case 0x1C: case 0x1D: case 0x1E: case 0x1F: - case 0x48: case 0x49: case 0x4A: case 0x4B: // 1001xxx - case 0x4C: case 0x4D: case 0x4E: case 0x4F: - case 0x58: case 0x59: case 0x5A: case 0x5B: // 1011xxx - case 0x5C: case 0x5D: case 0x5E: case 0x5F: { - // CBNZ, CBZ - uint16_t op = (instr >> 11) & 1; - uint16_t i = (instr >> 9) & 1; - uint16_t imm5 = (instr >> 3) & 0x1F; - ThumbRegister Rn(instr, 0); - opcode << (op != 0 ? "cbnz" : "cbz"); - uint32_t imm32 = (i << 6) | (imm5 << 1); - args << Rn << ", "; - DumpBranchTarget(args, instr_ptr + 4, imm32); - break; - } - case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27: - case 0x28: case 0x29: case 0x2A: case 0x2B: case 0x2C: case 0x2D: case 0x2E: case 0x2F: { - opcode << "push"; - args << RegisterList((instr & 0xFF) | ((instr & 0x100) << 6)); - break; - } - case 0x60: case 0x61: case 0x62: case 0x63: case 0x64: case 0x65: case 0x66: case 0x67: - case 0x68: case 0x69: case 0x6A: case 0x6B: case 0x6C: case 0x6D: case 0x6E: case 0x6F: { - opcode << "pop"; - args << RegisterList((instr & 0xFF) | ((instr & 0x100) << 7)); - break; - } - case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: { - opcode << "bkpt"; - args << "#" << (instr & 0xFF); - break; - } - case 0x50: case 0x51: // 101000x - case 0x52: case 0x53: // 101001x - case 0x56: case 0x57: { // 101011x - uint16_t op = (instr >> 6) & 3; - opcode << kThumbReverseOperations[op]; - ThumbRegister Rm(instr, 3); - ThumbRegister Rd(instr, 0); - args << Rd << ", " << Rm; - break; - } - case 0x78: case 0x79: case 0x7A: case 0x7B: // 1111xxx - case 0x7C: case 0x7D: case 0x7E: case 0x7F: { - // If-Then, and hints - uint16_t opA = (instr >> 4) & 0xF; - uint16_t opB = instr & 0xF; - if (opB == 0) { - switch (opA) { - case 0: opcode << "nop"; break; - case 1: opcode << "yield"; break; - case 2: opcode << "wfe"; break; - case 3: opcode << "sev"; break; - default: break; - } - } else { - uint32_t first_cond = opA; - uint32_t mask = opB; - opcode << "it"; + const uint32_t* const ip = reinterpret_cast<const uint32_t*>(instr_ptr); + next = reinterpret_cast<uintptr_t>(disasm_->DecodeA32At(ip)); + } - // Flesh out the base "it" opcode with the specific collection of 't's and 'e's, - // and store up the actual condition codes we'll want to add to the next few opcodes. - size_t count = 3 - CTZ(mask); - it_conditions_.resize(count + 2); // Plus the implicit 't', plus the "" for the IT itself. - for (size_t i = 0; i < count; ++i) { - bool positive_cond = ((first_cond & 1) != 0); - bool positive_mask = ((mask & (1 << (3 - i))) != 0); - if (positive_mask == positive_cond) { - opcode << 't'; - it_conditions_[i] = kConditionCodeNames[first_cond]; - } else { - opcode << 'e'; - it_conditions_[i] = kConditionCodeNames[first_cond ^ 1]; - } - } - it_conditions_[count] = kConditionCodeNames[first_cond]; // The implicit 't'. + os << output_.str(); + output_.str(std::string()); + return next - instr_ptr; +} - it_conditions_[count + 1] = ""; // No condition code for the IT itself... - DumpCond(args, first_cond); // ...because it's considered an argument. - } - break; - } - default: - break; - } - } else if (((instr & 0xF000) == 0x5000) || ((instr & 0xE000) == 0x6000) || - ((instr & 0xE000) == 0x8000)) { - // Load/store single data item - uint16_t opA = instr >> 12; - // uint16_t opB = (instr >> 9) & 7; - switch (opA) { - case 0x6: { - // STR Rt, [Rn, #imm] - 01100 iiiii nnn ttt - // LDR Rt, [Rn, #imm] - 01101 iiiii nnn ttt - uint16_t imm5 = (instr >> 6) & 0x1F; - ThumbRegister Rn(instr, 3); - ThumbRegister Rt(instr, 0); - opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); - args << Rt << ", [" << Rn << ", #" << (imm5 << 2) << "]"; - break; - } - case 0x9: { - // STR Rt, [SP, #imm] - 01100 ttt iiiiiiii - // LDR Rt, [SP, #imm] - 01101 ttt iiiiiiii - uint16_t imm8 = instr & 0xFF; - ThumbRegister Rt(instr, 8); - opcode << ((instr & 0x800) == 0 ? "str" : "ldr"); - args << Rt << ", [sp, #" << (imm8 << 2) << "]"; - break; - } - default: - break; - } - } else if (opcode1 == 0x38 || opcode1 == 0x39) { - uint16_t imm11 = instr & 0x7FFF; - int32_t imm32 = imm11 << 1; - imm32 = (imm32 << 20) >> 20; // sign extend 12 bit immediate - opcode << "b"; - DumpBranchTarget(args, instr_ptr + 4, imm32); - } +void DisassemblerArm::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { + DCHECK_LE(begin, end); - // Apply any IT-block conditions to the opcode if necessary. - if (!it_conditions_.empty()) { - opcode << it_conditions_.back(); - it_conditions_.pop_back(); - } + // Remove the Thumb specifier bit; no effect if begin does not point to T32 code. + const uintptr_t base = reinterpret_cast<uintptr_t>(begin) & ~1; + + const bool is_t32 = (reinterpret_cast<uintptr_t>(begin) & 1) != 0; + disasm_->SetCodeAddress(GetPc(base)); - os << FormatInstructionPointer(instr_ptr) - << StringPrintf(": %04x \t%-7s ", instr, opcode.str().c_str()) - << args.str() << '\n'; + if (is_t32) { + // The Thumb specifier bits cancel each other. + disasm_->DisassembleT32Buffer(reinterpret_cast<const uint16_t*>(base), end - begin); + } else { + disasm_->DisassembleA32Buffer(reinterpret_cast<const uint32_t*>(base), end - begin); } - return 2; + + os << output_.str(); + output_.str(std::string()); } } // namespace arm diff --git a/disassembler/disassembler_arm.h b/disassembler/disassembler_arm.h index f870e8ef86..237b577bc2 100644 --- a/disassembler/disassembler_arm.h +++ b/disassembler/disassembler_arm.h @@ -17,32 +17,33 @@ #ifndef ART_DISASSEMBLER_DISASSEMBLER_ARM_H_ #define ART_DISASSEMBLER_DISASSEMBLER_ARM_H_ -#include <vector> +#include <memory> +#include <sstream> +#include "base/macros.h" #include "disassembler.h" namespace art { namespace arm { class DisassemblerArm FINAL : public Disassembler { + class CustomDisassembler; + public: - explicit DisassemblerArm(DisassemblerOptions* options) : Disassembler(options) {} + explicit DisassemblerArm(DisassemblerOptions* options); size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE; void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE; private: - void DumpArm(std::ostream& os, const uint8_t* instr); - - // Returns the size of the instruction just decoded - size_t DumpThumb16(std::ostream& os, const uint8_t* instr); - size_t DumpThumb32(std::ostream& os, const uint8_t* instr_ptr); - - void DumpBranchTarget(std::ostream& os, const uint8_t* instr_ptr, int32_t imm32); - void DumpCond(std::ostream& os, uint32_t cond); - void DumpMemoryDomain(std::ostream& os, uint32_t domain); - - std::vector<const char*> it_conditions_; + uintptr_t GetPc(uintptr_t instr_ptr) const { + return GetDisassemblerOptions()->absolute_addresses_ + ? instr_ptr + : instr_ptr - reinterpret_cast<uintptr_t>(GetDisassemblerOptions()->base_address_); + } + + std::ostringstream output_; + std::unique_ptr<CustomDisassembler> disasm_; DISALLOW_COPY_AND_ASSIGN(DisassemblerArm); }; diff --git a/disassembler/disassembler_arm64.cc b/disassembler/disassembler_arm64.cc index 6a9afe5740..49b9623f4f 100644 --- a/disassembler/disassembler_arm64.cc +++ b/disassembler/disassembler_arm64.cc @@ -20,9 +20,12 @@ #include <sstream> -#include "base/logging.h" -#include "base/stringprintf.h" -#include "thread.h" +#include "android-base/logging.h" +#include "android-base/stringprintf.h" + +using android::base::StringPrintf; + +using namespace vixl::aarch64; // NOLINT(build/namespaces) namespace art { namespace arm64 { @@ -38,15 +41,14 @@ enum { LR = 30 }; -void CustomDisassembler::AppendRegisterNameToOutput( - const vixl::Instruction* instr, - const vixl::CPURegister& reg) { +void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, + const CPURegister& reg) { USE(instr); if (reg.IsRegister() && reg.Is64Bits()) { - if (reg.code() == TR) { + if (reg.GetCode() == TR) { AppendToOutput("tr"); return; - } else if (reg.code() == LR) { + } else if (reg.GetCode() == LR) { AppendToOutput("lr"); return; } @@ -56,7 +58,7 @@ void CustomDisassembler::AppendRegisterNameToOutput( Disassembler::AppendRegisterNameToOutput(instr, reg); } -void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) { +void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) { Disassembler::VisitLoadLiteral(instr); if (!read_literals_) { @@ -66,27 +68,27 @@ void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) { // Get address of literal. Bail if not within expected buffer range to // avoid trying to fetch invalid literals (we can encounter this when // interpreting raw data as instructions). - void* data_address = instr->LiteralAddress<void*>(); + void* data_address = instr->GetLiteralAddress<void*>(); if (data_address < base_address_ || data_address >= end_address_) { AppendToOutput(" (?)"); return; } // Output information on literal. - vixl::Instr op = instr->Mask(vixl::LoadLiteralMask); + Instr op = instr->Mask(LoadLiteralMask); switch (op) { - case vixl::LDR_w_lit: - case vixl::LDR_x_lit: - case vixl::LDRSW_x_lit: { - int64_t data = op == vixl::LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address) - : *reinterpret_cast<int32_t*>(data_address); + case LDR_w_lit: + case LDR_x_lit: + case LDRSW_x_lit: { + int64_t data = op == LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address) + : *reinterpret_cast<int32_t*>(data_address); AppendToOutput(" (0x%" PRIx64 " / %" PRId64 ")", data, data); break; } - case vixl::LDR_s_lit: - case vixl::LDR_d_lit: { - double data = (op == vixl::LDR_s_lit) ? *reinterpret_cast<float*>(data_address) - : *reinterpret_cast<double*>(data_address); + case LDR_s_lit: + case LDR_d_lit: { + double data = (op == LDR_s_lit) ? *reinterpret_cast<float*>(data_address) + : *reinterpret_cast<double*>(data_address); AppendToOutput(" (%g)", data); break; } @@ -95,27 +97,27 @@ void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) { } } -void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) { +void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) { Disassembler::VisitLoadStoreUnsignedOffset(instr); - if (instr->Rn() == TR) { - int64_t offset = instr->ImmLSUnsigned() << instr->SizeLS(); + if (instr->GetRn() == TR) { + int64_t offset = instr->GetImmLSUnsigned() << instr->GetSizeLS(); std::ostringstream tmp_stream; - Thread::DumpThreadOffset<8>(tmp_stream, static_cast<uint32_t>(offset)); + options_->thread_offset_name_function_(tmp_stream, static_cast<uint32_t>(offset)); AppendToOutput(" ; %s", tmp_stream.str().c_str()); } } size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) { - const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin); + const Instruction* instr = reinterpret_cast<const Instruction*>(begin); decoder.Decode(instr); os << FormatInstructionPointer(begin) - << StringPrintf(": %08x\t%s\n", instr->InstructionBits(), disasm.GetOutput()); - return vixl::kInstructionSize; + << StringPrintf(": %08x\t%s\n", instr->GetInstructionBits(), disasm.GetOutput()); + return kInstructionSize; } void DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) { - for (const uint8_t* cur = begin; cur < end; cur += vixl::kInstructionSize) { + for (const uint8_t* cur = begin; cur < end; cur += kInstructionSize) { Dump(os, cur); } } diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h index a4e5ee8a43..19e4dfb486 100644 --- a/disassembler/disassembler_arm64.h +++ b/disassembler/disassembler_arm64.h @@ -19,36 +19,39 @@ #include "disassembler.h" +// TODO(VIXL): Make VIXL compile with -Wshadow. #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wshadow" -#include "vixl/a64/decoder-a64.h" -#include "vixl/a64/disasm-a64.h" +#include "aarch64/decoder-aarch64.h" +#include "aarch64/disasm-aarch64.h" #pragma GCC diagnostic pop namespace art { namespace arm64 { -class CustomDisassembler FINAL : public vixl::Disassembler { +class CustomDisassembler FINAL : public vixl::aarch64::Disassembler { public: explicit CustomDisassembler(DisassemblerOptions* options) - : vixl::Disassembler(), + : vixl::aarch64::Disassembler(), read_literals_(options->can_read_literals_), base_address_(options->base_address_), - end_address_(options->end_address_) { + end_address_(options->end_address_), + options_(options) { if (!options->absolute_addresses_) { - MapCodeAddress(0, reinterpret_cast<const vixl::Instruction*>(options->base_address_)); + MapCodeAddress(0, + reinterpret_cast<const vixl::aarch64::Instruction*>(options->base_address_)); } } // Use register aliases in the disassembly. - void AppendRegisterNameToOutput(const vixl::Instruction* instr, - const vixl::CPURegister& reg) OVERRIDE; + void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr, + const vixl::aarch64::CPURegister& reg) OVERRIDE; // Improve the disassembly of literal load instructions. - void VisitLoadLiteral(const vixl::Instruction* instr) OVERRIDE; + void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE; // Improve the disassembly of thread offset. - void VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) OVERRIDE; + void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE; private: // Indicate if the disassembler should read data loaded from literal pools. @@ -62,6 +65,8 @@ class CustomDisassembler FINAL : public vixl::Disassembler { // Valid address range: [base_address_, end_address_) const void* const base_address_; const void* const end_address_; + + DisassemblerOptions* options_; }; class DisassemblerArm64 FINAL : public Disassembler { @@ -75,7 +80,7 @@ class DisassemblerArm64 FINAL : public Disassembler { void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE; private: - vixl::Decoder decoder; + vixl::aarch64::Decoder decoder; CustomDisassembler disasm; DISALLOW_COPY_AND_ASSIGN(DisassemblerArm64); diff --git a/disassembler/disassembler_mips.cc b/disassembler/disassembler_mips.cc index a95ea649c7..eb57d339af 100644 --- a/disassembler/disassembler_mips.cc +++ b/disassembler/disassembler_mips.cc @@ -19,9 +19,12 @@ #include <ostream> #include <sstream> -#include "base/logging.h" -#include "base/stringprintf.h" -#include "thread.h" +#include "android-base/logging.h" +#include "android-base/stringprintf.h" + +#include "base/bit_utils.h" + +using android::base::StringPrintf; namespace art { namespace mips { @@ -40,6 +43,7 @@ struct MipsInstruction { static const uint32_t kOpcodeShift = 26; static const uint32_t kCop1 = (17 << kOpcodeShift); +static const uint32_t kMsa = (30 << kOpcodeShift); // MSA major opcode. static const uint32_t kITypeMask = (0x3f << kOpcodeShift); static const uint32_t kJTypeMask = (0x3f << kOpcodeShift); @@ -48,6 +52,8 @@ static const uint32_t kSpecial0Mask = (0x3f << kOpcodeShift); static const uint32_t kSpecial2Mask = (0x3f << kOpcodeShift); static const uint32_t kSpecial3Mask = (0x3f << kOpcodeShift); static const uint32_t kFpMask = kRTypeMask; +static const uint32_t kMsaMask = kRTypeMask; +static const uint32_t kMsaSpecialMask = (0x3f << kOpcodeShift); static const MipsInstruction gMipsInstructions[] = { // "sll r0, r0, 0" is the canonical "nop", used in delay slots. @@ -136,6 +142,8 @@ static const MipsInstruction gMipsInstructions[] = { { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x11, "clo", "DS" }, { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x12, "dclz", "DS" }, { kSpecial0Mask | (0x1f << 16) | 0x7ff, (0x01 << 6) | 0x13, "dclo", "DS" }, + { kSpecial0Mask | 0x73f, 0x05, "lsa", "DSTj" }, + { kSpecial0Mask | 0x73f, 0x15, "dlsa", "DSTj" }, // TODO: sdbbp // SPECIAL2 @@ -153,6 +161,7 @@ static const MipsInstruction gMipsInstructions[] = { { kSpecial3Mask | 0x3f, (31 << kOpcodeShift), "ext", "TSAZ", }, { kSpecial3Mask | 0x3f, (31 << kOpcodeShift) | 3, "dext", "TSAZ", }, { kSpecial3Mask | 0x3f, (31 << kOpcodeShift) | 4, "ins", "TSAz", }, + { kSpecial3Mask | 0x3f, (31 << kOpcodeShift) | 6, "dinsu", "TSFz", }, { kSpecial3Mask | (0x1f << 21) | (0x1f << 6) | 0x3f, (31 << kOpcodeShift) | (16 << 6) | 32, "seb", @@ -217,8 +226,8 @@ static const MipsInstruction gMipsInstructions[] = { { kITypeMask, 12 << kOpcodeShift, "andi", "TSi", }, { kITypeMask, 13 << kOpcodeShift, "ori", "TSi", }, { kITypeMask, 14 << kOpcodeShift, "xori", "TSi", }, - { kITypeMask | (0x1f << 21), 15 << kOpcodeShift, "lui", "TI", }, - { kITypeMask, 15 << kOpcodeShift, "aui", "TSI", }, + { kITypeMask | (0x1f << 21), 15 << kOpcodeShift, "lui", "Ti", }, + { kITypeMask, 15 << kOpcodeShift, "aui", "TSi", }, { kITypeMask | (0x3e3 << 16), (17 << kOpcodeShift) | (8 << 21), "bc1f", "cB" }, { kITypeMask | (0x3e3 << 16), (17 << kOpcodeShift) | (8 << 21) | (1 << 16), "bc1t", "cB" }, @@ -330,8 +339,12 @@ static const MipsInstruction gMipsInstructions[] = { { kITypeMask, 55u << kOpcodeShift, "ld", "TO", }, { kITypeMask, 56u << kOpcodeShift, "sc", "TO", }, { kITypeMask, 57u << kOpcodeShift, "swc1", "tO", }, + { kJTypeMask, 58u << kOpcodeShift, "balc", "P" }, { kITypeMask | (0x1f << 16), (59u << kOpcodeShift) | (30 << 16), "auipc", "Si" }, { kITypeMask | (0x3 << 19), (59u << kOpcodeShift) | (0 << 19), "addiupc", "Sp" }, + { kITypeMask | (0x3 << 19), (59u << kOpcodeShift) | (1 << 19), "lwpc", "So" }, + { kITypeMask | (0x3 << 19), (59u << kOpcodeShift) | (2 << 19), "lwupc", "So" }, + { kITypeMask | (0x7 << 18), (59u << kOpcodeShift) | (6 << 18), "ldpc", "S0" }, { kITypeMask, 61u << kOpcodeShift, "sdc1", "tO", }, { kITypeMask | (0x1f << 21), 62u << kOpcodeShift, "jialc", "Ti" }, { kITypeMask | (1 << 21), (62u << kOpcodeShift) | (1 << 21), "bnezc", "Sb" }, // TODO: de-dup? @@ -384,6 +397,12 @@ static const MipsInstruction gMipsInstructions[] = { { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 13, "trunc.w", "fad" }, { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 14, "ceil.w", "fad" }, { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 15, "floor.w", "fad" }, + { kFpMask | (0x201 << 16), kCop1 | (0x200 << 16) | 17, "movf", "fadc" }, + { kFpMask | (0x201 << 16), kCop1 | (0x201 << 16) | 17, "movt", "fadc" }, + { kFpMask | (0x10 << 21), kCop1 | (0x10 << 21) | 18, "movz", "fadT" }, + { kFpMask | (0x10 << 21), kCop1 | (0x10 << 21) | 19, "movn", "fadT" }, + { kFpMask | (0x10 << 21), kCop1 | (0x10 << 21) | 20, "seleqz", "fadt" }, + { kFpMask | (0x10 << 21), kCop1 | (0x10 << 21) | 23, "selnez", "fadt" }, { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 26, "rint", "fad" }, { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 27, "class", "fad" }, { kFpMask | (0x21f << 16), kCop1 | (0x200 << 16) | 32, "cvt.s", "fad" }, @@ -401,6 +420,37 @@ static const MipsInstruction gMipsInstructions[] = { { kFpMask, kCop1 | 0x10, "sel", "fadt" }, { kFpMask, kCop1 | 0x1e, "max", "fadt" }, { kFpMask, kCop1 | 0x1c, "min", "fadt" }, + + // MSA instructions. + { kMsaMask | (0x1f << 21), kMsa | (0x0 << 21) | 0x1e, "and.v", "kmn" }, + { kMsaMask | (0x1f << 21), kMsa | (0x1 << 21) | 0x1e, "or.v", "kmn" }, + { kMsaMask | (0x1f << 21), kMsa | (0x2 << 21) | 0x1e, "nor.v", "kmn" }, + { kMsaMask | (0x1f << 21), kMsa | (0x3 << 21) | 0x1e, "xor.v", "kmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x0 << 23) | 0xe, "addv", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x1 << 23) | 0xe, "subv", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x0 << 23) | 0x12, "mulv", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x4 << 23) | 0x12, "div_s", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x5 << 23) | 0x12, "div_u", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x6 << 23) | 0x12, "mod_s", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x7 << 23) | 0x12, "mod_u", "Vkmn" }, + { kMsaMask | (0xf << 22), kMsa | (0x0 << 22) | 0x1b, "fadd", "Ukmn" }, + { kMsaMask | (0xf << 22), kMsa | (0x1 << 22) | 0x1b, "fsub", "Ukmn" }, + { kMsaMask | (0xf << 22), kMsa | (0x2 << 22) | 0x1b, "fmul", "Ukmn" }, + { kMsaMask | (0xf << 22), kMsa | (0x3 << 22) | 0x1b, "fdiv", "Ukmn" }, + { kMsaMask | (0x1ff << 17), kMsa | (0x19e << 17) | 0x1e, "ffint_s", "ukm" }, + { kMsaMask | (0x1ff << 17), kMsa | (0x19c << 17) | 0x1e, "ftint_s", "ukm" }, + { kMsaMask | (0x7 << 23), kMsa | (0x0 << 23) | 0xd, "sll", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x1 << 23) | 0xd, "sra", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x2 << 23) | 0xd, "srl", "Vkmn" }, + { kMsaMask | (0x7 << 23), kMsa | (0x0 << 23) | 0x9, "slli", "kmW" }, + { kMsaMask | (0x7 << 23), kMsa | (0x1 << 23) | 0x9, "srai", "kmW" }, + { kMsaMask | (0x7 << 23), kMsa | (0x2 << 23) | 0x9, "srli", "kmW" }, + { kMsaMask | (0x3ff << 16), kMsa | (0xbe << 16) | 0x19, "move.v", "km" }, + { kMsaMask | (0xf << 22), kMsa | (0x1 << 22) | 0x19, "splati", "kX" }, + { kMsaMask | (0xff << 18), kMsa | (0xc0 << 18) | 0x1e, "fill", "vkD" }, + { kMsaMask | (0x7 << 23), kMsa | (0x6 << 23) | 0x7, "ldi", "kx" }, + { kMsaSpecialMask | (0xf << 2), kMsa | (0x8 << 2), "ld", "kw" }, + { kMsaSpecialMask | (0xf << 2), kMsa | (0x9 << 2), "st", "kw" }, }; static uint32_t ReadU32(const uint8_t* ptr) { @@ -459,6 +509,7 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) { case 'D': args << 'r' << rd; break; case 'd': args << 'f' << rd; break; case 'a': args << 'f' << sa; break; + case 'F': args << (sa + 32); break; // dinsu position. case 'f': // Floating point "fmt". { size_t fmt = (instruction >> 21) & 0x7; // TODO: other fmts? @@ -472,12 +523,12 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) { } continue; // No ", ". } - case 'I': // Upper 16-bit immediate. - args << reinterpret_cast<void*>((instruction & 0xffff) << 16); - break; case 'i': // Sign-extended lower 16-bit immediate. args << static_cast<int16_t>(instruction & 0xffff); break; + case 'j': // sa value for lsa/dlsa. + args << (sa + 1); + break; case 'L': // Jump label. { // TODO: is this right? @@ -499,15 +550,28 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) { args << StringPrintf("%+d(r%d)", offset, rs); if (rs == 17) { args << " ; "; - if (is64bit_) { - Thread::DumpThreadOffset<8>(args, offset); - } else { - Thread::DumpThreadOffset<4>(args, offset); - } + GetDisassemblerOptions()->thread_offset_name_function_(args, offset); } } break; - case 'P': // 26-bit offset in bc. + case 'o': // 19-bit offset in lwpc and lwupc. + { + int32_t offset = (instruction & 0x7ffff) - ((instruction & 0x40000) << 1); + offset <<= 2; + args << FormatInstructionPointer(instr_ptr + offset); + args << StringPrintf(" ; %+d", offset); + } + break; + case '0': // 18-bit offset in ldpc. + { + int32_t offset = (instruction & 0x3ffff) - ((instruction & 0x20000) << 1); + offset <<= 3; + uintptr_t ptr = RoundDown(reinterpret_cast<uintptr_t>(instr_ptr), 8); + args << FormatInstructionPointer(reinterpret_cast<const uint8_t*>(ptr + offset)); + args << StringPrintf(" ; %+d", offset); + } + break; + case 'P': // 26-bit offset in bc and balc. { int32_t offset = (instruction & 0x3ffffff) - ((instruction & 0x2000000) << 1); offset <<= 2; @@ -528,7 +592,126 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) { case 'T': args << 'r' << rt; break; case 't': args << 'f' << rt; break; case 'Z': args << (rd + 1); break; // sz ([d]ext size). - case 'z': args << (rd - sa + 1); break; // sz ([d]ins size). + case 'z': args << (rd - sa + 1); break; // sz ([d]ins, dinsu size). + case 'k': args << 'w' << sa; break; + case 'm': args << 'w' << rd; break; + case 'n': args << 'w' << rt; break; + case 'U': // MSA 1-bit df (word/doubleword), position 21. + { + int32_t df = (instruction >> 21) & 0x1; + switch (df) { + case 0: opcode += ".w"; break; + case 1: opcode += ".d"; break; + } + continue; // No ", ". + } + case 'u': // MSA 1-bit df (word/doubleword), position 16. + { + int32_t df = (instruction >> 16) & 0x1; + switch (df) { + case 0: opcode += ".w"; break; + case 1: opcode += ".d"; break; + } + continue; // No ", ". + } + case 'V': // MSA 2-bit df, position 21. + { + int32_t df = (instruction >> 21) & 0x3; + switch (df) { + case 0: opcode += ".b"; break; + case 1: opcode += ".h"; break; + case 2: opcode += ".w"; break; + case 3: opcode += ".d"; break; + } + continue; // No ", ". + } + case 'v': // MSA 2-bit df, position 16. + { + int32_t df = (instruction >> 16) & 0x3; + switch (df) { + case 0: opcode += ".b"; break; + case 1: opcode += ".h"; break; + case 2: opcode += ".w"; break; + case 3: opcode += ".d"; break; + } + continue; // No ", ". + } + case 'W': // MSA df/m. + { + int32_t df_m = (instruction >> 16) & 0x7f; + if ((df_m & (0x1 << 6)) == 0) { + opcode += ".d"; + args << (df_m & 0x3f); + break; + } + if ((df_m & (0x1 << 5)) == 0) { + opcode += ".w"; + args << (df_m & 0x1f); + break; + } + if ((df_m & (0x1 << 4)) == 0) { + opcode += ".h"; + args << (df_m & 0xf); + break; + } + if ((df_m & (0x1 << 3)) == 0) { + opcode += ".b"; + args << (df_m & 0x7); + } + break; + } + case 'w': // MSA +x(rs). + { + int32_t df = instruction & 0x3; + int32_t s10 = (instruction >> 16) & 0x3ff; + s10 -= (s10 & 0x200) << 1; // Sign-extend s10. + switch (df) { + case 0: opcode += ".b"; break; + case 1: opcode += ".h"; break; + case 2: opcode += ".w"; break; + case 3: opcode += ".d"; break; + } + args << StringPrintf("%+d(r%d)", s10 << df, rd); + break; + } + case 'X': // MSA df/n - ws[x]. + { + int32_t df_n = (instruction >> 16) & 0x3f; + if ((df_n & (0x3 << 4)) == 0) { + opcode += ".b"; + args << 'w' << rd << '[' << (df_n & 0xf) << ']'; + break; + } + if ((df_n & (0x3 << 3)) == 0) { + opcode += ".h"; + args << 'w' << rd << '[' << (df_n & 0x7) << ']'; + break; + } + if ((df_n & (0x3 << 2)) == 0) { + opcode += ".w"; + args << 'w' << rd << '[' << (df_n & 0x3) << ']'; + break; + } + if ((df_n & (0x3 << 1)) == 0) { + opcode += ".d"; + args << 'w' << rd << '[' << (df_n & 0x1) << ']'; + } + break; + } + case 'x': // MSA i10. + { + int32_t df = (instruction >> 21) & 0x3; + int32_t i10 = (instruction >> 11) & 0x3ff; + i10 -= (i10 & 0x200) << 1; // Sign-extend i10. + switch (df) { + case 0: opcode += ".b"; break; + case 1: opcode += ".h"; break; + case 2: opcode += ".w"; break; + case 3: opcode += ".d"; break; + } + args << i10; + break; + } } if (*(args_fmt + 1)) { args << ", "; @@ -544,10 +727,8 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) { // jic reg, imm // pc-relative +/- 2GB branch and link: // auipc reg, imm - // daddiu reg, reg, imm - // jialc reg, 0 - if (((op == 0x36 && rs == 0 && rt != 0) || // jic - (op == 0x19 && rs == rt && rt != 0)) && // daddiu + // jialc reg, imm + if (((op == 0x36 || op == 0x3E) && rs == 0 && rt != 0) && // ji[al]c last_ptr_ && (intptr_t)instr_ptr - (intptr_t)last_ptr_ == 4 && (last_instr_ & 0xFC1F0000) == 0xEC1E0000 && // auipc ((last_instr_ >> 21) & 0x1F) == rt) { @@ -555,9 +736,9 @@ size_t DisassemblerMips::Dump(std::ostream& os, const uint8_t* instr_ptr) { offset -= (offset & 0x8000) << 1; offset -= 4; if (op == 0x36) { - args << " ; b "; + args << " ; bc "; } else { - args << " ; move r" << rt << ", "; + args << " ; balc "; } args << FormatInstructionPointer(instr_ptr + (int32_t)offset); args << StringPrintf(" ; %+d", (int32_t)offset); diff --git a/disassembler/disassembler_mips.h b/disassembler/disassembler_mips.h index b0e49b3978..6342f22962 100644 --- a/disassembler/disassembler_mips.h +++ b/disassembler/disassembler_mips.h @@ -26,9 +26,8 @@ namespace mips { class DisassemblerMips FINAL : public Disassembler { public: - DisassemblerMips(DisassemblerOptions* options, bool is64bit) + explicit DisassemblerMips(DisassemblerOptions* options) : Disassembler(options), - is64bit_(is64bit), last_ptr_(nullptr), last_instr_(0) {} @@ -36,8 +35,6 @@ class DisassemblerMips FINAL : public Disassembler { void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE; private: - const bool is64bit_; - // Address and encoding of the last disassembled instruction. // Needed to produce more readable disassembly of certain 2-instruction sequences. const uint8_t* last_ptr_; diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index 1f74c93045..e12bcec776 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -21,9 +21,10 @@ #include <ostream> #include <sstream> -#include "base/logging.h" -#include "base/stringprintf.h" -#include "thread.h" +#include "android-base/logging.h" +#include "android-base/stringprintf.h" + +using android::base::StringPrintf; namespace art { namespace x86 { @@ -243,7 +244,38 @@ std::string DisassemblerX86::DumpAddress(uint8_t mod, uint8_t rm, uint8_t rex64, return address.str(); } +size_t DisassemblerX86::DumpNops(std::ostream& os, const uint8_t* instr) { +static constexpr uint8_t kNops[][10] = { + { }, + { 0x90 }, + { 0x66, 0x90 }, + { 0x0f, 0x1f, 0x00 }, + { 0x0f, 0x1f, 0x40, 0x00 }, + { 0x0f, 0x1f, 0x44, 0x00, 0x00 }, + { 0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00 }, + { 0x0f, 0x1f, 0x80, 0x00, 0x00, 0x00, 0x00 }, + { 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x66, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 }, + { 0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 } + }; + + for (size_t i = 1; i < arraysize(kNops); ++i) { + if (memcmp(instr, kNops[i], i) == 0) { + os << FormatInstructionPointer(instr) + << StringPrintf(": %22s \t nop \n", DumpCodeHex(instr, instr + i).c_str()); + return i; + } + } + + return 0; +} + size_t DisassemblerX86::DumpInstruction(std::ostream& os, const uint8_t* instr) { + size_t nop_size = DumpNops(os, instr); + if (nop_size != 0u) { + return nop_size; + } + const uint8_t* begin_instr = instr; bool have_prefixes = true; uint8_t prefix[4] = {0, 0, 0, 0}; @@ -400,6 +432,7 @@ DISASSEMBLER_ENTRY(cmp, case 0x89: opcode1 = "mov"; store = true; has_modrm = true; break; case 0x8A: opcode1 = "mov"; load = true; has_modrm = true; byte_operand = true; break; case 0x8B: opcode1 = "mov"; load = true; has_modrm = true; break; + case 0x9D: opcode1 = "popf"; break; case 0x0F: // 2 byte extended opcode instr++; @@ -541,6 +574,20 @@ DISASSEMBLER_ENTRY(cmp, load = true; src_reg_file = dst_reg_file = SSE; break; + case 0x29: + opcode1 = "pcmpeqq"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x39: + opcode1 = "pcmpgtq"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; case 0x40: opcode1 = "pmulld"; prefix[2] = 0; @@ -565,7 +612,7 @@ DISASSEMBLER_ENTRY(cmp, opcode1 = "roundss"; prefix[2] = 0; has_modrm = true; - store = true; + load = true; src_reg_file = SSE; dst_reg_file = SSE; immediate_bytes = 1; @@ -574,7 +621,7 @@ DISASSEMBLER_ENTRY(cmp, opcode1 = "roundsd"; prefix[2] = 0; has_modrm = true; - store = true; + load = true; src_reg_file = SSE; dst_reg_file = SSE; immediate_bytes = 1; @@ -704,6 +751,24 @@ DISASSEMBLER_ENTRY(cmp, load = true; has_modrm = true; break; + case 0x64: + case 0x65: + case 0x66: + if (prefix[2] == 0x66) { + src_reg_file = dst_reg_file = SSE; + prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode + } else { + src_reg_file = dst_reg_file = MMX; + } + switch (*instr) { + case 0x64: opcode1 = "pcmpgtb"; break; + case 0x65: opcode1 = "pcmpgtw"; break; + case 0x66: opcode1 = "pcmpgtd"; break; + } + prefix[2] = 0; + has_modrm = true; + load = true; + break; case 0x6E: if (prefix[2] == 0x66) { dst_reg_file = SSE; @@ -799,6 +864,24 @@ DISASSEMBLER_ENTRY(cmp, store = true; immediate_bytes = 1; break; + case 0x74: + case 0x75: + case 0x76: + if (prefix[2] == 0x66) { + src_reg_file = dst_reg_file = SSE; + prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode + } else { + src_reg_file = dst_reg_file = MMX; + } + switch (*instr) { + case 0x74: opcode1 = "pcmpeqb"; break; + case 0x75: opcode1 = "pcmpeqw"; break; + case 0x76: opcode1 = "pcmpeqd"; break; + } + prefix[2] = 0; + has_modrm = true; + load = true; + break; case 0x7C: if (prefix[0] == 0xF2) { opcode1 = "haddps"; @@ -826,6 +909,22 @@ DISASSEMBLER_ENTRY(cmp, has_modrm = true; store = true; break; + case 0x7F: + if (prefix[2] == 0x66) { + src_reg_file = dst_reg_file = SSE; + opcode1 = "movdqa"; + prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode + } else if (prefix[0] == 0xF3) { + src_reg_file = dst_reg_file = SSE; + opcode1 = "movdqu"; + prefix[0] = 0; // clear prefix now it's served its purpose as part of the opcode + } else { + dst_reg_file = MMX; + opcode1 = "movq"; + } + store = true; + has_modrm = true; + break; case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: case 0x89: case 0x8A: case 0x8B: case 0x8C: case 0x8D: case 0x8E: case 0x8F: opcode1 = "j"; @@ -1034,6 +1133,22 @@ DISASSEMBLER_ENTRY(cmp, opcode1 = opcode_tmp.c_str(); } break; + case 0xE0: + case 0xE3: + if (prefix[2] == 0x66) { + src_reg_file = dst_reg_file = SSE; + prefix[2] = 0; // clear prefix now it's served its purpose as part of the opcode + } else { + src_reg_file = dst_reg_file = MMX; + } + switch (*instr) { + case 0xE0: opcode1 = "pavgb"; break; + case 0xE3: opcode1 = "pavgw"; break; + } + prefix[2] = 0; + has_modrm = true; + load = true; + break; case 0xEB: if (prefix[2] == 0x66) { src_reg_file = dst_reg_file = SSE; @@ -1257,7 +1372,7 @@ DISASSEMBLER_ENTRY(cmp, has_modrm = true; reg_is_opcode = true; store = true; - immediate_bytes = ((instr[1] & 0x38) == 0) ? 1 : 0; + immediate_bytes = ((instr[1] & 0x38) == 0) ? (instr[0] == 0xF7 ? 4 : 1) : 0; break; case 0xFF: { @@ -1377,11 +1492,11 @@ DISASSEMBLER_ENTRY(cmp, } if (prefix[1] == kFs && !supports_rex_) { args << " ; "; - Thread::DumpThreadOffset<4>(args, address_bits); + GetDisassemblerOptions()->thread_offset_name_function_(args, address_bits); } if (prefix[1] == kGs && supports_rex_) { args << " ; "; - Thread::DumpThreadOffset<8>(args, address_bits); + GetDisassemblerOptions()->thread_offset_name_function_(args, address_bits); } const char* prefix_str; switch (prefix[0]) { diff --git a/disassembler/disassembler_x86.h b/disassembler/disassembler_x86.h index 71c3e4161c..31b62bccf2 100644 --- a/disassembler/disassembler_x86.h +++ b/disassembler/disassembler_x86.h @@ -33,6 +33,7 @@ class DisassemblerX86 FINAL : public Disassembler { void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE; private: + size_t DumpNops(std::ostream& os, const uint8_t* instr); size_t DumpInstruction(std::ostream& os, const uint8_t* instr); std::string DumpAddress(uint8_t mod, uint8_t rm, uint8_t rex64, uint8_t rex_w, bool no_ops, |