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-rw-r--r--disassembler/disassembler_arm.cc14
-rw-r--r--disassembler/disassembler_arm.h6
-rw-r--r--disassembler/disassembler_arm64.h14
-rw-r--r--disassembler/disassembler_mips.h6
-rw-r--r--disassembler/disassembler_x86.h6
5 files changed, 23 insertions, 23 deletions
diff --git a/disassembler/disassembler_arm.cc b/disassembler/disassembler_arm.cc
index 49f92499e3..c1a6f59341 100644
--- a/disassembler/disassembler_arm.cc
+++ b/disassembler/disassembler_arm.cc
@@ -39,15 +39,15 @@ using vixl::aarch32::pc;
static const vixl::aarch32::Register tr(TR);
-class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler {
- class CustomDisassemblerStream FINAL : public DisassemblerStream {
+class DisassemblerArm::CustomDisassembler final : public PrintDisassembler {
+ class CustomDisassemblerStream final : public DisassemblerStream {
public:
CustomDisassemblerStream(std::ostream& os,
const CustomDisassembler* disasm,
const DisassemblerOptions* options)
: DisassemblerStream(os), disasm_(disasm), options_(options) {}
- DisassemblerStream& operator<<(const PrintLabel& label) OVERRIDE {
+ DisassemblerStream& operator<<(const PrintLabel& label) override {
const LocationType type = label.GetLocationType();
switch (type) {
@@ -73,7 +73,7 @@ class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler {
}
}
- DisassemblerStream& operator<<(vixl::aarch32::Register reg) OVERRIDE {
+ DisassemblerStream& operator<<(vixl::aarch32::Register reg) override {
if (reg.Is(tr)) {
os() << "tr";
return *this;
@@ -82,7 +82,7 @@ class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler {
}
}
- DisassemblerStream& operator<<(const MemOperand& operand) OVERRIDE {
+ DisassemblerStream& operator<<(const MemOperand& operand) override {
// VIXL must use a PrintLabel object whenever the base register is PC;
// the following check verifies this invariant, and guards against bugs.
DCHECK(!operand.GetBaseRegister().Is(pc));
@@ -96,7 +96,7 @@ class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler {
return *this;
}
- DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) OVERRIDE {
+ DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override {
// VIXL must use a PrintLabel object whenever the base register is PC;
// the following check verifies this invariant, and guards against bugs.
DCHECK(!operand.GetBaseRegister().Is(pc));
@@ -116,7 +116,7 @@ class DisassemblerArm::CustomDisassembler FINAL : public PrintDisassembler {
disassembler_stream_(os, this, options),
is_t32_(true) {}
- void PrintCodeAddress(uint32_t prog_ctr) OVERRIDE {
+ void PrintCodeAddress(uint32_t prog_ctr) override {
os() << "0x" << std::hex << std::setw(8) << std::setfill('0') << prog_ctr << ": ";
}
diff --git a/disassembler/disassembler_arm.h b/disassembler/disassembler_arm.h
index 237b577bc2..dd6621d344 100644
--- a/disassembler/disassembler_arm.h
+++ b/disassembler/disassembler_arm.h
@@ -26,14 +26,14 @@
namespace art {
namespace arm {
-class DisassemblerArm FINAL : public Disassembler {
+class DisassemblerArm final : public Disassembler {
class CustomDisassembler;
public:
explicit DisassemblerArm(DisassemblerOptions* options);
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
uintptr_t GetPc(uintptr_t instr_ptr) const {
diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h
index 19e4dfb486..89beaa927b 100644
--- a/disassembler/disassembler_arm64.h
+++ b/disassembler/disassembler_arm64.h
@@ -29,7 +29,7 @@
namespace art {
namespace arm64 {
-class CustomDisassembler FINAL : public vixl::aarch64::Disassembler {
+class CustomDisassembler final : public vixl::aarch64::Disassembler {
public:
explicit CustomDisassembler(DisassemblerOptions* options)
: vixl::aarch64::Disassembler(),
@@ -45,13 +45,13 @@ class CustomDisassembler FINAL : public vixl::aarch64::Disassembler {
// Use register aliases in the disassembly.
void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
- const vixl::aarch64::CPURegister& reg) OVERRIDE;
+ const vixl::aarch64::CPURegister& reg) override;
// Improve the disassembly of literal load instructions.
- void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE;
+ void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) override;
// Improve the disassembly of thread offset.
- void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE;
+ void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) override;
private:
// Indicate if the disassembler should read data loaded from literal pools.
@@ -69,15 +69,15 @@ class CustomDisassembler FINAL : public vixl::aarch64::Disassembler {
DisassemblerOptions* options_;
};
-class DisassemblerArm64 FINAL : public Disassembler {
+class DisassemblerArm64 final : public Disassembler {
public:
explicit DisassemblerArm64(DisassemblerOptions* options) :
Disassembler(options), disasm(options) {
decoder.AppendVisitor(&disasm);
}
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
vixl::aarch64::Decoder decoder;
diff --git a/disassembler/disassembler_mips.h b/disassembler/disassembler_mips.h
index afa6af366f..bc74b43ac9 100644
--- a/disassembler/disassembler_mips.h
+++ b/disassembler/disassembler_mips.h
@@ -24,7 +24,7 @@
namespace art {
namespace mips {
-class DisassemblerMips FINAL : public Disassembler {
+class DisassemblerMips final : public Disassembler {
public:
explicit DisassemblerMips(DisassemblerOptions* options, bool is_o32_abi)
: Disassembler(options),
@@ -33,8 +33,8 @@ class DisassemblerMips FINAL : public Disassembler {
is_o32_abi_(is_o32_abi) {}
const char* RegName(uint32_t reg);
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
// Address and encoding of the last disassembled instruction.
diff --git a/disassembler/disassembler_x86.h b/disassembler/disassembler_x86.h
index 31b62bccf2..a329280b70 100644
--- a/disassembler/disassembler_x86.h
+++ b/disassembler/disassembler_x86.h
@@ -24,13 +24,13 @@ namespace x86 {
enum RegFile { GPR, MMX, SSE };
-class DisassemblerX86 FINAL : public Disassembler {
+class DisassemblerX86 final : public Disassembler {
public:
DisassemblerX86(DisassemblerOptions* options, bool supports_rex)
: Disassembler(options), supports_rex_(supports_rex) {}
- size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE;
- void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
+ size_t Dump(std::ostream& os, const uint8_t* begin) override;
+ void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override;
private:
size_t DumpNops(std::ostream& os, const uint8_t* instr);
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-10-20 11:18:12 +0000