summaryrefslogtreecommitdiff
path: root/disassembler
diff options
context:
space:
mode:
Diffstat (limited to 'disassembler')
-rw-r--r--disassembler/Android.mk4
-rw-r--r--disassembler/disassembler_arm64.cc49
-rw-r--r--disassembler/disassembler_arm64.h21
3 files changed, 38 insertions, 36 deletions
diff --git a/disassembler/Android.mk b/disassembler/Android.mk
index d76bbb8801..6905f884ef 100644
--- a/disassembler/Android.mk
+++ b/disassembler/Android.mk
@@ -91,9 +91,9 @@ define build-libart-disassembler
LOCAL_NATIVE_COVERAGE := $(ART_COVERAGE)
# For disassembler_arm64.
ifeq ($$(art_ndebug_or_debug),debug)
- LOCAL_SHARED_LIBRARIES += libvixl
+ LOCAL_SHARED_LIBRARIES += libvixl-arm64
else
- LOCAL_SHARED_LIBRARIES += libvixl
+ LOCAL_SHARED_LIBRARIES += libvixl-arm64
endif
ifeq ($$(art_target_or_host),target)
include $(BUILD_SHARED_LIBRARY)
diff --git a/disassembler/disassembler_arm64.cc b/disassembler/disassembler_arm64.cc
index 6a9afe5740..a93f7d5902 100644
--- a/disassembler/disassembler_arm64.cc
+++ b/disassembler/disassembler_arm64.cc
@@ -24,6 +24,8 @@
#include "base/stringprintf.h"
#include "thread.h"
+using namespace vixl::aarch64; // NOLINT(build/namespaces)
+
namespace art {
namespace arm64 {
@@ -38,15 +40,14 @@ enum {
LR = 30
};
-void CustomDisassembler::AppendRegisterNameToOutput(
- const vixl::Instruction* instr,
- const vixl::CPURegister& reg) {
+void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr,
+ const CPURegister& reg) {
USE(instr);
if (reg.IsRegister() && reg.Is64Bits()) {
- if (reg.code() == TR) {
+ if (reg.GetCode() == TR) {
AppendToOutput("tr");
return;
- } else if (reg.code() == LR) {
+ } else if (reg.GetCode() == LR) {
AppendToOutput("lr");
return;
}
@@ -56,7 +57,7 @@ void CustomDisassembler::AppendRegisterNameToOutput(
Disassembler::AppendRegisterNameToOutput(instr, reg);
}
-void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) {
+void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) {
Disassembler::VisitLoadLiteral(instr);
if (!read_literals_) {
@@ -66,27 +67,27 @@ void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) {
// Get address of literal. Bail if not within expected buffer range to
// avoid trying to fetch invalid literals (we can encounter this when
// interpreting raw data as instructions).
- void* data_address = instr->LiteralAddress<void*>();
+ void* data_address = instr->GetLiteralAddress<void*>();
if (data_address < base_address_ || data_address >= end_address_) {
AppendToOutput(" (?)");
return;
}
// Output information on literal.
- vixl::Instr op = instr->Mask(vixl::LoadLiteralMask);
+ Instr op = instr->Mask(LoadLiteralMask);
switch (op) {
- case vixl::LDR_w_lit:
- case vixl::LDR_x_lit:
- case vixl::LDRSW_x_lit: {
- int64_t data = op == vixl::LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address)
- : *reinterpret_cast<int32_t*>(data_address);
+ case LDR_w_lit:
+ case LDR_x_lit:
+ case LDRSW_x_lit: {
+ int64_t data = op == LDR_x_lit ? *reinterpret_cast<int64_t*>(data_address)
+ : *reinterpret_cast<int32_t*>(data_address);
AppendToOutput(" (0x%" PRIx64 " / %" PRId64 ")", data, data);
break;
}
- case vixl::LDR_s_lit:
- case vixl::LDR_d_lit: {
- double data = (op == vixl::LDR_s_lit) ? *reinterpret_cast<float*>(data_address)
- : *reinterpret_cast<double*>(data_address);
+ case LDR_s_lit:
+ case LDR_d_lit: {
+ double data = (op == LDR_s_lit) ? *reinterpret_cast<float*>(data_address)
+ : *reinterpret_cast<double*>(data_address);
AppendToOutput(" (%g)", data);
break;
}
@@ -95,11 +96,11 @@ void CustomDisassembler::VisitLoadLiteral(const vixl::Instruction* instr) {
}
}
-void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) {
+void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
Disassembler::VisitLoadStoreUnsignedOffset(instr);
- if (instr->Rn() == TR) {
- int64_t offset = instr->ImmLSUnsigned() << instr->SizeLS();
+ if (instr->GetRn() == TR) {
+ int64_t offset = instr->GetImmLSUnsigned() << instr->GetSizeLS();
std::ostringstream tmp_stream;
Thread::DumpThreadOffset<8>(tmp_stream, static_cast<uint32_t>(offset));
AppendToOutput(" ; %s", tmp_stream.str().c_str());
@@ -107,15 +108,15 @@ void CustomDisassembler::VisitLoadStoreUnsignedOffset(const vixl::Instruction* i
}
size_t DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin) {
- const vixl::Instruction* instr = reinterpret_cast<const vixl::Instruction*>(begin);
+ const Instruction* instr = reinterpret_cast<const Instruction*>(begin);
decoder.Decode(instr);
os << FormatInstructionPointer(begin)
- << StringPrintf(": %08x\t%s\n", instr->InstructionBits(), disasm.GetOutput());
- return vixl::kInstructionSize;
+ << StringPrintf(": %08x\t%s\n", instr->GetInstructionBits(), disasm.GetOutput());
+ return kInstructionSize;
}
void DisassemblerArm64::Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) {
- for (const uint8_t* cur = begin; cur < end; cur += vixl::kInstructionSize) {
+ for (const uint8_t* cur = begin; cur < end; cur += kInstructionSize) {
Dump(os, cur);
}
}
diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h
index a4e5ee8a43..c64d8eaf9d 100644
--- a/disassembler/disassembler_arm64.h
+++ b/disassembler/disassembler_arm64.h
@@ -21,34 +21,35 @@
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wshadow"
-#include "vixl/a64/decoder-a64.h"
-#include "vixl/a64/disasm-a64.h"
+#include "a64/decoder-a64.h"
+#include "a64/disasm-a64.h"
#pragma GCC diagnostic pop
namespace art {
namespace arm64 {
-class CustomDisassembler FINAL : public vixl::Disassembler {
+class CustomDisassembler FINAL : public vixl::aarch64::Disassembler {
public:
explicit CustomDisassembler(DisassemblerOptions* options)
- : vixl::Disassembler(),
+ : vixl::aarch64::Disassembler(),
read_literals_(options->can_read_literals_),
base_address_(options->base_address_),
end_address_(options->end_address_) {
if (!options->absolute_addresses_) {
- MapCodeAddress(0, reinterpret_cast<const vixl::Instruction*>(options->base_address_));
+ MapCodeAddress(0,
+ reinterpret_cast<const vixl::aarch64::Instruction*>(options->base_address_));
}
}
// Use register aliases in the disassembly.
- void AppendRegisterNameToOutput(const vixl::Instruction* instr,
- const vixl::CPURegister& reg) OVERRIDE;
+ void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
+ const vixl::aarch64::CPURegister& reg) OVERRIDE;
// Improve the disassembly of literal load instructions.
- void VisitLoadLiteral(const vixl::Instruction* instr) OVERRIDE;
+ void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE;
// Improve the disassembly of thread offset.
- void VisitLoadStoreUnsignedOffset(const vixl::Instruction* instr) OVERRIDE;
+ void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE;
private:
// Indicate if the disassembler should read data loaded from literal pools.
@@ -75,7 +76,7 @@ class DisassemblerArm64 FINAL : public Disassembler {
void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE;
private:
- vixl::Decoder decoder;
+ vixl::aarch64::Decoder decoder;
CustomDisassembler disasm;
DISALLOW_COPY_AND_ASSIGN(DisassemblerArm64);
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-10-20 04:51:53 +0000