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-rw-r--r--compiler/dex/quick/arm/arm_lir.h9
-rw-r--r--compiler/dex/quick/arm/assemble_arm.cc12
-rw-r--r--compiler/dex/quick/arm/fp_arm.cc19
-rw-r--r--compiler/dex/quick/arm/target_arm.cc49
-rw-r--r--compiler/dex/quick/dex_file_to_method_inliner_map.h4
-rw-r--r--compiler/dex/quick/mips/target_mips.cc30
-rw-r--r--compiler/dex/quick/x86/target_x86.cc7
7 files changed, 83 insertions, 47 deletions
diff --git a/compiler/dex/quick/arm/arm_lir.h b/compiler/dex/quick/arm/arm_lir.h
index 395c78828e..b06ebcf012 100644
--- a/compiler/dex/quick/arm/arm_lir.h
+++ b/compiler/dex/quick/arm/arm_lir.h
@@ -241,7 +241,7 @@ enum ArmOpcode {
kArmFirst = 0,
kArm16BitData = kArmFirst, // DATA [0] rd[15..0].
kThumbAdcRR, // adc [0100000101] rm[5..3] rd[2..0].
- kThumbAddRRI3, // add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0]*/
+ kThumbAddRRI3, // add(1) [0001110] imm_3[8..6] rn[5..3] rd[2..0].
kThumbAddRI8, // add(2) [00110] rd[10..8] imm_8[7..0].
kThumbAddRRR, // add(3) [0001100] rm[8..6] rn[5..3] rd[2..0].
kThumbAddRRLH, // add(4) [01000100] H12[01] rm[5..3] rd[2..0].
@@ -326,20 +326,23 @@ enum ArmOpcode {
kThumb2Vaddd, // vadd vd, vn, vm [111011100011] rn[19..16] rd[15-12] [10110000] rm[3..0].
kThumb2Vdivs, // vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10100000] rm[3..0].
kThumb2Vdivd, // vdiv vd, vn, vm [111011101000] rn[19..16] rd[15-12] [10110000] rm[3..0].
+ kThumb2VmlaF64, // vmla.F64 vd, vn, vm [111011100000] vn[19..16] vd[15..12] [10110000] vm[3..0].
kThumb2VcvtIF, // vcvt.F32 vd, vm [1110111010111000] vd[15..12] [10101100] vm[3..0].
kThumb2VcvtID, // vcvt.F64 vd, vm [1110111010111000] vd[15..12] [10111100] vm[3..0].
kThumb2VcvtFI, // vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10101100] vm[3..0].
kThumb2VcvtDI, // vcvt.S32.F32 vd, vm [1110111010111101] vd[15..12] [10111100] vm[3..0].
kThumb2VcvtFd, // vcvt.F64.F32 vd, vm [1110111010110111] vd[15..12] [10101100] vm[3..0].
kThumb2VcvtDF, // vcvt.F32.F64 vd, vm [1110111010110111] vd[15..12] [10111100] vm[3..0].
+ kThumb2VcvtF64S32, // vcvt.F64.S32 vd, vm [1110111010111000] vd[15..12] [10111100] vm[3..0].
+ kThumb2VcvtF64U32, // vcvt.F64.U32 vd, vm [1110111010111000] vd[15..12] [10110100] vm[3..0].
kThumb2Vsqrts, // vsqrt.f32 vd, vm [1110111010110001] vd[15..12] [10101100] vm[3..0].
kThumb2Vsqrtd, // vsqrt.f64 vd, vm [1110111010110001] vd[15..12] [10111100] vm[3..0].
kThumb2MovI8M, // mov(T2) rd, #<const> [11110] i [00001001111] imm3 rd[11..8] imm8.
kThumb2MovImm16, // mov(T3) rd, #<const> [11110] i [0010100] imm4 [0] imm3 rd[11..8] imm8.
kThumb2StrRRI12, // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0].
kThumb2LdrRRI12, // str(Imm,T3) rd,[rn,#imm12] [111110001100] rn[19..16] rt[15..12] imm12[11..0].
- kThumb2StrRRI8Predec, // str(Imm,T4) rd,[rn,#-imm8] [111110000100] rn[19..16] rt[15..12] [1100] imm[7..0]*/
- kThumb2LdrRRI8Predec, // ldr(Imm,T4) rd,[rn,#-imm8] [111110000101] rn[19..16] rt[15..12] [1100] imm[7..0]*/
+ kThumb2StrRRI8Predec, // str(Imm,T4) rd,[rn,#-imm8] [111110000100] rn[19..16] rt[15..12] [1100] imm[7..0].
+ kThumb2LdrRRI8Predec, // ldr(Imm,T4) rd,[rn,#-imm8] [111110000101] rn[19..16] rt[15..12] [1100] imm[7..0].
kThumb2Cbnz, // cbnz rd,<label> [101110] i [1] imm5[7..3] rn[2..0].
kThumb2Cbz, // cbn rd,<label> [101100] i [1] imm5[7..3] rn[2..0].
kThumb2AddRRI12, // add rd, rn, #imm12 [11110] i [100000] rn[19..16] [0] imm3[14..12] rd[11..8] imm8[7..0].
diff --git a/compiler/dex/quick/arm/assemble_arm.cc b/compiler/dex/quick/arm/assemble_arm.cc
index 820b3aa24e..00939ec98b 100644
--- a/compiler/dex/quick/arm/assemble_arm.cc
+++ b/compiler/dex/quick/arm/assemble_arm.cc
@@ -457,6 +457,10 @@ const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = {
kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0_USE12,
"vdivd", "!0S, !1S, !2S", 4, kFixupNone),
+ ENCODING_MAP(kThumb2VmlaF64, 0xee000b00,
+ kFmtDfp, 22, 12, kFmtDfp, 7, 16, kFmtDfp, 5, 0,
+ kFmtUnused, -1, -1, IS_TERTIARY_OP | REG_DEF0 | REG_USE012,
+ "vmla", "!0S, !1S, !2S", 4, kFixupNone),
ENCODING_MAP(kThumb2VcvtIF, 0xeeb80ac0,
kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
@@ -481,6 +485,14 @@ const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = {
kFmtSfp, 22, 12, kFmtDfp, 5, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
"vcvt.f32.f64 ", "!0s, !1S", 4, kFixupNone),
+ ENCODING_MAP(kThumb2VcvtF64S32, 0xeeb80bc0,
+ kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
+ kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
+ "vcvt.f64.s32 ", "!0S, !1s", 4, kFixupNone),
+ ENCODING_MAP(kThumb2VcvtF64U32, 0xeeb80b40,
+ kFmtDfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
+ kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
+ "vcvt.f64.u32 ", "!0S, !1s", 4, kFixupNone),
ENCODING_MAP(kThumb2Vsqrts, 0xeeb10ac0,
kFmtSfp, 22, 12, kFmtSfp, 5, 0, kFmtUnused, -1, -1,
kFmtUnused, -1, -1, IS_BINARY_OP | REG_DEF0_USE1,
diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc
index 8af9cdd6f5..1a9d9c5e70 100644
--- a/compiler/dex/quick/arm/fp_arm.cc
+++ b/compiler/dex/quick/arm/fp_arm.cc
@@ -141,9 +141,24 @@ void ArmMir2Lir::GenConversion(Instruction::Code opcode,
case Instruction::DOUBLE_TO_INT:
op = kThumb2VcvtDI;
break;
- case Instruction::LONG_TO_DOUBLE:
- GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pL2d), rl_dest, rl_src);
+ case Instruction::LONG_TO_DOUBLE: {
+ rl_src = LoadValueWide(rl_src, kFPReg);
+ src_reg = S2d(rl_src.low_reg, rl_src.high_reg);
+ rl_result = EvalLoc(rl_dest, kFPReg, true);
+ // TODO: clean up AllocTempDouble so that its result has the double bits set.
+ int tmp1 = AllocTempDouble();
+ int tmp2 = AllocTempDouble();
+
+ NewLIR2(kThumb2VcvtF64S32, tmp1 | ARM_FP_DOUBLE, (src_reg & ~ARM_FP_DOUBLE) + 1);
+ NewLIR2(kThumb2VcvtF64U32, S2d(rl_result.low_reg, rl_result.high_reg), (src_reg & ~ARM_FP_DOUBLE));
+ LoadConstantWide(tmp2, tmp2 + 1, 0x41f0000000000000LL);
+ NewLIR3(kThumb2VmlaF64, S2d(rl_result.low_reg, rl_result.high_reg), tmp1 | ARM_FP_DOUBLE,
+ tmp2 | ARM_FP_DOUBLE);
+ FreeTemp(tmp1);
+ FreeTemp(tmp2);
+ StoreValueWide(rl_dest, rl_result);
return;
+ }
case Instruction::FLOAT_TO_LONG:
GenConversionCall(QUICK_ENTRYPOINT_OFFSET(pF2l), rl_dest, rl_src);
return;
diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc
index d80ae3bc23..759104150d 100644
--- a/compiler/dex/quick/arm/target_arm.cc
+++ b/compiler/dex/quick/arm/target_arm.cc
@@ -255,7 +255,7 @@ static const char* shift_names[4] = {
"ror"};
/* Decode and print a ARM register name */
-static char* DecodeRegList(int opcode, int vector, char* buf) {
+static char* DecodeRegList(int opcode, int vector, char* buf, size_t buf_size) {
int i;
bool printed = false;
buf[0] = 0;
@@ -268,20 +268,20 @@ static char* DecodeRegList(int opcode, int vector, char* buf) {
reg_id = r15pc;
}
if (printed) {
- sprintf(buf + strlen(buf), ", r%d", reg_id);
+ snprintf(buf + strlen(buf), buf_size - strlen(buf), ", r%d", reg_id);
} else {
printed = true;
- sprintf(buf, "r%d", reg_id);
+ snprintf(buf, buf_size, "r%d", reg_id);
}
}
}
return buf;
}
-static char* DecodeFPCSRegList(int count, int base, char* buf) {
- sprintf(buf, "s%d", base);
+static char* DecodeFPCSRegList(int count, int base, char* buf, size_t buf_size) {
+ snprintf(buf, buf_size, "s%d", base);
for (int i = 1; i < count; i++) {
- sprintf(buf + strlen(buf), ", s%d", base + i);
+ snprintf(buf + strlen(buf), buf_size - strlen(buf), ", s%d", base + i);
}
return buf;
}
@@ -333,7 +333,7 @@ std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char
switch (*fmt++) {
case 'H':
if (operand != 0) {
- sprintf(tbuf, ", %s %d", shift_names[operand & 0x3], operand >> 2);
+ snprintf(tbuf, arraysize(tbuf), ", %s %d", shift_names[operand & 0x3], operand >> 2);
} else {
strcpy(tbuf, "");
}
@@ -373,41 +373,41 @@ std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char
break;
case 'n':
operand = ~ExpandImmediate(operand);
- sprintf(tbuf, "%d [%#x]", operand, operand);
+ snprintf(tbuf, arraysize(tbuf), "%d [%#x]", operand, operand);
break;
case 'm':
operand = ExpandImmediate(operand);
- sprintf(tbuf, "%d [%#x]", operand, operand);
+ snprintf(tbuf, arraysize(tbuf), "%d [%#x]", operand, operand);
break;
case 's':
- sprintf(tbuf, "s%d", operand & ARM_FP_REG_MASK);
+ snprintf(tbuf, arraysize(tbuf), "s%d", operand & ARM_FP_REG_MASK);
break;
case 'S':
- sprintf(tbuf, "d%d", (operand & ARM_FP_REG_MASK) >> 1);
+ snprintf(tbuf, arraysize(tbuf), "d%d", (operand & ARM_FP_REG_MASK) >> 1);
break;
case 'h':
- sprintf(tbuf, "%04x", operand);
+ snprintf(tbuf, arraysize(tbuf), "%04x", operand);
break;
case 'M':
case 'd':
- sprintf(tbuf, "%d", operand);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand);
break;
case 'C':
DCHECK_LT(operand, static_cast<int>(
sizeof(core_reg_names)/sizeof(core_reg_names[0])));
- sprintf(tbuf, "%s", core_reg_names[operand]);
+ snprintf(tbuf, arraysize(tbuf), "%s", core_reg_names[operand]);
break;
case 'E':
- sprintf(tbuf, "%d", operand*4);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand*4);
break;
case 'F':
- sprintf(tbuf, "%d", operand*2);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand*2);
break;
case 'c':
strcpy(tbuf, cc_names[operand]);
break;
case 't':
- sprintf(tbuf, "0x%08x (L%p)",
+ snprintf(tbuf, arraysize(tbuf), "0x%08x (L%p)",
reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 +
(operand << 1),
lir->target);
@@ -419,7 +419,7 @@ std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char
(((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) &
~3) + (offset_1 << 21 >> 9) + (offset_2 << 1)) &
0xfffffffc;
- sprintf(tbuf, "%p", reinterpret_cast<void *>(target));
+ snprintf(tbuf, arraysize(tbuf), "%p", reinterpret_cast<void *>(target));
break;
}
@@ -428,13 +428,13 @@ std::string ArmMir2Lir::BuildInsnString(const char* fmt, LIR* lir, unsigned char
strcpy(tbuf, "see above");
break;
case 'R':
- DecodeRegList(lir->opcode, operand, tbuf);
+ DecodeRegList(lir->opcode, operand, tbuf, arraysize(tbuf));
break;
case 'P':
- DecodeFPCSRegList(operand, 16, tbuf);
+ DecodeFPCSRegList(operand, 16, tbuf, arraysize(tbuf));
break;
case 'Q':
- DecodeFPCSRegList(operand, 0, tbuf);
+ DecodeFPCSRegList(operand, 0, tbuf, arraysize(tbuf));
break;
default:
strcpy(tbuf, "DecodeError1");
@@ -461,7 +461,7 @@ void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefi
for (i = 0; i < kArmRegEnd; i++) {
if (mask & (1ULL << i)) {
- sprintf(num, "%d ", i);
+ snprintf(num, arraysize(num), "%d ", i);
strcat(buf, num);
}
}
@@ -475,8 +475,9 @@ void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, uint64_t mask, const char* prefi
/* Memory bits */
if (arm_lir && (mask & ENCODE_DALVIK_REG)) {
- sprintf(buf + strlen(buf), "dr%d%s", DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info),
- DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : "");
+ snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
+ DECODE_ALIAS_INFO_REG(arm_lir->flags.alias_info),
+ DECODE_ALIAS_INFO_WIDE(arm_lir->flags.alias_info) ? "(+1)" : "");
}
if (mask & ENCODE_LITERAL) {
strcat(buf, "lit ");
diff --git a/compiler/dex/quick/dex_file_to_method_inliner_map.h b/compiler/dex/quick/dex_file_to_method_inliner_map.h
index 6d5b8893c5..215dc12b26 100644
--- a/compiler/dex/quick/dex_file_to_method_inliner_map.h
+++ b/compiler/dex/quick/dex_file_to_method_inliner_map.h
@@ -40,7 +40,9 @@ class DexFileToMethodInlinerMap {
DexFileToMethodInlinerMap();
~DexFileToMethodInlinerMap();
- DexFileMethodInliner* GetMethodInliner(const DexFile* dex_file) LOCKS_EXCLUDED(lock_);
+ DexFileMethodInliner* GetMethodInliner(const DexFile* dex_file) NO_THREAD_SAFETY_ANALYSIS;
+ // TODO: There is an irregular non-scoped use of locks that defeats annotalysis with -O0.
+ // Fix the NO_THREAD_SAFETY_ANALYSIS when this works and add the appropriate LOCKS_EXCLUDED.
private:
ReaderWriterMutex lock_;
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc
index 869706fbe0..1aee06c89a 100644
--- a/compiler/dex/quick/mips/target_mips.cc
+++ b/compiler/dex/quick/mips/target_mips.cc
@@ -180,34 +180,35 @@ std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned cha
}
break;
case 's':
- sprintf(tbuf, "$f%d", operand & MIPS_FP_REG_MASK);
+ snprintf(tbuf, arraysize(tbuf), "$f%d", operand & MIPS_FP_REG_MASK);
break;
case 'S':
DCHECK_EQ(((operand & MIPS_FP_REG_MASK) & 1), 0);
- sprintf(tbuf, "$f%d", operand & MIPS_FP_REG_MASK);
+ snprintf(tbuf, arraysize(tbuf), "$f%d", operand & MIPS_FP_REG_MASK);
break;
case 'h':
- sprintf(tbuf, "%04x", operand);
+ snprintf(tbuf, arraysize(tbuf), "%04x", operand);
break;
case 'M':
case 'd':
- sprintf(tbuf, "%d", operand);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand);
break;
case 'D':
- sprintf(tbuf, "%d", operand+1);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand+1);
break;
case 'E':
- sprintf(tbuf, "%d", operand*4);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand*4);
break;
case 'F':
- sprintf(tbuf, "%d", operand*2);
+ snprintf(tbuf, arraysize(tbuf), "%d", operand*2);
break;
case 't':
- sprintf(tbuf, "0x%08x (L%p)", reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 +
- (operand << 2), lir->target);
+ snprintf(tbuf, arraysize(tbuf), "0x%08x (L%p)",
+ reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4 + (operand << 2),
+ lir->target);
break;
case 'T':
- sprintf(tbuf, "0x%08x", operand << 2);
+ snprintf(tbuf, arraysize(tbuf), "0x%08x", operand << 2);
break;
case 'u': {
int offset_1 = lir->operands[0];
@@ -215,7 +216,7 @@ std::string MipsMir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned cha
uintptr_t target =
(((reinterpret_cast<uintptr_t>(base_addr) + lir->offset + 4) & ~3) +
(offset_1 << 21 >> 9) + (offset_2 << 1)) & 0xfffffffc;
- sprintf(tbuf, "%p", reinterpret_cast<void*>(target));
+ snprintf(tbuf, arraysize(tbuf), "%p", reinterpret_cast<void*>(target));
break;
}
@@ -257,7 +258,7 @@ void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *pre
for (i = 0; i < kMipsRegEnd; i++) {
if (mask & (1ULL << i)) {
- sprintf(num, "%d ", i);
+ snprintf(num, arraysize(num), "%d ", i);
strcat(buf, num);
}
}
@@ -270,8 +271,9 @@ void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, uint64_t mask, const char *pre
}
/* Memory bits */
if (mips_lir && (mask & ENCODE_DALVIK_REG)) {
- sprintf(buf + strlen(buf), "dr%d%s", DECODE_ALIAS_INFO_REG(mips_lir->flags.alias_info),
- DECODE_ALIAS_INFO_WIDE(mips_lir->flags.alias_info) ? "(+1)" : "");
+ snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
+ DECODE_ALIAS_INFO_REG(mips_lir->flags.alias_info),
+ DECODE_ALIAS_INFO_WIDE(mips_lir->flags.alias_info) ? "(+1)" : "");
}
if (mask & ENCODE_LITERAL) {
strcat(buf, "lit ");
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 0b8c07e3cc..b281063a4a 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -270,7 +270,7 @@ void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix
for (i = 0; i < kX86RegEnd; i++) {
if (mask & (1ULL << i)) {
- sprintf(num, "%d ", i);
+ snprintf(num, arraysize(num), "%d ", i);
strcat(buf, num);
}
}
@@ -280,8 +280,9 @@ void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix
}
/* Memory bits */
if (x86LIR && (mask & ENCODE_DALVIK_REG)) {
- sprintf(buf + strlen(buf), "dr%d%s", DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info),
- (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : "");
+ snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s",
+ DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info),
+ (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : "");
}
if (mask & ENCODE_LITERAL) {
strcat(buf, "lit ");
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-28 16:57:42 +0000