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-rw-r--r--compiler/utils/mips64/assembler_mips64.cc68
-rw-r--r--compiler/utils/mips64/assembler_mips64.h112
2 files changed, 58 insertions, 122 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index 00e8995bff..8e9b509e30 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -117,14 +117,6 @@ void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister ft, uint16_t imm)
Emit(encoding);
}
-void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- EmitR(0, rs, rt, rd, 0, 0x20);
-}
-
-void Mips64Assembler::Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
- EmitI(0x8, rs, rt, imm16);
-}
-
void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x21);
}
@@ -141,10 +133,6 @@ void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x19, rs, rt, imm16);
}
-void Mips64Assembler::Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- EmitR(0, rs, rt, rd, 0, 0x22);
-}
-
void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x23);
}
@@ -153,50 +141,14 @@ void Mips64Assembler::Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 0, 0x2f);
}
-void Mips64Assembler::MultR2(GpuRegister rs, GpuRegister rt) {
- EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x18);
-}
-
-void Mips64Assembler::MultuR2(GpuRegister rs, GpuRegister rt) {
- EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x19);
-}
-
-void Mips64Assembler::DivR2(GpuRegister rs, GpuRegister rt) {
- EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1a);
-}
-
-void Mips64Assembler::DivuR2(GpuRegister rs, GpuRegister rt) {
- EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1b);
-}
-
-void Mips64Assembler::MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- EmitR(0x1c, rs, rt, rd, 0, 2);
-}
-
-void Mips64Assembler::DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- DivR2(rs, rt);
- Mflo(rd);
-}
-
-void Mips64Assembler::ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- DivR2(rs, rt);
- Mfhi(rd);
-}
-
-void Mips64Assembler::DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- DivuR2(rs, rt);
- Mflo(rd);
-}
-
-void Mips64Assembler::ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
- DivuR2(rs, rt);
- Mfhi(rd);
-}
-
void Mips64Assembler::MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x18);
}
+void Mips64Assembler::MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
+ EmitR(0, rs, rt, rd, 3, 0x18);
+}
+
void Mips64Assembler::DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1a);
}
@@ -217,6 +169,10 @@ void Mips64Assembler::Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1c);
}
+void Mips64Assembler::Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
+ EmitR(0, rs, rt, rd, 3, 0x1c);
+}
+
void Mips64Assembler::Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt) {
EmitR(0, rs, rt, rd, 2, 0x1e);
}
@@ -440,14 +396,6 @@ void Mips64Assembler::Sync(uint32_t stype) {
static_cast<GpuRegister>(0), stype & 0x1f, 0xf);
}
-void Mips64Assembler::Mfhi(GpuRegister rd) {
- EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x10);
-}
-
-void Mips64Assembler::Mflo(GpuRegister rd) {
- EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x12);
-}
-
void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) {
EmitI(0x28, rs, rt, imm16);
}
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index 33f22d2c2d..42962bca20 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -66,35 +66,25 @@ class Mips64Assembler FINAL : public Assembler {
virtual ~Mips64Assembler() {}
// Emit Machine Instructions.
- void Add(GpuRegister rd, GpuRegister rs, GpuRegister rt);
- void Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
void Daddu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
- void Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt);
void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt);
void Dsubu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
- void MultR2(GpuRegister rs, GpuRegister rt); // R2
- void MultuR2(GpuRegister rs, GpuRegister rt); // R2
- void DivR2(GpuRegister rs, GpuRegister rt); // R2
- void DivuR2(GpuRegister rs, GpuRegister rt); // R2
- void MulR2(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R2
- void DivR2(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R2
- void ModR2(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R2
- void DivuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R2
- void ModuR2(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R2
- void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R6
- void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R6
- void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R6
- void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R6
- void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt); // R6
- void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 R6
- void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 R6
- void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 R6
- void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 R6
- void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64 R6
+ void MulR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+ void MuhR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+ void DivR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+ void ModR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+ void DivuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+ void ModuR6(GpuRegister rd, GpuRegister rs, GpuRegister rt);
+ void Dmul(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
+ void Dmuh(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
+ void Ddiv(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
+ void Dmod(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
+ void Ddivu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
+ void Dmodu(GpuRegister rd, GpuRegister rs, GpuRegister rt); // MIPS64
void And(GpuRegister rd, GpuRegister rs, GpuRegister rt);
void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16);
@@ -104,12 +94,12 @@ class Mips64Assembler FINAL : public Assembler {
void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16);
void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt);
- void Bitswap(GpuRegister rd, GpuRegister rt); // R6
- void Dbitswap(GpuRegister rd, GpuRegister rt); // R6
- void Seb(GpuRegister rd, GpuRegister rt); // R2+
- void Seh(GpuRegister rd, GpuRegister rt); // R2+
- void Dsbh(GpuRegister rd, GpuRegister rt); // R2+
- void Dshd(GpuRegister rd, GpuRegister rt); // R2+
+ void Bitswap(GpuRegister rd, GpuRegister rt);
+ void Dbitswap(GpuRegister rd, GpuRegister rt);
+ void Seb(GpuRegister rd, GpuRegister rt);
+ void Seh(GpuRegister rd, GpuRegister rt);
+ void Dsbh(GpuRegister rd, GpuRegister rt);
+ void Dshd(GpuRegister rd, GpuRegister rt);
void Dext(GpuRegister rs, GpuRegister rt, int pos, int size_less_one); // MIPS64
void Wsbh(GpuRegister rd, GpuRegister rt);
void Sc(GpuRegister rt, GpuRegister base, int16_t imm9 = 0);
@@ -146,11 +136,9 @@ class Mips64Assembler FINAL : public Assembler {
void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16);
void Lwu(GpuRegister rt, GpuRegister rs, uint16_t imm16); // MIPS64
void Lui(GpuRegister rt, uint16_t imm16);
- void Dahi(GpuRegister rs, uint16_t imm16); // MIPS64 R6
- void Dati(GpuRegister rs, uint16_t imm16); // MIPS64 R6
+ void Dahi(GpuRegister rs, uint16_t imm16); // MIPS64
+ void Dati(GpuRegister rs, uint16_t imm16); // MIPS64
void Sync(uint32_t stype);
- void Mfhi(GpuRegister rd); // R2
- void Mflo(GpuRegister rd); // R2
void Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16);
void Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16);
@@ -175,21 +163,21 @@ class Mips64Assembler FINAL : public Assembler {
void Jalr(GpuRegister rd, GpuRegister rs);
void Jalr(GpuRegister rs);
void Jr(GpuRegister rs);
- void Auipc(GpuRegister rs, uint16_t imm16); // R6
- void Jic(GpuRegister rt, uint16_t imm16); // R6
- void Jialc(GpuRegister rt, uint16_t imm16); // R6
- void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R6
- void Bltzc(GpuRegister rt, uint16_t imm16); // R6
- void Bgtzc(GpuRegister rt, uint16_t imm16); // R6
- void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R6
- void Bgezc(GpuRegister rt, uint16_t imm16); // R6
- void Blezc(GpuRegister rt, uint16_t imm16); // R6
- void Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R6
- void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R6
- void Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R6
- void Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16); // R6
- void Beqzc(GpuRegister rs, uint32_t imm21); // R6
- void Bnezc(GpuRegister rs, uint32_t imm21); // R6
+ void Auipc(GpuRegister rs, uint16_t imm16);
+ void Jic(GpuRegister rt, uint16_t imm16);
+ void Jialc(GpuRegister rt, uint16_t imm16);
+ void Bltc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
+ void Bltzc(GpuRegister rt, uint16_t imm16);
+ void Bgtzc(GpuRegister rt, uint16_t imm16);
+ void Bgec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
+ void Bgezc(GpuRegister rt, uint16_t imm16);
+ void Blezc(GpuRegister rt, uint16_t imm16);
+ void Bltuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
+ void Bgeuc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
+ void Beqc(GpuRegister rs, GpuRegister rt, uint16_t imm16);
+ void Bnec(GpuRegister rs, GpuRegister rt, uint16_t imm16);
+ void Beqzc(GpuRegister rs, uint32_t imm21);
+ void Bnezc(GpuRegister rs, uint32_t imm21);
void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
@@ -259,25 +247,25 @@ class Mips64Assembler FINAL : public Assembler {
void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value, GpuRegister rtmp = AT);
void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64
- void Bind(Label* label) OVERRIDE; // R6
+ void Bind(Label* label) OVERRIDE;
void Jump(Label* label) OVERRIDE {
B(label);
}
- void B(Label* label); // R6
- void Jalr(Label* label, GpuRegister indirect_reg = RA); // R6
+ void B(Label* label);
+ void Jalr(Label* label, GpuRegister indirect_reg = RA);
// TODO: implement common for R6 and non-R6 interface for conditional branches?
- void Bltc(GpuRegister rs, GpuRegister rt, Label* label); // R6
- void Bltzc(GpuRegister rt, Label* label); // R6
- void Bgtzc(GpuRegister rt, Label* label); // R6
- void Bgec(GpuRegister rs, GpuRegister rt, Label* label); // R6
- void Bgezc(GpuRegister rt, Label* label); // R6
- void Blezc(GpuRegister rt, Label* label); // R6
- void Bltuc(GpuRegister rs, GpuRegister rt, Label* label); // R6
- void Bgeuc(GpuRegister rs, GpuRegister rt, Label* label); // R6
- void Beqc(GpuRegister rs, GpuRegister rt, Label* label); // R6
- void Bnec(GpuRegister rs, GpuRegister rt, Label* label); // R6
- void Beqzc(GpuRegister rs, Label* label); // R6
- void Bnezc(GpuRegister rs, Label* label); // R6
+ void Bltc(GpuRegister rs, GpuRegister rt, Label* label);
+ void Bltzc(GpuRegister rt, Label* label);
+ void Bgtzc(GpuRegister rt, Label* label);
+ void Bgec(GpuRegister rs, GpuRegister rt, Label* label);
+ void Bgezc(GpuRegister rt, Label* label);
+ void Blezc(GpuRegister rt, Label* label);
+ void Bltuc(GpuRegister rs, GpuRegister rt, Label* label);
+ void Bgeuc(GpuRegister rs, GpuRegister rt, Label* label);
+ void Beqc(GpuRegister rs, GpuRegister rt, Label* label);
+ void Bnec(GpuRegister rs, GpuRegister rt, Label* label);
+ void Beqzc(GpuRegister rs, Label* label);
+ void Bnezc(GpuRegister rs, Label* label);
void EmitLoad(ManagedRegister m_dst, GpuRegister src_register, int32_t src_offset, size_t size);
void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset);
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