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-rw-r--r--compiler/utils/arm/assembler_arm.h9
-rw-r--r--compiler/utils/arm/assembler_arm32.cc14
-rw-r--r--compiler/utils/arm/assembler_arm32.h4
-rw-r--r--compiler/utils/arm/assembler_thumb2.cc13
-rw-r--r--compiler/utils/arm/assembler_thumb2.h5
-rw-r--r--compiler/utils/arm/constants_arm.h3
-rw-r--r--compiler/utils/assembler_thumb_test.cc3
-rw-r--r--compiler/utils/assembler_thumb_test_expected.cc.inc241
-rw-r--r--compiler/utils/x86_64/assembler_x86_64.cc21
-rw-r--r--compiler/utils/x86_64/assembler_x86_64.h69
10 files changed, 227 insertions, 155 deletions
diff --git a/compiler/utils/arm/assembler_arm.h b/compiler/utils/arm/assembler_arm.h
index 967b191d32..d59bc6be40 100644
--- a/compiler/utils/arm/assembler_arm.h
+++ b/compiler/utils/arm/assembler_arm.h
@@ -470,6 +470,13 @@ class ArmAssembler : public Assembler {
orr(rd, rn, so, cond, kCcSet);
}
+ virtual void orn(Register rd, Register rn, const ShifterOperand& so,
+ Condition cond = AL, SetCc set_cc = kCcDontCare) = 0;
+
+ virtual void orns(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) {
+ orn(rd, rn, so, cond, kCcSet);
+ }
+
virtual void mov(Register rd, const ShifterOperand& so,
Condition cond = AL, SetCc set_cc = kCcDontCare) = 0;
@@ -832,6 +839,8 @@ class ArmAssembler : public Assembler {
uint32_t immediate,
ShifterOperand* shifter_op) = 0;
+ virtual bool ShifterOperandCanAlwaysHold(uint32_t immediate) = 0;
+
static bool IsInstructionForExceptionHandling(uintptr_t pc);
virtual void CompareAndBranchIfZero(Register r, Label* label) = 0;
diff --git a/compiler/utils/arm/assembler_arm32.cc b/compiler/utils/arm/assembler_arm32.cc
index f7772aea3d..6e7c828b4a 100644
--- a/compiler/utils/arm/assembler_arm32.cc
+++ b/compiler/utils/arm/assembler_arm32.cc
@@ -48,6 +48,11 @@ bool Arm32Assembler::ShifterOperandCanHoldArm32(uint32_t immediate, ShifterOpera
return false;
}
+bool Arm32Assembler::ShifterOperandCanAlwaysHold(uint32_t immediate) {
+ ShifterOperand shifter_op;
+ return ShifterOperandCanHoldArm32(immediate, &shifter_op);
+}
+
bool Arm32Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
Register rn ATTRIBUTE_UNUSED,
Opcode opcode ATTRIBUTE_UNUSED,
@@ -130,6 +135,15 @@ void Arm32Assembler::orr(Register rd, Register rn, const ShifterOperand& so,
}
+void Arm32Assembler::orn(Register rd ATTRIBUTE_UNUSED,
+ Register rn ATTRIBUTE_UNUSED,
+ const ShifterOperand& so ATTRIBUTE_UNUSED,
+ Condition cond ATTRIBUTE_UNUSED,
+ SetCc set_cc ATTRIBUTE_UNUSED) {
+ LOG(FATAL) << "orn is not supported on ARM32";
+}
+
+
void Arm32Assembler::mov(Register rd, const ShifterOperand& so,
Condition cond, SetCc set_cc) {
EmitType01(cond, so.type(), MOV, set_cc, R0, rd, so);
diff --git a/compiler/utils/arm/assembler_arm32.h b/compiler/utils/arm/assembler_arm32.h
index 3407369654..4646538716 100644
--- a/compiler/utils/arm/assembler_arm32.h
+++ b/compiler/utils/arm/assembler_arm32.h
@@ -74,6 +74,9 @@ class Arm32Assembler FINAL : public ArmAssembler {
virtual void orr(Register rd, Register rn, const ShifterOperand& so,
Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
+ virtual void orn(Register rd, Register rn, const ShifterOperand& so,
+ Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
+
virtual void mov(Register rd, const ShifterOperand& so,
Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
@@ -294,6 +297,7 @@ class Arm32Assembler FINAL : public ArmAssembler {
uint32_t immediate,
ShifterOperand* shifter_op) OVERRIDE;
+ bool ShifterOperandCanAlwaysHold(uint32_t immediate) OVERRIDE;
static bool IsInstructionForExceptionHandling(uintptr_t pc);
diff --git a/compiler/utils/arm/assembler_thumb2.cc b/compiler/utils/arm/assembler_thumb2.cc
index 0f6c4f5a34..cc87856e82 100644
--- a/compiler/utils/arm/assembler_thumb2.cc
+++ b/compiler/utils/arm/assembler_thumb2.cc
@@ -390,6 +390,10 @@ void Thumb2Assembler::FinalizeCode() {
EmitLiterals();
}
+bool Thumb2Assembler::ShifterOperandCanAlwaysHold(uint32_t immediate) {
+ return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
+}
+
bool Thumb2Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
Register rn ATTRIBUTE_UNUSED,
Opcode opcode,
@@ -410,6 +414,7 @@ bool Thumb2Assembler::ShifterOperandCanHold(Register rd ATTRIBUTE_UNUSED,
case MOV:
// TODO: Support less than or equal to 12bits.
return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
+
case MVN:
default:
return ArmAssembler::ModifiedImmediate(immediate) != kInvalidModifiedImmediate;
@@ -492,6 +497,12 @@ void Thumb2Assembler::orr(Register rd, Register rn, const ShifterOperand& so,
}
+void Thumb2Assembler::orn(Register rd, Register rn, const ShifterOperand& so,
+ Condition cond, SetCc set_cc) {
+ EmitDataProcessing(cond, ORN, set_cc, rn, rd, so);
+}
+
+
void Thumb2Assembler::mov(Register rd, const ShifterOperand& so,
Condition cond, SetCc set_cc) {
EmitDataProcessing(cond, MOV, set_cc, R0, rd, so);
@@ -1105,6 +1116,7 @@ bool Thumb2Assembler::Is32BitDataProcessing(Condition cond,
rn_is_valid = false; // There is no Rn for these instructions.
break;
case TEQ:
+ case ORN:
return true;
case ADD:
case SUB:
@@ -1222,6 +1234,7 @@ void Thumb2Assembler::Emit32BitDataProcessing(Condition cond ATTRIBUTE_UNUSED,
case MOV: thumb_opcode = 2U /* 0b0010 */; rn = PC; break;
case BIC: thumb_opcode = 1U /* 0b0001 */; break;
case MVN: thumb_opcode = 3U /* 0b0011 */; rn = PC; break;
+ case ORN: thumb_opcode = 3U /* 0b0011 */; break;
default:
break;
}
diff --git a/compiler/utils/arm/assembler_thumb2.h b/compiler/utils/arm/assembler_thumb2.h
index a1a8927f44..055b1379ad 100644
--- a/compiler/utils/arm/assembler_thumb2.h
+++ b/compiler/utils/arm/assembler_thumb2.h
@@ -98,6 +98,9 @@ class Thumb2Assembler FINAL : public ArmAssembler {
virtual void orr(Register rd, Register rn, const ShifterOperand& so,
Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
+ virtual void orn(Register rd, Register rn, const ShifterOperand& so,
+ Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
+
virtual void mov(Register rd, const ShifterOperand& so,
Condition cond = AL, SetCc set_cc = kCcDontCare) OVERRIDE;
@@ -337,6 +340,8 @@ class Thumb2Assembler FINAL : public ArmAssembler {
uint32_t immediate,
ShifterOperand* shifter_op) OVERRIDE;
+ bool ShifterOperandCanAlwaysHold(uint32_t immediate) OVERRIDE;
+
static bool IsInstructionForExceptionHandling(uintptr_t pc);
diff --git a/compiler/utils/arm/constants_arm.h b/compiler/utils/arm/constants_arm.h
index 6b4daed909..2060064423 100644
--- a/compiler/utils/arm/constants_arm.h
+++ b/compiler/utils/arm/constants_arm.h
@@ -148,7 +148,8 @@ enum Opcode {
MOV = 13, // Move
BIC = 14, // Bit Clear
MVN = 15, // Move Not
- kMaxOperand = 16
+ ORN = 16, // Logical OR NOT.
+ kMaxOperand = 17
};
std::ostream& operator<<(std::ostream& os, const Opcode& rhs);
diff --git a/compiler/utils/assembler_thumb_test.cc b/compiler/utils/assembler_thumb_test.cc
index b2a354b63c..2ae88413e7 100644
--- a/compiler/utils/assembler_thumb_test.cc
+++ b/compiler/utils/assembler_thumb_test.cc
@@ -238,6 +238,7 @@ TEST(Thumb2AssemblerTest, DataProcessingRegister) {
__ sub(R0, R1, ShifterOperand(R2), AL, kCcKeep);
__ and_(R0, R1, ShifterOperand(R2), AL, kCcKeep);
__ orr(R0, R1, ShifterOperand(R2), AL, kCcKeep);
+ __ orn(R0, R1, ShifterOperand(R2), AL, kCcKeep);
__ eor(R0, R1, ShifterOperand(R2), AL, kCcKeep);
__ bic(R0, R1, ShifterOperand(R2), AL, kCcKeep);
__ adc(R0, R1, ShifterOperand(R2), AL, kCcKeep);
@@ -371,6 +372,7 @@ TEST(Thumb2AssemblerTest, DataProcessingImmediate) {
__ sub(R0, R1, ShifterOperand(0x55));
__ and_(R0, R1, ShifterOperand(0x55));
__ orr(R0, R1, ShifterOperand(0x55));
+ __ orn(R0, R1, ShifterOperand(0x55));
__ eor(R0, R1, ShifterOperand(0x55));
__ bic(R0, R1, ShifterOperand(0x55));
__ adc(R0, R1, ShifterOperand(0x55));
@@ -403,6 +405,7 @@ TEST(Thumb2AssemblerTest, DataProcessingModifiedImmediate) {
__ sub(R0, R1, ShifterOperand(0x550055));
__ and_(R0, R1, ShifterOperand(0x550055));
__ orr(R0, R1, ShifterOperand(0x550055));
+ __ orn(R0, R1, ShifterOperand(0x550055));
__ eor(R0, R1, ShifterOperand(0x550055));
__ bic(R0, R1, ShifterOperand(0x550055));
__ adc(R0, R1, ShifterOperand(0x550055));
diff --git a/compiler/utils/assembler_thumb_test_expected.cc.inc b/compiler/utils/assembler_thumb_test_expected.cc.inc
index 82ad6429bf..b79c2e46f0 100644
--- a/compiler/utils/assembler_thumb_test_expected.cc.inc
+++ b/compiler/utils/assembler_thumb_test_expected.cc.inc
@@ -23,109 +23,110 @@ const char* DataProcessingRegisterResults[] = {
" 8: eba1 0002 sub.w r0, r1, r2\n",
" c: ea01 0002 and.w r0, r1, r2\n",
" 10: ea41 0002 orr.w r0, r1, r2\n",
- " 14: ea81 0002 eor.w r0, r1, r2\n",
- " 18: ea21 0002 bic.w r0, r1, r2\n",
- " 1c: eb41 0002 adc.w r0, r1, r2\n",
- " 20: eb61 0002 sbc.w r0, r1, r2\n",
- " 24: ebc1 0002 rsb r0, r1, r2\n",
- " 28: ea90 0f01 teq r0, r1\n",
- " 2c: 0008 movs r0, r1\n",
- " 2e: 4608 mov r0, r1\n",
- " 30: 43c8 mvns r0, r1\n",
- " 32: 4408 add r0, r1\n",
- " 34: 1888 adds r0, r1, r2\n",
- " 36: 1a88 subs r0, r1, r2\n",
- " 38: 4148 adcs r0, r1\n",
- " 3a: 4188 sbcs r0, r1\n",
- " 3c: 4008 ands r0, r1\n",
- " 3e: 4308 orrs r0, r1\n",
- " 40: 4048 eors r0, r1\n",
- " 42: 4388 bics r0, r1\n",
- " 44: 4208 tst r0, r1\n",
- " 46: 4288 cmp r0, r1\n",
- " 48: 42c8 cmn r0, r1\n",
- " 4a: 4641 mov r1, r8\n",
- " 4c: 4681 mov r9, r0\n",
- " 4e: 46c8 mov r8, r9\n",
- " 50: 4441 add r1, r8\n",
- " 52: 4481 add r9, r0\n",
- " 54: 44c8 add r8, r9\n",
- " 56: 4548 cmp r0, r9\n",
- " 58: 4588 cmp r8, r1\n",
- " 5a: 45c1 cmp r9, r8\n",
- " 5c: 4248 negs r0, r1\n",
- " 5e: 4240 negs r0, r0\n",
- " 60: ea5f 0008 movs.w r0, r8\n",
- " 64: ea7f 0008 mvns.w r0, r8\n",
- " 68: eb01 0008 add.w r0, r1, r8\n",
- " 6c: eb11 0008 adds.w r0, r1, r8\n",
- " 70: ebb1 0008 subs.w r0, r1, r8\n",
- " 74: eb50 0008 adcs.w r0, r0, r8\n",
- " 78: eb70 0008 sbcs.w r0, r0, r8\n",
- " 7c: ea10 0008 ands.w r0, r0, r8\n",
- " 80: ea50 0008 orrs.w r0, r0, r8\n",
- " 84: ea90 0008 eors.w r0, r0, r8\n",
- " 88: ea30 0008 bics.w r0, r0, r8\n",
- " 8c: ea10 0f08 tst.w r0, r8\n",
- " 90: eb10 0f08 cmn.w r0, r8\n",
- " 94: f1d8 0000 rsbs r0, r8, #0\n",
- " 98: f1d8 0800 rsbs r8, r8, #0\n",
- " 9c: bf08 it eq\n",
- " 9e: ea7f 0001 mvnseq.w r0, r1\n",
- " a2: bf08 it eq\n",
- " a4: eb11 0002 addseq.w r0, r1, r2\n",
- " a8: bf08 it eq\n",
- " aa: ebb1 0002 subseq.w r0, r1, r2\n",
- " ae: bf08 it eq\n",
- " b0: eb50 0001 adcseq.w r0, r0, r1\n",
- " b4: bf08 it eq\n",
- " b6: eb70 0001 sbcseq.w r0, r0, r1\n",
- " ba: bf08 it eq\n",
- " bc: ea10 0001 andseq.w r0, r0, r1\n",
- " c0: bf08 it eq\n",
- " c2: ea50 0001 orrseq.w r0, r0, r1\n",
- " c6: bf08 it eq\n",
- " c8: ea90 0001 eorseq.w r0, r0, r1\n",
- " cc: bf08 it eq\n",
- " ce: ea30 0001 bicseq.w r0, r0, r1\n",
- " d2: bf08 it eq\n",
- " d4: 43c8 mvneq r0, r1\n",
+ " 14: ea61 0002 orn r0, r1, r2\n",
+ " 18: ea81 0002 eor.w r0, r1, r2\n",
+ " 1c: ea21 0002 bic.w r0, r1, r2\n",
+ " 20: eb41 0002 adc.w r0, r1, r2\n",
+ " 24: eb61 0002 sbc.w r0, r1, r2\n",
+ " 28: ebc1 0002 rsb r0, r1, r2\n",
+ " 2c: ea90 0f01 teq r0, r1\n",
+ " 30: 0008 movs r0, r1\n",
+ " 32: 4608 mov r0, r1\n",
+ " 34: 43c8 mvns r0, r1\n",
+ " 36: 4408 add r0, r1\n",
+ " 38: 1888 adds r0, r1, r2\n",
+ " 3a: 1a88 subs r0, r1, r2\n",
+ " 3c: 4148 adcs r0, r1\n",
+ " 3e: 4188 sbcs r0, r1\n",
+ " 40: 4008 ands r0, r1\n",
+ " 42: 4308 orrs r0, r1\n",
+ " 44: 4048 eors r0, r1\n",
+ " 46: 4388 bics r0, r1\n",
+ " 48: 4208 tst r0, r1\n",
+ " 4a: 4288 cmp r0, r1\n",
+ " 4c: 42c8 cmn r0, r1\n",
+ " 4e: 4641 mov r1, r8\n",
+ " 50: 4681 mov r9, r0\n",
+ " 52: 46c8 mov r8, r9\n",
+ " 54: 4441 add r1, r8\n",
+ " 56: 4481 add r9, r0\n",
+ " 58: 44c8 add r8, r9\n",
+ " 5a: 4548 cmp r0, r9\n",
+ " 5c: 4588 cmp r8, r1\n",
+ " 5e: 45c1 cmp r9, r8\n",
+ " 60: 4248 negs r0, r1\n",
+ " 62: 4240 negs r0, r0\n",
+ " 64: ea5f 0008 movs.w r0, r8\n",
+ " 68: ea7f 0008 mvns.w r0, r8\n",
+ " 6c: eb01 0008 add.w r0, r1, r8\n",
+ " 70: eb11 0008 adds.w r0, r1, r8\n",
+ " 74: ebb1 0008 subs.w r0, r1, r8\n",
+ " 78: eb50 0008 adcs.w r0, r0, r8\n",
+ " 7c: eb70 0008 sbcs.w r0, r0, r8\n",
+ " 80: ea10 0008 ands.w r0, r0, r8\n",
+ " 84: ea50 0008 orrs.w r0, r0, r8\n",
+ " 88: ea90 0008 eors.w r0, r0, r8\n",
+ " 8c: ea30 0008 bics.w r0, r0, r8\n",
+ " 90: ea10 0f08 tst.w r0, r8\n",
+ " 94: eb10 0f08 cmn.w r0, r8\n",
+ " 98: f1d8 0000 rsbs r0, r8, #0\n",
+ " 9c: f1d8 0800 rsbs r8, r8, #0\n",
+ " a0: bf08 it eq\n",
+ " a2: ea7f 0001 mvnseq.w r0, r1\n",
+ " a6: bf08 it eq\n",
+ " a8: eb11 0002 addseq.w r0, r1, r2\n",
+ " ac: bf08 it eq\n",
+ " ae: ebb1 0002 subseq.w r0, r1, r2\n",
+ " b2: bf08 it eq\n",
+ " b4: eb50 0001 adcseq.w r0, r0, r1\n",
+ " b8: bf08 it eq\n",
+ " ba: eb70 0001 sbcseq.w r0, r0, r1\n",
+ " be: bf08 it eq\n",
+ " c0: ea10 0001 andseq.w r0, r0, r1\n",
+ " c4: bf08 it eq\n",
+ " c6: ea50 0001 orrseq.w r0, r0, r1\n",
+ " ca: bf08 it eq\n",
+ " cc: ea90 0001 eorseq.w r0, r0, r1\n",
+ " d0: bf08 it eq\n",
+ " d2: ea30 0001 bicseq.w r0, r0, r1\n",
" d6: bf08 it eq\n",
- " d8: 1888 addeq r0, r1, r2\n",
+ " d8: 43c8 mvneq r0, r1\n",
" da: bf08 it eq\n",
- " dc: 1a88 subeq r0, r1, r2\n",
+ " dc: 1888 addeq r0, r1, r2\n",
" de: bf08 it eq\n",
- " e0: 4148 adceq r0, r1\n",
+ " e0: 1a88 subeq r0, r1, r2\n",
" e2: bf08 it eq\n",
- " e4: 4188 sbceq r0, r1\n",
+ " e4: 4148 adceq r0, r1\n",
" e6: bf08 it eq\n",
- " e8: 4008 andeq r0, r1\n",
+ " e8: 4188 sbceq r0, r1\n",
" ea: bf08 it eq\n",
- " ec: 4308 orreq r0, r1\n",
+ " ec: 4008 andeq r0, r1\n",
" ee: bf08 it eq\n",
- " f0: 4048 eoreq r0, r1\n",
+ " f0: 4308 orreq r0, r1\n",
" f2: bf08 it eq\n",
- " f4: 4388 biceq r0, r1\n",
- " f6: 4608 mov r0, r1\n",
- " f8: 43c8 mvns r0, r1\n",
- " fa: 4408 add r0, r1\n",
- " fc: 1888 adds r0, r1, r2\n",
- " fe: 1a88 subs r0, r1, r2\n",
- " 100: 4148 adcs r0, r1\n",
- " 102: 4188 sbcs r0, r1\n",
- " 104: 4008 ands r0, r1\n",
- " 106: 4308 orrs r0, r1\n",
- " 108: 4048 eors r0, r1\n",
- " 10a: 4388 bics r0, r1\n",
- " 10c: 4641 mov r1, r8\n",
- " 10e: 4681 mov r9, r0\n",
- " 110: 46c8 mov r8, r9\n",
- " 112: 4441 add r1, r8\n",
- " 114: 4481 add r9, r0\n",
- " 116: 44c8 add r8, r9\n",
- " 118: 4248 negs r0, r1\n",
- " 11a: 4240 negs r0, r0\n",
- " 11c: eb01 0c00 add.w ip, r1, r0\n",
+ " f4: 4048 eoreq r0, r1\n",
+ " f6: bf08 it eq\n",
+ " f8: 4388 biceq r0, r1\n",
+ " fa: 4608 mov r0, r1\n",
+ " fc: 43c8 mvns r0, r1\n",
+ " fe: 4408 add r0, r1\n",
+ " 100: 1888 adds r0, r1, r2\n",
+ " 102: 1a88 subs r0, r1, r2\n",
+ " 104: 4148 adcs r0, r1\n",
+ " 106: 4188 sbcs r0, r1\n",
+ " 108: 4008 ands r0, r1\n",
+ " 10a: 4308 orrs r0, r1\n",
+ " 10c: 4048 eors r0, r1\n",
+ " 10e: 4388 bics r0, r1\n",
+ " 110: 4641 mov r1, r8\n",
+ " 112: 4681 mov r9, r0\n",
+ " 114: 46c8 mov r8, r9\n",
+ " 116: 4441 add r1, r8\n",
+ " 118: 4481 add r9, r0\n",
+ " 11a: 44c8 add r8, r9\n",
+ " 11c: 4248 negs r0, r1\n",
+ " 11e: 4240 negs r0, r0\n",
+ " 120: eb01 0c00 add.w ip, r1, r0\n",
nullptr
};
const char* DataProcessingImmediateResults[] = {
@@ -135,21 +136,22 @@ const char* DataProcessingImmediateResults[] = {
" a: f2a1 0055 subw r0, r1, #85 ; 0x55\n",
" e: f001 0055 and.w r0, r1, #85 ; 0x55\n",
" 12: f041 0055 orr.w r0, r1, #85 ; 0x55\n",
- " 16: f081 0055 eor.w r0, r1, #85 ; 0x55\n",
- " 1a: f021 0055 bic.w r0, r1, #85 ; 0x55\n",
- " 1e: f141 0055 adc.w r0, r1, #85 ; 0x55\n",
- " 22: f161 0055 sbc.w r0, r1, #85 ; 0x55\n",
- " 26: f1c1 0055 rsb r0, r1, #85 ; 0x55\n",
- " 2a: f010 0f55 tst.w r0, #85 ; 0x55\n",
- " 2e: f090 0f55 teq r0, #85 ; 0x55\n",
- " 32: 2855 cmp r0, #85 ; 0x55\n",
- " 34: f110 0f55 cmn.w r0, #85 ; 0x55\n",
- " 38: 1d48 adds r0, r1, #5\n",
- " 3a: 1f48 subs r0, r1, #5\n",
- " 3c: 2055 movs r0, #85 ; 0x55\n",
- " 3e: f07f 0055 mvns.w r0, #85 ; 0x55\n",
- " 42: 1d48 adds r0, r1, #5\n",
- " 44: 1f48 subs r0, r1, #5\n",
+ " 16: f061 0055 orn r0, r1, #85 ; 0x55\n",
+ " 1a: f081 0055 eor.w r0, r1, #85 ; 0x55\n",
+ " 1e: f021 0055 bic.w r0, r1, #85 ; 0x55\n",
+ " 22: f141 0055 adc.w r0, r1, #85 ; 0x55\n",
+ " 26: f161 0055 sbc.w r0, r1, #85 ; 0x55\n",
+ " 2a: f1c1 0055 rsb r0, r1, #85 ; 0x55\n",
+ " 2e: f010 0f55 tst.w r0, #85 ; 0x55\n",
+ " 32: f090 0f55 teq r0, #85 ; 0x55\n",
+ " 36: 2855 cmp r0, #85 ; 0x55\n",
+ " 38: f110 0f55 cmn.w r0, #85 ; 0x55\n",
+ " 3c: 1d48 adds r0, r1, #5\n",
+ " 3e: 1f48 subs r0, r1, #5\n",
+ " 40: 2055 movs r0, #85 ; 0x55\n",
+ " 42: f07f 0055 mvns.w r0, #85 ; 0x55\n",
+ " 46: 1d48 adds r0, r1, #5\n",
+ " 48: 1f48 subs r0, r1, #5\n",
nullptr
};
const char* DataProcessingModifiedImmediateResults[] = {
@@ -159,15 +161,16 @@ const char* DataProcessingModifiedImmediateResults[] = {
" c: f1a1 1055 sub.w r0, r1, #5570645 ; 0x550055\n",
" 10: f001 1055 and.w r0, r1, #5570645 ; 0x550055\n",
" 14: f041 1055 orr.w r0, r1, #5570645 ; 0x550055\n",
- " 18: f081 1055 eor.w r0, r1, #5570645 ; 0x550055\n",
- " 1c: f021 1055 bic.w r0, r1, #5570645 ; 0x550055\n",
- " 20: f141 1055 adc.w r0, r1, #5570645 ; 0x550055\n",
- " 24: f161 1055 sbc.w r0, r1, #5570645 ; 0x550055\n",
- " 28: f1c1 1055 rsb r0, r1, #5570645 ; 0x550055\n",
- " 2c: f010 1f55 tst.w r0, #5570645 ; 0x550055\n",
- " 30: f090 1f55 teq r0, #5570645 ; 0x550055\n",
- " 34: f1b0 1f55 cmp.w r0, #5570645 ; 0x550055\n",
- " 38: f110 1f55 cmn.w r0, #5570645 ; 0x550055\n",
+ " 18: f061 1055 orn r0, r1, #5570645 ; 0x550055\n",
+ " 1c: f081 1055 eor.w r0, r1, #5570645 ; 0x550055\n",
+ " 20: f021 1055 bic.w r0, r1, #5570645 ; 0x550055\n",
+ " 24: f141 1055 adc.w r0, r1, #5570645 ; 0x550055\n",
+ " 28: f161 1055 sbc.w r0, r1, #5570645 ; 0x550055\n",
+ " 2c: f1c1 1055 rsb r0, r1, #5570645 ; 0x550055\n",
+ " 30: f010 1f55 tst.w r0, #5570645 ; 0x550055\n",
+ " 34: f090 1f55 teq r0, #5570645 ; 0x550055\n",
+ " 38: f1b0 1f55 cmp.w r0, #5570645 ; 0x550055\n",
+ " 3c: f110 1f55 cmn.w r0, #5570645 ; 0x550055\n",
nullptr
};
const char* DataProcessingModifiedImmediatesResults[] = {
diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc
index 6e7d74d528..9eb5e67041 100644
--- a/compiler/utils/x86_64/assembler_x86_64.cc
+++ b/compiler/utils/x86_64/assembler_x86_64.cc
@@ -3122,7 +3122,14 @@ void X86_64Assembler::AddConstantArea() {
}
}
-int ConstantArea::AddInt32(int32_t v) {
+size_t ConstantArea::AppendInt32(int32_t v) {
+ size_t result = buffer_.size() * elem_size_;
+ buffer_.push_back(v);
+ return result;
+}
+
+size_t ConstantArea::AddInt32(int32_t v) {
+ // Look for an existing match.
for (size_t i = 0, e = buffer_.size(); i < e; i++) {
if (v == buffer_[i]) {
return i * elem_size_;
@@ -3130,12 +3137,10 @@ int ConstantArea::AddInt32(int32_t v) {
}
// Didn't match anything.
- int result = buffer_.size() * elem_size_;
- buffer_.push_back(v);
- return result;
+ return AppendInt32(v);
}
-int ConstantArea::AddInt64(int64_t v) {
+size_t ConstantArea::AddInt64(int64_t v) {
int32_t v_low = v;
int32_t v_high = v >> 32;
if (buffer_.size() > 1) {
@@ -3148,18 +3153,18 @@ int ConstantArea::AddInt64(int64_t v) {
}
// Didn't match anything.
- int result = buffer_.size() * elem_size_;
+ size_t result = buffer_.size() * elem_size_;
buffer_.push_back(v_low);
buffer_.push_back(v_high);
return result;
}
-int ConstantArea::AddDouble(double v) {
+size_t ConstantArea::AddDouble(double v) {
// Treat the value as a 64-bit integer value.
return AddInt64(bit_cast<int64_t, double>(v));
}
-int ConstantArea::AddFloat(float v) {
+size_t ConstantArea::AddFloat(float v) {
// Treat the value as a 32-bit integer value.
return AddInt32(bit_cast<int32_t, float>(v));
}
diff --git a/compiler/utils/x86_64/assembler_x86_64.h b/compiler/utils/x86_64/assembler_x86_64.h
index 255f551675..01d28e305d 100644
--- a/compiler/utils/x86_64/assembler_x86_64.h
+++ b/compiler/utils/x86_64/assembler_x86_64.h
@@ -269,36 +269,40 @@ class Address : public Operand {
* Class to handle constant area values.
*/
class ConstantArea {
- public:
- ConstantArea() {}
+ public:
+ ConstantArea() {}
- // Add a double to the constant area, returning the offset into
- // the constant area where the literal resides.
- int AddDouble(double v);
+ // Add a double to the constant area, returning the offset into
+ // the constant area where the literal resides.
+ size_t AddDouble(double v);
- // Add a float to the constant area, returning the offset into
- // the constant area where the literal resides.
- int AddFloat(float v);
+ // Add a float to the constant area, returning the offset into
+ // the constant area where the literal resides.
+ size_t AddFloat(float v);
- // Add an int32_t to the constant area, returning the offset into
- // the constant area where the literal resides.
- int AddInt32(int32_t v);
+ // Add an int32_t to the constant area, returning the offset into
+ // the constant area where the literal resides.
+ size_t AddInt32(int32_t v);
- // Add an int64_t to the constant area, returning the offset into
- // the constant area where the literal resides.
- int AddInt64(int64_t v);
+ // Add an int32_t to the end of the constant area, returning the offset into
+ // the constant area where the literal resides.
+ size_t AppendInt32(int32_t v);
- int GetSize() const {
- return buffer_.size() * elem_size_;
- }
+ // Add an int64_t to the constant area, returning the offset into
+ // the constant area where the literal resides.
+ size_t AddInt64(int64_t v);
- const std::vector<int32_t>& GetBuffer() const {
- return buffer_;
- }
+ size_t GetSize() const {
+ return buffer_.size() * elem_size_;
+ }
- private:
- static constexpr size_t elem_size_ = sizeof(int32_t);
- std::vector<int32_t> buffer_;
+ const std::vector<int32_t>& GetBuffer() const {
+ return buffer_;
+ }
+
+ private:
+ static constexpr size_t elem_size_ = sizeof(int32_t);
+ std::vector<int32_t> buffer_;
};
@@ -806,19 +810,27 @@ class X86_64Assembler FINAL : public Assembler {
// Add a double to the constant area, returning the offset into
// the constant area where the literal resides.
- int AddDouble(double v) { return constant_area_.AddDouble(v); }
+ size_t AddDouble(double v) { return constant_area_.AddDouble(v); }
// Add a float to the constant area, returning the offset into
// the constant area where the literal resides.
- int AddFloat(float v) { return constant_area_.AddFloat(v); }
+ size_t AddFloat(float v) { return constant_area_.AddFloat(v); }
// Add an int32_t to the constant area, returning the offset into
// the constant area where the literal resides.
- int AddInt32(int32_t v) { return constant_area_.AddInt32(v); }
+ size_t AddInt32(int32_t v) {
+ return constant_area_.AddInt32(v);
+ }
+
+ // Add an int32_t to the end of the constant area, returning the offset into
+ // the constant area where the literal resides.
+ size_t AppendInt32(int32_t v) {
+ return constant_area_.AppendInt32(v);
+ }
// Add an int64_t to the constant area, returning the offset into
// the constant area where the literal resides.
- int AddInt64(int64_t v) { return constant_area_.AddInt64(v); }
+ size_t AddInt64(int64_t v) { return constant_area_.AddInt64(v); }
// Add the contents of the constant area to the assembler buffer.
void AddConstantArea();
@@ -826,6 +838,9 @@ class X86_64Assembler FINAL : public Assembler {
// Is the constant area empty? Return true if there are no literals in the constant area.
bool IsConstantAreaEmpty() const { return constant_area_.GetSize() == 0; }
+ // Return the current size of the constant area.
+ size_t ConstantAreaSize() const { return constant_area_.GetSize(); }
+
//
// Heap poisoning.
//
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-11-02 07:48:46 +0000