diff options
Diffstat (limited to 'compiler/utils')
| -rw-r--r-- | compiler/utils/arm/assembler_arm_vixl.cc | 2 | ||||
| -rw-r--r-- | compiler/utils/assembler.h | 2 | ||||
| -rw-r--r-- | compiler/utils/assembler_thumb_test.cc | 4 | ||||
| -rw-r--r-- | compiler/utils/mips/assembler_mips.cc | 74 | ||||
| -rw-r--r-- | compiler/utils/mips/assembler_mips.h | 14 | ||||
| -rw-r--r-- | compiler/utils/mips/assembler_mips32r6_test.cc | 68 | ||||
| -rw-r--r-- | compiler/utils/mips/assembler_mips_test.cc | 32 | ||||
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.cc | 52 | ||||
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.h | 10 | ||||
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64_test.cc | 50 | ||||
| -rw-r--r-- | compiler/utils/x86/assembler_x86.cc | 4 | ||||
| -rw-r--r-- | compiler/utils/x86_64/assembler_x86_64.cc | 4 | ||||
| -rw-r--r-- | compiler/utils/x86_64/assembler_x86_64_test.cc | 2 |
13 files changed, 159 insertions, 159 deletions
diff --git a/compiler/utils/arm/assembler_arm_vixl.cc b/compiler/utils/arm/assembler_arm_vixl.cc index ebb631e33c..77f5d7081a 100644 --- a/compiler/utils/arm/assembler_arm_vixl.cc +++ b/compiler/utils/arm/assembler_arm_vixl.cc @@ -91,7 +91,7 @@ void ArmVIXLAssembler::GenerateMarkingRegisterCheck(vixl32::Register temp, int c ___ Ldr(temp, MemOperand(tr, Thread::IsGcMarkingOffset<kArmPointerSize>().Int32Value())); // Check that mr == self.tls32_.is.gc_marking. ___ Cmp(mr, temp); - ___ B(eq, &mr_is_ok, /* far_target */ false); + ___ B(eq, &mr_is_ok, /* is_far_target= */ false); ___ Bkpt(code); ___ Bind(&mr_is_ok); } diff --git a/compiler/utils/assembler.h b/compiler/utils/assembler.h index 096410de3e..05372251dc 100644 --- a/compiler/utils/assembler.h +++ b/compiler/utils/assembler.h @@ -295,7 +295,7 @@ class DebugFrameOpCodeWriterForAssembler final void ImplicitlyAdvancePC() final; explicit DebugFrameOpCodeWriterForAssembler(Assembler* buffer) - : dwarf::DebugFrameOpCodeWriter<>(false /* enabled */), + : dwarf::DebugFrameOpCodeWriter<>(/* enabled= */ false), assembler_(buffer), delay_emitting_advance_pc_(false), delayed_advance_pcs_() { diff --git a/compiler/utils/assembler_thumb_test.cc b/compiler/utils/assembler_thumb_test.cc index 3d262969a4..c9ece1df69 100644 --- a/compiler/utils/assembler_thumb_test.cc +++ b/compiler/utils/assembler_thumb_test.cc @@ -239,7 +239,7 @@ TEST_F(ArmVIXLAssemblerTest, VixlJniHelpers) { __ Load(scratch_register, FrameOffset(4092), 4); __ Load(scratch_register, FrameOffset(4096), 4); __ LoadRawPtrFromThread(scratch_register, ThreadOffset32(512)); - __ LoadRef(method_register, scratch_register, MemberOffset(128), /* unpoison_reference */ false); + __ LoadRef(method_register, scratch_register, MemberOffset(128), /* unpoison_reference= */ false); // Stores __ Store(FrameOffset(32), method_register, 4); @@ -284,7 +284,7 @@ TEST_F(ArmVIXLAssemblerTest, VixlJniHelpers) { __ DecreaseFrameSize(4096); __ DecreaseFrameSize(32); - __ RemoveFrame(frame_size, callee_save_regs, /* may_suspend */ true); + __ RemoveFrame(frame_size, callee_save_regs, /* may_suspend= */ true); EmitAndCheck(&assembler, "VixlJniHelpers"); } diff --git a/compiler/utils/mips/assembler_mips.cc b/compiler/utils/mips/assembler_mips.cc index a673e3210c..a9d1a25530 100644 --- a/compiler/utils/mips/assembler_mips.cc +++ b/compiler/utils/mips/assembler_mips.cc @@ -463,7 +463,7 @@ void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16, MipsLabel* p } void MipsAssembler::Addiu(Register rt, Register rs, uint16_t imm16) { - Addiu(rt, rs, imm16, /* patcher_label */ nullptr); + Addiu(rt, rs, imm16, /* patcher_label= */ nullptr); } void MipsAssembler::Subu(Register rd, Register rs, Register rt) { @@ -732,7 +732,7 @@ void MipsAssembler::Lw(Register rt, Register rs, uint16_t imm16, MipsLabel* patc } void MipsAssembler::Lw(Register rt, Register rs, uint16_t imm16) { - Lw(rt, rs, imm16, /* patcher_label */ nullptr); + Lw(rt, rs, imm16, /* patcher_label= */ nullptr); } void MipsAssembler::Lwl(Register rt, Register rs, uint16_t imm16) { @@ -814,7 +814,7 @@ void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16, MipsLabel* patc } void MipsAssembler::Sw(Register rt, Register rs, uint16_t imm16) { - Sw(rt, rs, imm16, /* patcher_label */ nullptr); + Sw(rt, rs, imm16, /* patcher_label= */ nullptr); } void MipsAssembler::Swl(Register rt, Register rs, uint16_t imm16) { @@ -3755,7 +3755,7 @@ void MipsAssembler::MoveInstructionToDelaySlot(Branch& branch) { void MipsAssembler::Buncond(MipsLabel* label, bool is_r6, bool is_bare) { uint32_t target = label->IsBound() ? GetLabelLocation(label) : Branch::kUnresolved; - branches_.emplace_back(is_r6, buffer_.Size(), target, /* is_call */ false, is_bare); + branches_.emplace_back(is_r6, buffer_.Size(), target, /* is_call= */ false, is_bare); MoveInstructionToDelaySlot(branches_.back()); FinalizeLabeledBranch(label); } @@ -3778,7 +3778,7 @@ void MipsAssembler::Bcond(MipsLabel* label, void MipsAssembler::Call(MipsLabel* label, bool is_r6, bool is_bare) { uint32_t target = label->IsBound() ? GetLabelLocation(label) : Branch::kUnresolved; - branches_.emplace_back(is_r6, buffer_.Size(), target, /* is_call */ true, is_bare); + branches_.emplace_back(is_r6, buffer_.Size(), target, /* is_call= */ true, is_bare); MoveInstructionToDelaySlot(branches_.back()); FinalizeLabeledBranch(label); } @@ -4300,43 +4300,43 @@ void MipsAssembler::EmitBranch(uint32_t branch_id) { } void MipsAssembler::B(MipsLabel* label, bool is_bare) { - Buncond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare); + Buncond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare); } void MipsAssembler::Bal(MipsLabel* label, bool is_bare) { - Call(label, /* is_r6 */ (IsR6() && !is_bare), is_bare); + Call(label, /* is_r6= */ (IsR6() && !is_bare), is_bare); } void MipsAssembler::Beq(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondEQ, rs, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondEQ, rs, rt); } void MipsAssembler::Bne(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondNE, rs, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondNE, rs, rt); } void MipsAssembler::Beqz(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondEQZ, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondEQZ, rt); } void MipsAssembler::Bnez(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondNEZ, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondNEZ, rt); } void MipsAssembler::Bltz(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondLTZ, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondLTZ, rt); } void MipsAssembler::Bgez(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondGEZ, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondGEZ, rt); } void MipsAssembler::Blez(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondLEZ, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondLEZ, rt); } void MipsAssembler::Bgtz(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ (IsR6() && !is_bare), is_bare, kCondGTZ, rt); + Bcond(label, /* is_r6= */ (IsR6() && !is_bare), is_bare, kCondGTZ, rt); } bool MipsAssembler::CanExchangeWithSlt(Register rs, Register rt) const { @@ -4392,7 +4392,7 @@ void MipsAssembler::Blt(Register rs, Register rt, MipsLabel* label, bool is_bare Bcond(label, IsR6(), is_bare, kCondLT, rs, rt); } else if (!Branch::IsNop(kCondLT, rs, rt)) { // Synthesize the instruction (not available on R2). - GenerateSltForCondBranch(/* unsigned_slt */ false, rs, rt); + GenerateSltForCondBranch(/* unsigned_slt= */ false, rs, rt); Bnez(AT, label, is_bare); } } @@ -4404,7 +4404,7 @@ void MipsAssembler::Bge(Register rs, Register rt, MipsLabel* label, bool is_bare B(label, is_bare); } else { // Synthesize the instruction (not available on R2). - GenerateSltForCondBranch(/* unsigned_slt */ false, rs, rt); + GenerateSltForCondBranch(/* unsigned_slt= */ false, rs, rt); Beqz(AT, label, is_bare); } } @@ -4414,7 +4414,7 @@ void MipsAssembler::Bltu(Register rs, Register rt, MipsLabel* label, bool is_bar Bcond(label, IsR6(), is_bare, kCondLTU, rs, rt); } else if (!Branch::IsNop(kCondLTU, rs, rt)) { // Synthesize the instruction (not available on R2). - GenerateSltForCondBranch(/* unsigned_slt */ true, rs, rt); + GenerateSltForCondBranch(/* unsigned_slt= */ true, rs, rt); Bnez(AT, label, is_bare); } } @@ -4426,7 +4426,7 @@ void MipsAssembler::Bgeu(Register rs, Register rt, MipsLabel* label, bool is_bar B(label, is_bare); } else { // Synthesize the instruction (not available on R2). - GenerateSltForCondBranch(/* unsigned_slt */ true, rs, rt); + GenerateSltForCondBranch(/* unsigned_slt= */ true, rs, rt); Beqz(AT, label, is_bare); } } @@ -4437,7 +4437,7 @@ void MipsAssembler::Bc1f(MipsLabel* label, bool is_bare) { void MipsAssembler::Bc1f(int cc, MipsLabel* label, bool is_bare) { CHECK(IsUint<3>(cc)) << cc; - Bcond(label, /* is_r6 */ false, is_bare, kCondF, static_cast<Register>(cc), ZERO); + Bcond(label, /* is_r6= */ false, is_bare, kCondF, static_cast<Register>(cc), ZERO); } void MipsAssembler::Bc1t(MipsLabel* label, bool is_bare) { @@ -4446,71 +4446,71 @@ void MipsAssembler::Bc1t(MipsLabel* label, bool is_bare) { void MipsAssembler::Bc1t(int cc, MipsLabel* label, bool is_bare) { CHECK(IsUint<3>(cc)) << cc; - Bcond(label, /* is_r6 */ false, is_bare, kCondT, static_cast<Register>(cc), ZERO); + Bcond(label, /* is_r6= */ false, is_bare, kCondT, static_cast<Register>(cc), ZERO); } void MipsAssembler::Bc(MipsLabel* label, bool is_bare) { - Buncond(label, /* is_r6 */ true, is_bare); + Buncond(label, /* is_r6= */ true, is_bare); } void MipsAssembler::Balc(MipsLabel* label, bool is_bare) { - Call(label, /* is_r6 */ true, is_bare); + Call(label, /* is_r6= */ true, is_bare); } void MipsAssembler::Beqc(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondEQ, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondEQ, rs, rt); } void MipsAssembler::Bnec(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondNE, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondNE, rs, rt); } void MipsAssembler::Beqzc(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondEQZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondEQZ, rt); } void MipsAssembler::Bnezc(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondNEZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondNEZ, rt); } void MipsAssembler::Bltzc(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLTZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLTZ, rt); } void MipsAssembler::Bgezc(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGEZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGEZ, rt); } void MipsAssembler::Blezc(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLEZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLEZ, rt); } void MipsAssembler::Bgtzc(Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGTZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGTZ, rt); } void MipsAssembler::Bltc(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLT, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLT, rs, rt); } void MipsAssembler::Bgec(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGE, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGE, rs, rt); } void MipsAssembler::Bltuc(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLTU, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLTU, rs, rt); } void MipsAssembler::Bgeuc(Register rs, Register rt, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGEU, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGEU, rs, rt); } void MipsAssembler::Bc1eqz(FRegister ft, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondF, static_cast<Register>(ft), ZERO); + Bcond(label, /* is_r6= */ true, is_bare, kCondF, static_cast<Register>(ft), ZERO); } void MipsAssembler::Bc1nez(FRegister ft, MipsLabel* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondT, static_cast<Register>(ft), ZERO); + Bcond(label, /* is_r6= */ true, is_bare, kCondT, static_cast<Register>(ft), ZERO); } void MipsAssembler::AdjustBaseAndOffset(Register& base, diff --git a/compiler/utils/mips/assembler_mips.h b/compiler/utils/mips/assembler_mips.h index 8a1e1df777..69189a49aa 100644 --- a/compiler/utils/mips/assembler_mips.h +++ b/compiler/utils/mips/assembler_mips.h @@ -862,7 +862,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi // We permit `base` and `temp` to coincide (however, we check that neither is AT), // in which case the `base` register may be overwritten in the process. CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base. - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); uint32_t low = Low32Bits(value); uint32_t high = High32Bits(value); Register reg; @@ -917,7 +917,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi Register base, int32_t offset, ImplicitNullChecker null_checker = NoImplicitNullChecker()) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kLoadDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kLoadDoubleword)); switch (type) { case kLoadSignedByte: Lb(reg, base, offset); @@ -960,7 +960,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi Register base, int32_t offset, ImplicitNullChecker null_checker = NoImplicitNullChecker()) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ false, /* is_float */ true); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ false, /* is_float= */ true); Lwc1(reg, base, offset); null_checker(); } @@ -970,7 +970,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi Register base, int32_t offset, ImplicitNullChecker null_checker = NoImplicitNullChecker()) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ true, /* is_float */ true); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ true, /* is_float= */ true); if (IsAligned<kMipsDoublewordSize>(offset)) { Ldc1(reg, base, offset); null_checker(); @@ -1016,7 +1016,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi // Must not use AT as `reg`, so as not to overwrite the value being stored // with the adjusted `base`. CHECK_NE(reg, AT); - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); switch (type) { case kStoreByte: Sb(reg, base, offset); @@ -1047,7 +1047,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi Register base, int32_t offset, ImplicitNullChecker null_checker = NoImplicitNullChecker()) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ false, /* is_float */ true); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ false, /* is_float= */ true); Swc1(reg, base, offset); null_checker(); } @@ -1057,7 +1057,7 @@ class MipsAssembler final : public Assembler, public JNIMacroAssembler<PointerSi Register base, int32_t offset, ImplicitNullChecker null_checker = NoImplicitNullChecker()) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ true, /* is_float */ true); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ true, /* is_float= */ true); if (IsAligned<kMipsDoublewordSize>(offset)) { Sdc1(reg, base, offset); null_checker(); diff --git a/compiler/utils/mips/assembler_mips32r6_test.cc b/compiler/utils/mips/assembler_mips32r6_test.cc index 723c489f21..4e27bbf28d 100644 --- a/compiler/utils/mips/assembler_mips32r6_test.cc +++ b/compiler/utils/mips/assembler_mips32r6_test.cc @@ -1078,11 +1078,11 @@ TEST_F(AssemblerMIPS32r6Test, StoreQToOffset) { ////////////// TEST_F(AssemblerMIPS32r6Test, Bc) { - BranchHelper(&mips::MipsAssembler::Bc, "Bc", /* has_slot */ false); + BranchHelper(&mips::MipsAssembler::Bc, "Bc", /* has_slot= */ false); } TEST_F(AssemblerMIPS32r6Test, Balc) { - BranchHelper(&mips::MipsAssembler::Balc, "Balc", /* has_slot */ false); + BranchHelper(&mips::MipsAssembler::Balc, "Balc", /* has_slot= */ false); } TEST_F(AssemblerMIPS32r6Test, Beqc) { @@ -1142,11 +1142,11 @@ TEST_F(AssemblerMIPS32r6Test, Bc1nez) { } TEST_F(AssemblerMIPS32r6Test, B) { - BranchHelper(&mips::MipsAssembler::B, "Bc", /* has_slot */ false); + BranchHelper(&mips::MipsAssembler::B, "Bc", /* has_slot= */ false); } TEST_F(AssemblerMIPS32r6Test, Bal) { - BranchHelper(&mips::MipsAssembler::Bal, "Balc", /* has_slot */ false); + BranchHelper(&mips::MipsAssembler::Bal, "Balc", /* has_slot= */ false); } TEST_F(AssemblerMIPS32r6Test, Beq) { @@ -1198,123 +1198,123 @@ TEST_F(AssemblerMIPS32r6Test, Bgeu) { } TEST_F(AssemblerMIPS32r6Test, BareBc) { - BranchHelper(&mips::MipsAssembler::Bc, "Bc", /* has_slot */ false, /* is_bare */ true); + BranchHelper(&mips::MipsAssembler::Bc, "Bc", /* has_slot= */ false, /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBalc) { - BranchHelper(&mips::MipsAssembler::Balc, "Balc", /* has_slot */ false, /* is_bare */ true); + BranchHelper(&mips::MipsAssembler::Balc, "Balc", /* has_slot= */ false, /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBeqc) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Beqc, "Beqc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Beqc, "Beqc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBnec) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bnec, "Bnec", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bnec, "Bnec", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBeqzc) { - BranchCondOneRegHelper(&mips::MipsAssembler::Beqzc, "Beqzc", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Beqzc, "Beqzc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBnezc) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bnezc, "Bnezc", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bnezc, "Bnezc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBltzc) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bltzc, "Bltzc", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bltzc, "Bltzc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgezc) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bgezc, "Bgezc", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bgezc, "Bgezc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBlezc) { - BranchCondOneRegHelper(&mips::MipsAssembler::Blezc, "Blezc", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Blezc, "Blezc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgtzc) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bgtzc, "Bgtzc", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bgtzc, "Bgtzc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBltc) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltc, "Bltc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltc, "Bltc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgec) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgec, "Bgec", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgec, "Bgec", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBltuc) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltuc, "Bltuc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltuc, "Bltuc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgeuc) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeuc, "Bgeuc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeuc, "Bgeuc", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBc1eqz) { - BranchFpuCondHelper(&mips::MipsAssembler::Bc1eqz, "Bc1eqz", /* is_bare */ true); + BranchFpuCondHelper(&mips::MipsAssembler::Bc1eqz, "Bc1eqz", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBc1nez) { - BranchFpuCondHelper(&mips::MipsAssembler::Bc1nez, "Bc1nez", /* is_bare */ true); + BranchFpuCondHelper(&mips::MipsAssembler::Bc1nez, "Bc1nez", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareB) { - BranchHelper(&mips::MipsAssembler::B, "B", /* has_slot */ true, /* is_bare */ true); + BranchHelper(&mips::MipsAssembler::B, "B", /* has_slot= */ true, /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBal) { - BranchHelper(&mips::MipsAssembler::Bal, "Bal", /* has_slot */ true, /* is_bare */ true); + BranchHelper(&mips::MipsAssembler::Bal, "Bal", /* has_slot= */ true, /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBeq) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBne) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bne, "Bne", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bne, "Bne", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBeqz) { - BranchCondOneRegHelper(&mips::MipsAssembler::Beqz, "Beqz", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Beqz, "Beqz", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBnez) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBltz) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bltz, "Bltz", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bltz, "Bltz", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgez) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bgez, "Bgez", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bgez, "Bgez", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBlez) { - BranchCondOneRegHelper(&mips::MipsAssembler::Blez, "Blez", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Blez, "Blez", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgtz) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bgtz, "Bgtz", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bgtz, "Bgtz", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBlt) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Blt, "Blt", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Blt, "Blt", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBge) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bge, "Bge", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bge, "Bge", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBltu) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltu, "Bltu", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltu, "Bltu", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, BareBgeu) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeu, "Bgeu", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeu, "Bgeu", /* is_bare= */ true); } TEST_F(AssemblerMIPS32r6Test, LongBeqc) { diff --git a/compiler/utils/mips/assembler_mips_test.cc b/compiler/utils/mips/assembler_mips_test.cc index 4f8ccee2c2..c0894d309e 100644 --- a/compiler/utils/mips/assembler_mips_test.cc +++ b/compiler/utils/mips/assembler_mips_test.cc @@ -2241,67 +2241,67 @@ TEST_F(AssemblerMIPSTest, Bc1t) { } TEST_F(AssemblerMIPSTest, BareB) { - BranchHelper(&mips::MipsAssembler::B, "B", /* is_bare */ true); + BranchHelper(&mips::MipsAssembler::B, "B", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBal) { - BranchHelper(&mips::MipsAssembler::Bal, "Bal", /* is_bare */ true); + BranchHelper(&mips::MipsAssembler::Bal, "Bal", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBeq) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Beq, "Beq", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBne) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bne, "Bne", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bne, "Bne", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBeqz) { - BranchCondOneRegHelper(&mips::MipsAssembler::Beqz, "Beqz", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Beqz, "Beqz", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBnez) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bnez, "Bnez", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBltz) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bltz, "Bltz", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bltz, "Bltz", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBgez) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bgez, "Bgez", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bgez, "Bgez", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBlez) { - BranchCondOneRegHelper(&mips::MipsAssembler::Blez, "Blez", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Blez, "Blez", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBgtz) { - BranchCondOneRegHelper(&mips::MipsAssembler::Bgtz, "Bgtz", /* is_bare */ true); + BranchCondOneRegHelper(&mips::MipsAssembler::Bgtz, "Bgtz", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBlt) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Blt, "Blt", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Blt, "Blt", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBge) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bge, "Bge", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bge, "Bge", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBltu) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltu, "Bltu", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bltu, "Bltu", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBgeu) { - BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeu, "Bgeu", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips::MipsAssembler::Bgeu, "Bgeu", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBc1f) { - BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1f, "Bc1f", /* is_bare */ true); + BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1f, "Bc1f", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, BareBc1t) { - BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1t, "Bc1t", /* is_bare */ true); + BranchFpuCondCodeHelper(&mips::MipsAssembler::Bc1t, "Bc1t", /* is_bare= */ true); } TEST_F(AssemblerMIPSTest, ImpossibleReordering) { diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc index 29d2beda96..70313ca093 100644 --- a/compiler/utils/mips64/assembler_mips64.cc +++ b/compiler/utils/mips64/assembler_mips64.cc @@ -2455,7 +2455,7 @@ Mips64Assembler::Branch::Branch(uint32_t location, uint32_t target, bool is_call condition_(kUncond) { InitializeType( (is_call ? (is_bare ? kBareCall : kCall) : (is_bare ? kBareCondBranch : kCondBranch)), - /* is_r6 */ true); + /* is_r6= */ true); } Mips64Assembler::Branch::Branch(bool is_r6, @@ -2516,7 +2516,7 @@ Mips64Assembler::Branch::Branch(uint32_t location, GpuRegister dest_reg, Type la rhs_reg_(ZERO), condition_(kUncond) { CHECK_NE(dest_reg, ZERO); - InitializeType(label_or_literal_type, /* is_r6 */ true); + InitializeType(label_or_literal_type, /* is_r6= */ true); } Mips64Assembler::BranchCondition Mips64Assembler::Branch::OppositeCondition( @@ -2896,7 +2896,7 @@ void Mips64Assembler::FinalizeLabeledBranch(Mips64Label* label) { void Mips64Assembler::Buncond(Mips64Label* label, bool is_bare) { uint32_t target = label->IsBound() ? GetLabelLocation(label) : Branch::kUnresolved; - branches_.emplace_back(buffer_.Size(), target, /* is_call */ false, is_bare); + branches_.emplace_back(buffer_.Size(), target, /* is_call= */ false, is_bare); FinalizeLabeledBranch(label); } @@ -2917,7 +2917,7 @@ void Mips64Assembler::Bcond(Mips64Label* label, void Mips64Assembler::Call(Mips64Label* label, bool is_bare) { uint32_t target = label->IsBound() ? GetLabelLocation(label) : Branch::kUnresolved; - branches_.emplace_back(buffer_.Size(), target, /* is_call */ true, is_bare); + branches_.emplace_back(buffer_.Size(), target, /* is_call= */ true, is_bare); FinalizeLabeledBranch(label); } @@ -3278,99 +3278,99 @@ void Mips64Assembler::Balc(Mips64Label* label, bool is_bare) { } void Mips64Assembler::Bltc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLT, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLT, rs, rt); } void Mips64Assembler::Bltzc(GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLTZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLTZ, rt); } void Mips64Assembler::Bgtzc(GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGTZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGTZ, rt); } void Mips64Assembler::Bgec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGE, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGE, rs, rt); } void Mips64Assembler::Bgezc(GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGEZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGEZ, rt); } void Mips64Assembler::Blezc(GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLEZ, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLEZ, rt); } void Mips64Assembler::Bltuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondLTU, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondLTU, rs, rt); } void Mips64Assembler::Bgeuc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondGEU, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondGEU, rs, rt); } void Mips64Assembler::Beqc(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondEQ, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondEQ, rs, rt); } void Mips64Assembler::Bnec(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondNE, rs, rt); + Bcond(label, /* is_r6= */ true, is_bare, kCondNE, rs, rt); } void Mips64Assembler::Beqzc(GpuRegister rs, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondEQZ, rs); + Bcond(label, /* is_r6= */ true, is_bare, kCondEQZ, rs); } void Mips64Assembler::Bnezc(GpuRegister rs, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondNEZ, rs); + Bcond(label, /* is_r6= */ true, is_bare, kCondNEZ, rs); } void Mips64Assembler::Bc1eqz(FpuRegister ft, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondF, static_cast<GpuRegister>(ft), ZERO); + Bcond(label, /* is_r6= */ true, is_bare, kCondF, static_cast<GpuRegister>(ft), ZERO); } void Mips64Assembler::Bc1nez(FpuRegister ft, Mips64Label* label, bool is_bare) { - Bcond(label, /* is_r6 */ true, is_bare, kCondT, static_cast<GpuRegister>(ft), ZERO); + Bcond(label, /* is_r6= */ true, is_bare, kCondT, static_cast<GpuRegister>(ft), ZERO); } void Mips64Assembler::Bltz(GpuRegister rt, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondLTZ, rt); + Bcond(label, /* is_r6= */ false, is_bare, kCondLTZ, rt); } void Mips64Assembler::Bgtz(GpuRegister rt, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondGTZ, rt); + Bcond(label, /* is_r6= */ false, is_bare, kCondGTZ, rt); } void Mips64Assembler::Bgez(GpuRegister rt, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondGEZ, rt); + Bcond(label, /* is_r6= */ false, is_bare, kCondGEZ, rt); } void Mips64Assembler::Blez(GpuRegister rt, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondLEZ, rt); + Bcond(label, /* is_r6= */ false, is_bare, kCondLEZ, rt); } void Mips64Assembler::Beq(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondEQ, rs, rt); + Bcond(label, /* is_r6= */ false, is_bare, kCondEQ, rs, rt); } void Mips64Assembler::Bne(GpuRegister rs, GpuRegister rt, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondNE, rs, rt); + Bcond(label, /* is_r6= */ false, is_bare, kCondNE, rs, rt); } void Mips64Assembler::Beqz(GpuRegister rs, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondEQZ, rs); + Bcond(label, /* is_r6= */ false, is_bare, kCondEQZ, rs); } void Mips64Assembler::Bnez(GpuRegister rs, Mips64Label* label, bool is_bare) { CHECK(is_bare); - Bcond(label, /* is_r6 */ false, is_bare, kCondNEZ, rs); + Bcond(label, /* is_r6= */ false, is_bare, kCondNEZ, rs); } void Mips64Assembler::AdjustBaseAndOffset(GpuRegister& base, diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h index ce447db4fb..2f991e92c5 100644 --- a/compiler/utils/mips64/assembler_mips64.h +++ b/compiler/utils/mips64/assembler_mips64.h @@ -1058,7 +1058,7 @@ class Mips64Assembler final : public Assembler, public JNIMacroAssembler<Pointer // We permit `base` and `temp` to coincide (however, we check that neither is AT), // in which case the `base` register may be overwritten in the process. CHECK_NE(temp, AT); // Must not use AT as temp, so as not to overwrite the adjusted base. - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); GpuRegister reg; // If the adjustment left `base` unchanged and equal to `temp`, we can't use `temp` // to load and hold the value but we can use AT instead as AT hasn't been used yet. @@ -1127,7 +1127,7 @@ class Mips64Assembler final : public Assembler, public JNIMacroAssembler<Pointer GpuRegister base, int32_t offset, ImplicitNullChecker null_checker = NoImplicitNullChecker()) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kLoadDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kLoadDoubleword)); switch (type) { case kLoadSignedByte: @@ -1178,7 +1178,7 @@ class Mips64Assembler final : public Assembler, public JNIMacroAssembler<Pointer ImplicitNullChecker null_checker = NoImplicitNullChecker()) { int element_size_shift = -1; if (type != kLoadQuadword) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kLoadDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kLoadDoubleword)); } else { AdjustBaseOffsetAndElementSizeShift(base, offset, element_size_shift); } @@ -1226,7 +1226,7 @@ class Mips64Assembler final : public Assembler, public JNIMacroAssembler<Pointer // Must not use AT as `reg`, so as not to overwrite the value being stored // with the adjusted `base`. CHECK_NE(reg, AT); - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); switch (type) { case kStoreByte: @@ -1267,7 +1267,7 @@ class Mips64Assembler final : public Assembler, public JNIMacroAssembler<Pointer ImplicitNullChecker null_checker = NoImplicitNullChecker()) { int element_size_shift = -1; if (type != kStoreQuadword) { - AdjustBaseAndOffset(base, offset, /* is_doubleword */ (type == kStoreDoubleword)); + AdjustBaseAndOffset(base, offset, /* is_doubleword= */ (type == kStoreDoubleword)); } else { AdjustBaseOffsetAndElementSizeShift(base, offset, element_size_shift); } diff --git a/compiler/utils/mips64/assembler_mips64_test.cc b/compiler/utils/mips64/assembler_mips64_test.cc index 66711c3210..499e8f4e15 100644 --- a/compiler/utils/mips64/assembler_mips64_test.cc +++ b/compiler/utils/mips64/assembler_mips64_test.cc @@ -852,99 +852,99 @@ TEST_F(AssemblerMIPS64Test, Bc1nez) { } TEST_F(AssemblerMIPS64Test, BareBc) { - BranchHelper(&mips64::Mips64Assembler::Bc, "Bc", /* is_bare */ true); + BranchHelper(&mips64::Mips64Assembler::Bc, "Bc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBalc) { - BranchHelper(&mips64::Mips64Assembler::Balc, "Balc", /* is_bare */ true); + BranchHelper(&mips64::Mips64Assembler::Balc, "Balc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBeqzc) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqzc, "Beqzc", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqzc, "Beqzc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBnezc) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnezc, "Bnezc", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnezc, "Bnezc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBltzc) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltzc, "Bltzc", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltzc, "Bltzc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBgezc) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgezc, "Bgezc", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgezc, "Bgezc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBlezc) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Blezc, "Blezc", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Blezc, "Blezc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBgtzc) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtzc, "Bgtzc", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtzc, "Bgtzc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBeqc) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beqc, "Beqc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beqc, "Beqc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBnec) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bnec, "Bnec", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bnec, "Bnec", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBltc) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltc, "Bltc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltc, "Bltc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBgec) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgec, "Bgec", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgec, "Bgec", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBltuc) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltuc, "Bltuc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bltuc, "Bltuc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBgeuc) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgeuc, "Bgeuc", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bgeuc, "Bgeuc", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBc1eqz) { - BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1eqz, "Bc1eqz", /* is_bare */ true); + BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1eqz, "Bc1eqz", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBc1nez) { - BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1nez, "Bc1nez", /* is_bare */ true); + BranchFpuCondHelper(&mips64::Mips64Assembler::Bc1nez, "Bc1nez", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBeqz) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqz, "Beqz", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Beqz, "Beqz", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBnez) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnez, "Bnez", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bnez, "Bnez", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBltz) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltz, "Bltz", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bltz, "Bltz", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBgez) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgez, "Bgez", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgez, "Bgez", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBlez) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Blez, "Blez", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Blez, "Blez", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBgtz) { - BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtz, "Bgtz", /* is_bare */ true); + BranchCondOneRegHelper(&mips64::Mips64Assembler::Bgtz, "Bgtz", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBeq) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beq, "Beq", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Beq, "Beq", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, BareBne) { - BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bne, "Bne", /* is_bare */ true); + BranchCondTwoRegsHelper(&mips64::Mips64Assembler::Bne, "Bne", /* is_bare= */ true); } TEST_F(AssemblerMIPS64Test, LongBeqc) { @@ -1252,7 +1252,7 @@ TEST_F(AssemblerMIPS64Test, Daui) { std::vector<mips64::GpuRegister*> reg1_registers = GetRegisters(); std::vector<mips64::GpuRegister*> reg2_registers = GetRegisters(); reg2_registers.erase(reg2_registers.begin()); // reg2 can't be ZERO, remove it. - std::vector<int64_t> imms = CreateImmediateValuesBits(/* imm_bits */ 16, /* as_uint */ true); + std::vector<int64_t> imms = CreateImmediateValuesBits(/* imm_bits= */ 16, /* as_uint= */ true); WarnOnCombinations(reg1_registers.size() * reg2_registers.size() * imms.size()); std::ostringstream expected; for (mips64::GpuRegister* reg1 : reg1_registers) { diff --git a/compiler/utils/x86/assembler_x86.cc b/compiler/utils/x86/assembler_x86.cc index 2d1e451232..4b073bde0b 100644 --- a/compiler/utils/x86/assembler_x86.cc +++ b/compiler/utils/x86/assembler_x86.cc @@ -2151,7 +2151,7 @@ void X86Assembler::cmpb(const Address& address, const Immediate& imm) { void X86Assembler::cmpw(const Address& address, const Immediate& imm) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); EmitUint8(0x66); - EmitComplex(7, address, imm, /* is_16_op */ true); + EmitComplex(7, address, imm, /* is_16_op= */ true); } @@ -2341,7 +2341,7 @@ void X86Assembler::addw(const Address& address, const Immediate& imm) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); CHECK(imm.is_uint16() || imm.is_int16()) << imm.value(); EmitUint8(0x66); - EmitComplex(0, address, imm, /* is_16_op */ true); + EmitComplex(0, address, imm, /* is_16_op= */ true); } diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc index ae68fe934e..c118bc6fbe 100644 --- a/compiler/utils/x86_64/assembler_x86_64.cc +++ b/compiler/utils/x86_64/assembler_x86_64.cc @@ -2391,7 +2391,7 @@ void X86_64Assembler::cmpw(const Address& address, const Immediate& imm) { CHECK(imm.is_int32()); EmitOperandSizeOverride(); EmitOptionalRex32(address); - EmitComplex(7, address, imm, /* is_16_op */ true); + EmitComplex(7, address, imm, /* is_16_op= */ true); } @@ -2805,7 +2805,7 @@ void X86_64Assembler::addw(const Address& address, const Immediate& imm) { CHECK(imm.is_uint16() || imm.is_int16()) << imm.value(); EmitUint8(0x66); EmitOptionalRex32(address); - EmitComplex(0, address, imm, /* is_16_op */ true); + EmitComplex(0, address, imm, /* is_16_op= */ true); } diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc index 528e037bdc..461f028d9a 100644 --- a/compiler/utils/x86_64/assembler_x86_64_test.cc +++ b/compiler/utils/x86_64/assembler_x86_64_test.cc @@ -2094,7 +2094,7 @@ std::string removeframe_test_fn(JNIMacroAssemblerX86_64Test::Base* assembler_tes ArrayRef<const ManagedRegister> spill_regs(raw_spill_regs); size_t frame_size = 10 * kStackAlignment; - assembler->RemoveFrame(frame_size, spill_regs, /* may_suspend */ true); + assembler->RemoveFrame(frame_size, spill_regs, /* may_suspend= */ true); // Construct assembly text counterpart. std::ostringstream str; |