diff options
Diffstat (limited to 'compiler/optimizing/scheduler_arm64.h')
| -rw-r--r-- | compiler/optimizing/scheduler_arm64.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/compiler/optimizing/scheduler_arm64.h b/compiler/optimizing/scheduler_arm64.h index 0d2f8d9fa0..7f6549dcfe 100644 --- a/compiler/optimizing/scheduler_arm64.h +++ b/compiler/optimizing/scheduler_arm64.h @@ -118,7 +118,7 @@ class SchedulingLatencyVisitorARM64 : public SchedulingLatencyVisitor { M(DataProcWithShifterOp, unused) #define DECLARE_VISIT_INSTRUCTION(type, unused) \ - void Visit##type(H##type* instruction) OVERRIDE; + void Visit##type(H##type* instruction) override; FOR_EACH_SCHEDULED_COMMON_INSTRUCTION(DECLARE_VISIT_INSTRUCTION) FOR_EACH_SCHEDULED_ABSTRACT_INSTRUCTION(DECLARE_VISIT_INSTRUCTION) @@ -136,9 +136,9 @@ class HSchedulerARM64 : public HScheduler { public: explicit HSchedulerARM64(SchedulingNodeSelector* selector) : HScheduler(&arm64_latency_visitor_, selector) {} - ~HSchedulerARM64() OVERRIDE {} + ~HSchedulerARM64() override {} - bool IsSchedulable(const HInstruction* instruction) const OVERRIDE { + bool IsSchedulable(const HInstruction* instruction) const override { #define CASE_INSTRUCTION_KIND(type, unused) case \ HInstruction::InstructionKind::k##type: switch (instruction->GetKind()) { @@ -160,7 +160,7 @@ class HSchedulerARM64 : public HScheduler { // SIMD&FP registers are callee saved) so don't reorder such vector instructions. // // TODO: remove this when a proper support of SIMD registers is introduced to the compiler. - bool IsSchedulingBarrier(const HInstruction* instr) const OVERRIDE { + bool IsSchedulingBarrier(const HInstruction* instr) const override { return HScheduler::IsSchedulingBarrier(instr) || instr->IsVecReduce() || instr->IsVecExtractScalar() || |