diff options
| -rw-r--r-- | compiler/dex/quick/x86/codegen_x86.h | 4 | ||||
| -rwxr-xr-x | compiler/dex/quick/x86/target_x86.cc | 25 |
2 files changed, 18 insertions, 11 deletions
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h index dd4d66105c..6020e70f32 100644 --- a/compiler/dex/quick/x86/codegen_x86.h +++ b/compiler/dex/quick/x86/codegen_x86.h @@ -497,6 +497,8 @@ class X86Mir2Lir : public Mir2Lir { void MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4); void AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir); + virtual void LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, OpSize opsize, + int op_mov); static bool ProvidesFullMemoryBarrier(X86OpCode opcode); @@ -914,7 +916,7 @@ class X86Mir2Lir : public Mir2Lir { * @param bb Basic block containing instruction. * @param mir Instruction to analyze. */ - void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); + virtual void AnalyzeFPInstruction(int opcode, BasicBlock * bb, MIR *mir); /* * @brief Analyze one use of a double operand. diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc index aadb41a37a..bf088aac50 100755 --- a/compiler/dex/quick/x86/target_x86.cc +++ b/compiler/dex/quick/x86/target_x86.cc @@ -2268,6 +2268,20 @@ void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { } } +void X86Mir2Lir::LoadVectorRegister(RegStorage rs_dest, RegStorage rs_src, + OpSize opsize, int op_mov) { + if (!cu_->target64 && opsize == k64) { + // Logic assumes that longs are loaded in GP register pairs. + NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), rs_src.GetLowReg()); + RegStorage r_tmp = AllocTempDouble(); + NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), rs_src.GetHighReg()); + NewLIR2(kX86PunpckldqRR, rs_dest.GetReg(), r_tmp.GetReg()); + FreeTemp(r_tmp); + } else { + NewLIR2(op_mov, rs_dest.GetReg(), rs_src.GetReg()); + } +} + void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); @@ -2321,16 +2335,7 @@ void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { RegStorage reg_to_shuffle = rl_src.reg; // Load the value into the XMM register. - if (!cu_->target64 && opsize == k64) { - // Logic assumes that longs are loaded in GP register pairs. - NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), reg_to_shuffle.GetLowReg()); - RegStorage r_tmp = AllocTempDouble(); - NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), reg_to_shuffle.GetHighReg()); - NewLIR2(kX86PunpckldqRR, rs_dest.GetReg(), r_tmp.GetReg()); - FreeTemp(r_tmp); - } else { - NewLIR2(op_mov, rs_dest.GetReg(), reg_to_shuffle.GetReg()); - } + LoadVectorRegister(rs_dest, reg_to_shuffle, opsize, op_mov); if (opsize == kSignedByte || opsize == kUnsignedByte) { // In the byte case, first duplicate it to be a word |