diff options
| -rw-r--r-- | compiler/optimizing/code_generator_arm.cc | 5 | ||||
| -rw-r--r-- | compiler/optimizing/code_generator_arm64.cc | 5 |
2 files changed, 10 insertions, 0 deletions
diff --git a/compiler/optimizing/code_generator_arm.cc b/compiler/optimizing/code_generator_arm.cc index c283e5a4c1..299350b879 100644 --- a/compiler/optimizing/code_generator_arm.cc +++ b/compiler/optimizing/code_generator_arm.cc @@ -607,7 +607,12 @@ void CodeGeneratorARM::SetupBlockedRegisters(bool is_baseline) const { } blocked_core_registers_[kCoreSavedRegisterForBaseline] = false; + } + if (is_baseline || GetGraph()->IsDebuggable()) { + // Stubs do not save callee-save floating point registers. If the graph + // is debuggable, we need to deal with these registers differently. For + // now, just block them. for (size_t i = 0; i < arraysize(kFpuCalleeSaves); ++i) { blocked_fpu_registers_[kFpuCalleeSaves[i]] = true; } diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc index 39d6db77da..c7ade65cd8 100644 --- a/compiler/optimizing/code_generator_arm64.cc +++ b/compiler/optimizing/code_generator_arm64.cc @@ -864,7 +864,12 @@ void CodeGeneratorARM64::SetupBlockedRegisters(bool is_baseline) const { while (!reserved_core_baseline_registers.IsEmpty()) { blocked_core_registers_[reserved_core_baseline_registers.PopLowestIndex().code()] = true; } + } + if (is_baseline || GetGraph()->IsDebuggable()) { + // Stubs do not save callee-save floating point registers. If the graph + // is debuggable, we need to deal with these registers differently. For + // now, just block them. CPURegList reserved_fp_baseline_registers = callee_saved_fp_registers; while (!reserved_fp_baseline_registers.IsEmpty()) { blocked_fpu_registers_[reserved_fp_baseline_registers.PopLowestIndex().code()] = true; |