diff options
28 files changed, 200 insertions, 143 deletions
diff --git a/compiler/optimizing/load_store_elimination.cc b/compiler/optimizing/load_store_elimination.cc index 9a97f54d54..8eaac0bbd3 100644 --- a/compiler/optimizing/load_store_elimination.cc +++ b/compiler/optimizing/load_store_elimination.cc @@ -61,7 +61,7 @@ class ReferenceInfo : public ArenaObject<kArenaAllocMisc> { (use->IsStaticFieldSet() && (reference_ == use->InputAt(1))) || (use->IsUnresolvedStaticFieldSet() && (reference_ == use->InputAt(0))) || (use->IsArraySet() && (reference_ == use->InputAt(2)))) { - // reference_ is merged to a phi/HSelect, passed to a callee, or stored to heap. + // reference_ is merged to HPhi/HSelect, passed to a callee, or stored to heap. // reference_ isn't the only name that can refer to its value anymore. is_singleton_ = false; is_singleton_and_not_returned_ = false; @@ -458,6 +458,10 @@ class HeapLocationCollector : public HGraphVisitor { CreateReferenceInfoForReferenceType(instruction); } + void VisitSelect(HSelect* instruction) OVERRIDE { + CreateReferenceInfoForReferenceType(instruction); + } + void VisitDeoptimize(HDeoptimize* instruction ATTRIBUTE_UNUSED) OVERRIDE { may_deoptimize_ = true; } diff --git a/compiler/optimizing/register_allocator.cc b/compiler/optimizing/register_allocator.cc index 5cd30adb45..b8d76b912e 100644 --- a/compiler/optimizing/register_allocator.cc +++ b/compiler/optimizing/register_allocator.cc @@ -994,10 +994,6 @@ bool RegisterAllocator::AllocateBlockedReg(LiveInterval* current) { return false; } - // We use the first use to compare with other intervals. If this interval - // is used after any active intervals, we will spill this interval. - size_t first_use = current->FirstUseAfter(current->GetStart()); - // First set all registers as not being used. size_t* next_use = registers_array_; for (size_t i = 0; i < number_of_registers_; ++i) { @@ -1011,7 +1007,7 @@ bool RegisterAllocator::AllocateBlockedReg(LiveInterval* current) { if (active->IsFixed()) { next_use[active->GetRegister()] = current->GetStart(); } else { - size_t use = active->FirstUseAfter(current->GetStart()); + size_t use = active->FirstRegisterUseAfter(current->GetStart()); if (use != kNoLifetime) { next_use[active->GetRegister()] = use; } @@ -1052,16 +1048,16 @@ bool RegisterAllocator::AllocateBlockedReg(LiveInterval* current) { DCHECK(current->IsHighInterval()); reg = current->GetRegister(); // When allocating the low part, we made sure the high register was available. - DCHECK_LT(first_use, next_use[reg]); + DCHECK_LT(first_register_use, next_use[reg]); } else if (current->IsLowInterval()) { - reg = FindAvailableRegisterPair(next_use, first_use); + reg = FindAvailableRegisterPair(next_use, first_register_use); // We should spill if both registers are not available. - should_spill = (first_use >= next_use[reg]) - || (first_use >= next_use[GetHighForLowRegister(reg)]); + should_spill = (first_register_use >= next_use[reg]) + || (first_register_use >= next_use[GetHighForLowRegister(reg)]); } else { DCHECK(!current->IsHighInterval()); reg = FindAvailableRegister(next_use, current); - should_spill = (first_use >= next_use[reg]); + should_spill = (first_register_use >= next_use[reg]); } DCHECK_NE(reg, kNoRegister); diff --git a/runtime/art_method-inl.h b/runtime/art_method-inl.h index 28540c8437..cc45c385b8 100644 --- a/runtime/art_method-inl.h +++ b/runtime/art_method-inl.h @@ -463,9 +463,11 @@ void ArtMethod::VisitRoots(RootVisitorType& visitor, size_t pointer_size) { } visitor.VisitRootIfNonNull(declaring_class_.AddressWithoutBarrier()); - ProfilingInfo* profiling_info = GetProfilingInfo(pointer_size); - if (hotness_count_ != 0 && !IsNative() && profiling_info != nullptr) { - profiling_info->VisitRoots(visitor); + if (!IsNative()) { + ProfilingInfo* profiling_info = GetProfilingInfo(pointer_size); + if (profiling_info != nullptr) { + profiling_info->VisitRoots(visitor); + } } } diff --git a/runtime/interpreter/mterp/arm/binopWide.S b/runtime/interpreter/mterp/arm/binopWide.S index 57d43c651a..1d511ecfb0 100644 --- a/runtime/interpreter/mterp/arm/binopWide.S +++ b/runtime/interpreter/mterp/arm/binopWide.S @@ -16,10 +16,10 @@ */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -28,8 +28,8 @@ orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes $instr @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST diff --git a/runtime/interpreter/mterp/arm/binopWide2addr.S b/runtime/interpreter/mterp/arm/binopWide2addr.S index 4e855f2d16..81db48bade 100644 --- a/runtime/interpreter/mterp/arm/binopWide2addr.S +++ b/runtime/interpreter/mterp/arm/binopWide2addr.S @@ -15,17 +15,17 @@ */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if $chkzero orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - $preinstr @ optional op; may set condition codes $instr @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST diff --git a/runtime/interpreter/mterp/arm/fbinopWide.S b/runtime/interpreter/mterp/arm/fbinopWide.S index 1bed817824..ca13bfbab6 100644 --- a/runtime/interpreter/mterp/arm/fbinopWide.S +++ b/runtime/interpreter/mterp/arm/fbinopWide.S @@ -14,9 +14,9 @@ VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB fldd d1, [r3] @ d1<- vCC fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST $instr @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA fstd d2, [r9] @ vAA<- d2 diff --git a/runtime/interpreter/mterp/arm/fbinopWide2addr.S b/runtime/interpreter/mterp/arm/fbinopWide2addr.S index 9f56986db8..4e7401dae3 100644 --- a/runtime/interpreter/mterp/arm/fbinopWide2addr.S +++ b/runtime/interpreter/mterp/arm/fbinopWide2addr.S @@ -12,10 +12,10 @@ VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB and r9, r9, #15 @ r9<- A fldd d1, [r3] @ d1<- vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA FETCH_ADVANCE_INST 1 @ advance rPC, load rINST fldd d0, [r9] @ d0<- vA - $instr @ d2<- op GET_INST_OPCODE ip @ extract opcode from rINST fstd d2, [r9] @ vAA<- d2 diff --git a/runtime/interpreter/mterp/arm/funopWider.S b/runtime/interpreter/mterp/arm/funopWider.S index 087a1f2faf..450ba3a157 100644 --- a/runtime/interpreter/mterp/arm/funopWider.S +++ b/runtime/interpreter/mterp/arm/funopWider.S @@ -12,6 +12,7 @@ FETCH_ADVANCE_INST 1 @ advance rPC, load rINST and r9, r9, #15 @ r9<- A $instr @ d0<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA fstd d0, [r9] @ vA<- d0 diff --git a/runtime/interpreter/mterp/arm/header.S b/runtime/interpreter/mterp/arm/header.S index 14319d953f..b2370bffb4 100644 --- a/runtime/interpreter/mterp/arm/header.S +++ b/runtime/interpreter/mterp/arm/header.S @@ -263,6 +263,19 @@ unspecified registers or condition codes. str \reg, [rFP, \vreg, lsl #2] str \reg, [rREFS, \vreg, lsl #2] .endm +.macro SET_VREG_SHADOW reg, vreg + str \reg, [rREFS, \vreg, lsl #2] +.endm + +/* + * Clear the corresponding shadow regs for a vreg pair + */ +.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 + mov \tmp1, #0 + add \tmp2, \vreg, #1 + SET_VREG_SHADOW \tmp1, \vreg + SET_VREG_SHADOW \tmp1, \tmp2 +.endm /* * Convert a virtual register index into an address. diff --git a/runtime/interpreter/mterp/arm/op_aget_wide.S b/runtime/interpreter/mterp/arm/op_aget_wide.S index caaec71d02..e1430b44f2 100644 --- a/runtime/interpreter/mterp/arm/op_aget_wide.S +++ b/runtime/interpreter/mterp/arm/op_aget_wide.S @@ -10,6 +10,7 @@ mov r3, r0, lsr #8 @ r3<- CC GET_VREG r0, r2 @ r0<- vBB (array object) GET_VREG r1, r3 @ r1<- vCC (requested index) + CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs cmp r0, #0 @ null array object? beq common_errNullObject @ yes, bail ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length diff --git a/runtime/interpreter/mterp/arm/op_const_wide.S b/runtime/interpreter/mterp/arm/op_const_wide.S index 2cdc4261e6..12394b6cbe 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide.S +++ b/runtime/interpreter/mterp/arm/op_const_wide.S @@ -6,6 +6,7 @@ FETCH r3, 4 @ r3<- HHHH (high) mov r9, rINST, lsr #8 @ r9<- AA orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) + CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs FETCH_ADVANCE_INST 5 @ advance rPC, load rINST add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] GET_INST_OPCODE ip @ extract opcode from rINST diff --git a/runtime/interpreter/mterp/arm/op_const_wide_16.S b/runtime/interpreter/mterp/arm/op_const_wide_16.S index 56bfc17a91..3811d8641b 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide_16.S +++ b/runtime/interpreter/mterp/arm/op_const_wide_16.S @@ -3,6 +3,7 @@ mov r3, rINST, lsr #8 @ r3<- AA mov r1, r0, asr #31 @ r1<- ssssssss FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] GET_INST_OPCODE ip @ extract opcode from rINST stmia r3, {r0-r1} @ vAA<- r0/r1 diff --git a/runtime/interpreter/mterp/arm/op_const_wide_32.S b/runtime/interpreter/mterp/arm/op_const_wide_32.S index 36d4628502..0b6f1cc384 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide_32.S +++ b/runtime/interpreter/mterp/arm/op_const_wide_32.S @@ -4,6 +4,7 @@ FETCH_S r2, 2 @ r2<- ssssBBBB (high) FETCH_ADVANCE_INST 3 @ advance rPC, load rINST orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] mov r1, r0, asr #31 @ r1<- ssssssss GET_INST_OPCODE ip @ extract opcode from rINST diff --git a/runtime/interpreter/mterp/arm/op_const_wide_high16.S b/runtime/interpreter/mterp/arm/op_const_wide_high16.S index bee592d16b..b9796eb561 100644 --- a/runtime/interpreter/mterp/arm/op_const_wide_high16.S +++ b/runtime/interpreter/mterp/arm/op_const_wide_high16.S @@ -4,6 +4,7 @@ mov r0, #0 @ r0<- 00000000 mov r1, r1, lsl #16 @ r1<- BBBB0000 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] GET_INST_OPCODE ip @ extract opcode from rINST stmia r3, {r0-r1} @ vAA<- r0/r1 diff --git a/runtime/interpreter/mterp/arm/op_iget_wide.S b/runtime/interpreter/mterp/arm/op_iget_wide.S index f8d2f41dea..859ffac038 100644 --- a/runtime/interpreter/mterp/arm/op_iget_wide.S +++ b/runtime/interpreter/mterp/arm/op_iget_wide.S @@ -15,8 +15,9 @@ PREFETCH_INST 2 cmp r3, #0 bne MterpException @ bail out - add r3, rFP, r2, lsl #2 @ r3<- &fp[A] - stmia r3, {r0-r1} @ fp[A]<- r0/r1 + CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs + add r3, rFP, r2, lsl #2 @ r3<- &fp[A] + stmia r3, {r0-r1} @ fp[A]<- r0/r1 ADVANCE 2 GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S index 4d6976e085..07f854adf4 100644 --- a/runtime/interpreter/mterp/arm/op_iget_wide_quick.S +++ b/runtime/interpreter/mterp/arm/op_iget_wide_quick.S @@ -8,6 +8,7 @@ ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) FETCH_ADVANCE_INST 2 @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] + CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs GET_INST_OPCODE ip @ extract opcode from rINST stmia r3, {r0-r1} @ fp[A]<- r0/r1 GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_result_wide.S b/runtime/interpreter/mterp/arm/op_move_result_wide.S index c64103c391..1845ccf69f 100644 --- a/runtime/interpreter/mterp/arm/op_move_result_wide.S +++ b/runtime/interpreter/mterp/arm/op_move_result_wide.S @@ -1,8 +1,9 @@ /* move-result-wide vAA */ - mov r2, rINST, lsr #8 @ r2<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] - add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] + add r2, rFP, rINST, lsl #2 @ r2<- &fp[AA] ldmia r3, {r0-r1} @ r0/r1<- retval.j + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST stmia r2, {r0-r1} @ fp[AA]<- r0/r1 GET_INST_OPCODE ip @ extract opcode from rINST diff --git a/runtime/interpreter/mterp/arm/op_move_wide.S b/runtime/interpreter/mterp/arm/op_move_wide.S index 1345b95fa7..f5d156d732 100644 --- a/runtime/interpreter/mterp/arm/op_move_wide.S +++ b/runtime/interpreter/mterp/arm/op_move_wide.S @@ -1,10 +1,11 @@ /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r2, rINST, #8, #4 @ r2<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r2, rFP, r2, lsl #2 @ r2<- &fp[A] + add r2, rFP, rINST, lsl #2 @ r2<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- fp[B] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST GET_INST_OPCODE ip @ extract opcode from rINST stmia r2, {r0-r1} @ fp[A]<- r0/r1 diff --git a/runtime/interpreter/mterp/arm/op_move_wide_16.S b/runtime/interpreter/mterp/arm/op_move_wide_16.S index 133a4c36ba..8a55c4b13b 100644 --- a/runtime/interpreter/mterp/arm/op_move_wide_16.S +++ b/runtime/interpreter/mterp/arm/op_move_wide_16.S @@ -3,9 +3,10 @@ FETCH r3, 2 @ r3<- BBBB FETCH r2, 1 @ r2<- AAAA add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] - add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] + add lr, rFP, r2, lsl #2 @ r2<- &fp[AAAA] ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 + CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs + stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/op_move_wide_from16.S b/runtime/interpreter/mterp/arm/op_move_wide_from16.S index f2ae785032..b65259db50 100644 --- a/runtime/interpreter/mterp/arm/op_move_wide_from16.S +++ b/runtime/interpreter/mterp/arm/op_move_wide_from16.S @@ -1,10 +1,11 @@ /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH r3, 1 @ r3<- BBBB - mov r2, rINST, lsr #8 @ r2<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] - add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] + add r2, rFP, rINST, lsl #2 @ r2<- &fp[AA] ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST GET_INST_OPCODE ip @ extract opcode from rINST stmia r2, {r0-r1} @ fp[AA]<- r0/r1 diff --git a/runtime/interpreter/mterp/arm/op_sget_wide.S b/runtime/interpreter/mterp/arm/op_sget_wide.S index 97db05f596..3a5090866a 100644 --- a/runtime/interpreter/mterp/arm/op_sget_wide.S +++ b/runtime/interpreter/mterp/arm/op_sget_wide.S @@ -12,10 +12,11 @@ bl artGet64StaticFromCode ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] mov r9, rINST, lsr #8 @ r9<- AA - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add lr, rFP, r9, lsl #2 @ r9<- &fp[AA] cmp r3, #0 @ Fail to resolve? bne MterpException @ bail out FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + CLEAR_SHADOW_PAIR r9, r2, ip @ Zero out the shadow regs + stmia lr, {r0-r1} @ vAA/vAA+1<- r0/r1 GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction diff --git a/runtime/interpreter/mterp/arm/unopWide.S b/runtime/interpreter/mterp/arm/unopWide.S index 7b8739cb92..a07423468d 100644 --- a/runtime/interpreter/mterp/arm/unopWide.S +++ b/runtime/interpreter/mterp/arm/unopWide.S @@ -8,10 +8,11 @@ */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST $preinstr @ optional op; may set condition codes $instr @ r0/r1<- op, r2-r3 changed diff --git a/runtime/interpreter/mterp/arm/unopWider.S b/runtime/interpreter/mterp/arm/unopWider.S index 657a3956e5..23b6b9d2f5 100644 --- a/runtime/interpreter/mterp/arm/unopWider.S +++ b/runtime/interpreter/mterp/arm/unopWider.S @@ -8,10 +8,11 @@ */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A GET_VREG r0, r3 @ r0<- vB - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] $preinstr @ optional op; may set condition codes + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST $instr @ r0<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S index 78c784b773..ee195598db 100644 --- a/runtime/interpreter/mterp/out/mterp_arm.S +++ b/runtime/interpreter/mterp/out/mterp_arm.S @@ -270,6 +270,19 @@ unspecified registers or condition codes. str \reg, [rFP, \vreg, lsl #2] str \reg, [rREFS, \vreg, lsl #2] .endm +.macro SET_VREG_SHADOW reg, vreg + str \reg, [rREFS, \vreg, lsl #2] +.endm + +/* + * Clear the corresponding shadow regs for a vreg pair + */ +.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 + mov \tmp1, #0 + add \tmp2, \vreg, #1 + SET_VREG_SHADOW \tmp1, \vreg + SET_VREG_SHADOW \tmp1, \tmp2 +.endm /* * Convert a virtual register index into an address. @@ -426,10 +439,11 @@ artMterpAsmInstructionStart = .L_op_nop /* move-wide vA, vB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r2, rINST, #8, #4 @ r2<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r2, rFP, r2, lsl #2 @ r2<- &fp[A] + add r2, rFP, rINST, lsl #2 @ r2<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- fp[B] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST GET_INST_OPCODE ip @ extract opcode from rINST stmia r2, {r0-r1} @ fp[A]<- r0/r1 @@ -442,10 +456,11 @@ artMterpAsmInstructionStart = .L_op_nop /* move-wide/from16 vAA, vBBBB */ /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ FETCH r3, 1 @ r3<- BBBB - mov r2, rINST, lsr #8 @ r2<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] - add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] + add r2, rFP, rINST, lsl #2 @ r2<- &fp[AA] ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST GET_INST_OPCODE ip @ extract opcode from rINST stmia r2, {r0-r1} @ fp[AA]<- r0/r1 @@ -460,10 +475,11 @@ artMterpAsmInstructionStart = .L_op_nop FETCH r3, 2 @ r3<- BBBB FETCH r2, 1 @ r2<- AAAA add r3, rFP, r3, lsl #2 @ r3<- &fp[BBBB] - add r2, rFP, r2, lsl #2 @ r2<- &fp[AAAA] + add lr, rFP, r2, lsl #2 @ r2<- &fp[AAAA] ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] FETCH_ADVANCE_INST 3 @ advance rPC, load rINST - stmia r2, {r0-r1} @ fp[AAAA]<- r0/r1 + CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs + stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction @@ -550,10 +566,11 @@ artMterpAsmInstructionStart = .L_op_nop .L_op_move_result_wide: /* 0x0b */ /* File: arm/op_move_result_wide.S */ /* move-result-wide vAA */ - mov r2, rINST, lsr #8 @ r2<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] - add r2, rFP, r2, lsl #2 @ r2<- &fp[AA] + add r2, rFP, rINST, lsl #2 @ r2<- &fp[AA] ldmia r3, {r0-r1} @ r0/r1<- retval.j + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST stmia r2, {r0-r1} @ fp[AA]<- r0/r1 GET_INST_OPCODE ip @ extract opcode from rINST @@ -731,6 +748,7 @@ artMterpAsmInstructionStart = .L_op_nop mov r3, rINST, lsr #8 @ r3<- AA mov r1, r0, asr #31 @ r1<- ssssssss FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] GET_INST_OPCODE ip @ extract opcode from rINST stmia r3, {r0-r1} @ vAA<- r0/r1 @@ -746,6 +764,7 @@ artMterpAsmInstructionStart = .L_op_nop FETCH_S r2, 2 @ r2<- ssssBBBB (high) FETCH_ADVANCE_INST 3 @ advance rPC, load rINST orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb + CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] mov r1, r0, asr #31 @ r1<- ssssssss GET_INST_OPCODE ip @ extract opcode from rINST @@ -764,6 +783,7 @@ artMterpAsmInstructionStart = .L_op_nop FETCH r3, 4 @ r3<- HHHH (high) mov r9, rINST, lsr #8 @ r9<- AA orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) + CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs FETCH_ADVANCE_INST 5 @ advance rPC, load rINST add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] GET_INST_OPCODE ip @ extract opcode from rINST @@ -780,6 +800,7 @@ artMterpAsmInstructionStart = .L_op_nop mov r0, #0 @ r0<- 00000000 mov r1, r1, lsl #16 @ r1<- BBBB0000 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST + CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs add r3, rFP, r3, lsl #2 @ r3<- &fp[AA] GET_INST_OPCODE ip @ extract opcode from rINST stmia r3, {r0-r1} @ vAA<- r0/r1 @@ -2068,6 +2089,7 @@ artMterpAsmInstructionStart = .L_op_nop mov r3, r0, lsr #8 @ r3<- CC GET_VREG r0, r2 @ r0<- vBB (array object) GET_VREG r1, r3 @ r1<- vCC (requested index) + CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs cmp r0, #0 @ null array object? beq common_errNullObject @ yes, bail ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length @@ -2519,8 +2541,9 @@ artMterpAsmInstructionStart = .L_op_nop PREFETCH_INST 2 cmp r3, #0 bne MterpException @ bail out - add r3, rFP, r2, lsl #2 @ r3<- &fp[A] - stmia r3, {r0-r1} @ fp[A]<- r0/r1 + CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs + add r3, rFP, r2, lsl #2 @ r3<- &fp[A] + stmia r3, {r0-r1} @ fp[A]<- r0/r1 ADVANCE 2 GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction @@ -2909,11 +2932,12 @@ artMterpAsmInstructionStart = .L_op_nop bl artGet64StaticFromCode ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] mov r9, rINST, lsr #8 @ r9<- AA - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add lr, rFP, r9, lsl #2 @ r9<- &fp[AA] cmp r3, #0 @ Fail to resolve? bne MterpException @ bail out FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 + CLEAR_SHADOW_PAIR r9, r2, ip @ Zero out the shadow regs + stmia lr, {r0-r1} @ vAA/vAA+1<- r0/r1 GET_INST_OPCODE ip @ extract opcode from rINST GOTO_OPCODE ip @ jump to next instruction @@ -3622,10 +3646,11 @@ artMterpAsmInstructionStart = .L_op_nop */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST rsbs r0, r0, #0 @ optional op; may set condition codes rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed @@ -3649,10 +3674,11 @@ artMterpAsmInstructionStart = .L_op_nop */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST mvn r0, r0 @ optional op; may set condition codes mvn r1, r1 @ r0/r1<- op, r2-r3 changed @@ -3702,10 +3728,11 @@ artMterpAsmInstructionStart = .L_op_nop */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST @ optional op; may set condition codes add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed @@ -3729,10 +3756,11 @@ artMterpAsmInstructionStart = .L_op_nop */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A GET_VREG r0, r3 @ r0<- vB - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] @ optional op; may set condition codes + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST mov r1, r0, asr #31 @ r0<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -3785,6 +3813,7 @@ artMterpAsmInstructionStart = .L_op_nop FETCH_ADVANCE_INST 1 @ advance rPC, load rINST and r9, r9, #15 @ r9<- A fsitod d0, s0 @ d0<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA fstd d0, [r9] @ vA<- d0 @@ -3912,10 +3941,11 @@ constvalop_long_to_double: */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A GET_VREG r0, r3 @ r0<- vB - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] @ optional op; may set condition codes + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST bl f2l_doconv @ r0<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -3944,6 +3974,7 @@ constvalop_long_to_double: FETCH_ADVANCE_INST 1 @ advance rPC, load rINST and r9, r9, #15 @ r9<- A fcvtds d0, s0 @ d0<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA fstd d0, [r9] @ vA<- d0 @@ -3990,10 +4021,11 @@ constvalop_long_to_double: */ /* unop vA, vB */ mov r3, rINST, lsr #12 @ r3<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r3, rFP, r3, lsl #2 @ r3<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r3, {r0-r1} @ r0/r1<- vAA + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST @ optional op; may set condition codes bl d2l_doconv @ r0/r1<- op, r2-r3 changed @@ -4570,10 +4602,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4582,8 +4614,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - adds r0, r0, r2 @ optional op; may set condition codes adc r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -4614,10 +4646,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4626,8 +4658,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - subs r0, r0, r2 @ optional op; may set condition codes sbc r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -4699,10 +4731,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4711,8 +4743,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes bl __aeabi_ldivmod @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -4744,10 +4776,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4756,8 +4788,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes bl __aeabi_ldivmod @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -4788,10 +4820,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4800,8 +4832,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - and r0, r0, r2 @ optional op; may set condition codes and r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -4832,10 +4864,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4844,8 +4876,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - orr r0, r0, r2 @ optional op; may set condition codes orr r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -4876,10 +4908,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -4888,8 +4920,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - eor r0, r0, r2 @ optional op; may set condition codes eor r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5177,9 +5209,9 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB fldd d1, [r3] @ d1<- vCC fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST faddd d2, d0, d1 @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA fstd d2, [r9] @ vAA<- d2 @@ -5207,9 +5239,9 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB fldd d1, [r3] @ d1<- vCC fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST fsubd d2, d0, d1 @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA fstd d2, [r9] @ vAA<- d2 @@ -5237,9 +5269,9 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB fldd d1, [r3] @ d1<- vCC fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST fmuld d2, d0, d1 @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA fstd d2, [r9] @ vAA<- d2 @@ -5267,9 +5299,9 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB fldd d1, [r3] @ d1<- vCC fldd d0, [r2] @ d0<- vBB - FETCH_ADVANCE_INST 2 @ advance rPC, load rINST fdivd d2, d0, d1 @ s2<- op + CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs GET_INST_OPCODE ip @ extract opcode from rINST VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA fstd d2, [r9] @ vAA<- d2 @@ -5299,10 +5331,10 @@ constvalop_long_to_double: */ /* binop vAA, vBB, vCC */ FETCH r0, 1 @ r0<- CCBB - mov r9, rINST, lsr #8 @ r9<- AA + mov rINST, rINST, lsr #8 @ rINST<- AA and r2, r0, #255 @ r2<- BB mov r3, r0, lsr #8 @ r3<- CC - add r9, rFP, r9, lsl #2 @ r9<- &fp[AA] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[AA] add r2, rFP, r2, lsl #2 @ r2<- &fp[BB] add r3, rFP, r3, lsl #2 @ r3<- &fp[CC] ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 @@ -5311,8 +5343,8 @@ constvalop_long_to_double: orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs FETCH_ADVANCE_INST 2 @ advance rPC, load rINST - @ optional op; may set condition codes bl fmod @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5754,17 +5786,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 0 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - adds r0, r0, r2 @ optional op; may set condition codes adc r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5794,17 +5826,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 0 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - subs r0, r0, r2 @ optional op; may set condition codes sbc r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5863,17 +5895,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 1 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes bl __aeabi_ldivmod @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5904,17 +5936,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 1 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes bl __aeabi_ldivmod @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5944,17 +5976,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 0 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - and r0, r0, r2 @ optional op; may set condition codes and r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -5984,17 +6016,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 0 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - orr r0, r0, r2 @ optional op; may set condition codes orr r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -6024,17 +6056,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 0 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - eor r0, r0, r2 @ optional op; may set condition codes eor r1, r1, r3 @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -6294,10 +6326,10 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB and r9, r9, #15 @ r9<- A fldd d1, [r3] @ d1<- vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA FETCH_ADVANCE_INST 1 @ advance rPC, load rINST fldd d0, [r9] @ d0<- vA - faddd d2, d0, d1 @ d2<- op GET_INST_OPCODE ip @ extract opcode from rINST fstd d2, [r9] @ vAA<- d2 @@ -6323,10 +6355,10 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB and r9, r9, #15 @ r9<- A fldd d1, [r3] @ d1<- vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA FETCH_ADVANCE_INST 1 @ advance rPC, load rINST fldd d0, [r9] @ d0<- vA - fsubd d2, d0, d1 @ d2<- op GET_INST_OPCODE ip @ extract opcode from rINST fstd d2, [r9] @ vAA<- d2 @@ -6352,10 +6384,10 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB and r9, r9, #15 @ r9<- A fldd d1, [r3] @ d1<- vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA FETCH_ADVANCE_INST 1 @ advance rPC, load rINST fldd d0, [r9] @ d0<- vA - fmuld d2, d0, d1 @ d2<- op GET_INST_OPCODE ip @ extract opcode from rINST fstd d2, [r9] @ vAA<- d2 @@ -6381,10 +6413,10 @@ constvalop_long_to_double: VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB and r9, r9, #15 @ r9<- A fldd d1, [r3] @ d1<- vB + CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA FETCH_ADVANCE_INST 1 @ advance rPC, load rINST fldd d0, [r9] @ d0<- vA - fdivd d2, d0, d1 @ d2<- op GET_INST_OPCODE ip @ extract opcode from rINST fstd d2, [r9] @ vAA<- d2 @@ -6413,17 +6445,17 @@ constvalop_long_to_double: */ /* binop/2addr vA, vB */ mov r1, rINST, lsr #12 @ r1<- B - ubfx r9, rINST, #8, #4 @ r9<- A + ubfx rINST, rINST, #8, #4 @ rINST<- A add r1, rFP, r1, lsl #2 @ r1<- &fp[B] - add r9, rFP, r9, lsl #2 @ r9<- &fp[A] + add r9, rFP, rINST, lsl #2 @ r9<- &fp[A] ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 .if 0 orrs ip, r2, r3 @ second arg (r2-r3) is zero? beq common_errDivideByZero .endif + CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs FETCH_ADVANCE_INST 1 @ advance rPC, load rINST - @ optional op; may set condition codes bl fmod @ result<- op, r0-r3 changed GET_INST_OPCODE ip @ extract opcode from rINST @@ -7155,6 +7187,7 @@ constvalop_long_to_double: ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) FETCH_ADVANCE_INST 2 @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] + CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs GET_INST_OPCODE ip @ extract opcode from rINST stmia r3, {r0-r1} @ fp[A]<- r0/r1 GOTO_OPCODE ip @ jump to next instruction diff --git a/test/530-checker-lse/src/Main.java b/test/530-checker-lse/src/Main.java index d647683869..4d6ea06fe0 100644 --- a/test/530-checker-lse/src/Main.java +++ b/test/530-checker-lse/src/Main.java @@ -664,28 +664,19 @@ public class Main { System.out.println("testFinalizableByForcingGc() failed to force gc."); } - /// CHECK-START: int Main.testHSelect(boolean) load_store_elimination (before) + /// CHECK-START: int Main.$noinline$testHSelect(boolean) load_store_elimination (before) /// CHECK: InstanceFieldSet /// CHECK: Select - /// CHECK-START: int Main.testHSelect(boolean) load_store_elimination (after) + /// CHECK-START: int Main.$noinline$testHSelect(boolean) load_store_elimination (after) /// CHECK: InstanceFieldSet /// CHECK: Select // Test that HSelect creates alias. - public static int testHSelect(boolean b) { - // Disable inlining. - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - System.out.print(""); - + public static int $noinline$testHSelect(boolean b) { + if (sFlag) { + throw new Error(); + } TestClass obj = new TestClass(); TestClass obj2 = null; obj.i = 0xdead; @@ -754,6 +745,8 @@ public class Main { assertIntEquals(test23(false), 5); assertFloatEquals(test24(), 8.0f); testFinalizableByForcingGc(); - assertIntEquals(testHSelect(true), 0xdead); + assertIntEquals($noinline$testHSelect(true), 0xdead); } + + static boolean sFlag; } diff --git a/test/572-checker-array-get-regression/expected.txt b/test/572-checker-array-get-regression/expected.txt index c08d7831c0..f7d1ad4743 100644 --- a/test/572-checker-array-get-regression/expected.txt +++ b/test/572-checker-array-get-regression/expected.txt @@ -1 +1 @@ -1048575 +524287 diff --git a/test/572-checker-array-get-regression/info.txt b/test/572-checker-array-get-regression/info.txt index 023d5b0c19..d06feee152 100644 --- a/test/572-checker-array-get-regression/info.txt +++ b/test/572-checker-array-get-regression/info.txt @@ -1,3 +1,3 @@ Regression test for the ARM64 Baker's read barrier fast path compiler -instrumentatin of array loads with a large constant index, where we +instrumentation of array loads with a large constant index, where we used to require too many scratch (temporary) registers. diff --git a/test/572-checker-array-get-regression/src/Main.java b/test/572-checker-array-get-regression/src/Main.java index 139221555a..a9bf326427 100644 --- a/test/572-checker-array-get-regression/src/Main.java +++ b/test/572-checker-array-get-regression/src/Main.java @@ -22,9 +22,9 @@ public class Main { /// CHECK-START: java.lang.Integer Main.test() ssa_builder (after) /// CHECK-DAG: <<Method:[ij]\d+>> CurrentMethod - /// CHECK-DAG: <<Const2P20:i\d+>> IntConstant 1048576 + /// CHECK-DAG: <<Const2P19:i\d+>> IntConstant 524288 /// CHECK-DAG: <<ConstM1:i\d+>> IntConstant -1 - /// CHECK-DAG: <<Array:l\d+>> NewArray [<<Const2P20>>,<<Method>>] + /// CHECK-DAG: <<Array:l\d+>> NewArray [<<Const2P19>>,<<Method>>] /// CHECK-DAG: <<NullCheck1:l\d+>> NullCheck [<<Array>>] /// CHECK-DAG: <<Length1:i\d+>> ArrayLength [<<NullCheck1>>] /// CHECK-DAG: <<Index:i\d+>> Add [<<Length1>>,<<ConstM1>>] @@ -34,16 +34,17 @@ public class Main { /// CHECK-DAG: <<LastElement:l\d+>> ArrayGet [<<NullCheck2>>,<<BoundsCheck>>] /// CHECK-DAG: Return [<<LastElement>>] + /// CHECK-START: java.lang.Integer Main.test() register (before) /// CHECK-DAG: <<Method:[ij]\d+>> CurrentMethod - /// CHECK-DAG: <<Const2P20:i\d+>> IntConstant 1048576 - /// CHECK-DAG: <<Const2P20M1:i\d+>> IntConstant 1048575 - /// CHECK-DAG: <<Array:l\d+>> NewArray [<<Const2P20>>,<<Method>>] - /// CHECK-DAG: <<LastElement:l\d+>> ArrayGet [<<Array>>,<<Const2P20M1>>] + /// CHECK-DAG: <<Const2P19:i\d+>> IntConstant 524288 + /// CHECK-DAG: <<Const2P19M1:i\d+>> IntConstant 524287 + /// CHECK-DAG: <<Array:l\d+>> NewArray [<<Const2P19>>,<<Method>>] + /// CHECK-DAG: <<LastElement:l\d+>> ArrayGet [<<Array>>,<<Const2P19M1>>] /// CHECK-DAG: Return [<<LastElement>>] public static Integer test() { - Integer[] integers = new Integer[1024 * 1024]; + Integer[] integers = new Integer[1 << 19]; initIntegerArray(integers); // Array load with a large constant index (after constant folding // and bounds check elimination). |