diff options
161 files changed, 7154 insertions, 478 deletions
diff --git a/build/Android.common.mk b/build/Android.common.mk index 00962f568e..1f040d69e3 100644 --- a/build/Android.common.mk +++ b/build/Android.common.mk @@ -17,7 +17,7 @@ ifndef ART_ANDROID_COMMON_MK ART_ANDROID_COMMON_MK = true -ART_TARGET_SUPPORTED_ARCH := arm arm64 mips x86 x86_64 +ART_TARGET_SUPPORTED_ARCH := arm arm64 mips mips64 x86 x86_64 ART_HOST_SUPPORTED_ARCH := x86 x86_64 ifeq (,$(filter $(TARGET_ARCH),$(ART_TARGET_SUPPORTED_ARCH))) diff --git a/build/Android.common_build.mk b/build/Android.common_build.mk index 086f298df6..cd9ed5004c 100644 --- a/build/Android.common_build.mk +++ b/build/Android.common_build.mk @@ -95,6 +95,7 @@ ART_TARGET_CLANG_arm := ART_TARGET_CLANG_arm64 := # TODO: Enable clang mips when b/18807290 and b/18789639 are fixed. ART_TARGET_CLANG_mips := false +ART_TARGET_CLANG_mips64 := false ART_TARGET_CLANG_x86 := ART_TARGET_CLANG_x86_64 := @@ -110,6 +111,7 @@ ART_TARGET_CLANG_CFLAGS := ART_TARGET_CLANG_CFLAGS_arm := ART_TARGET_CLANG_CFLAGS_arm64 := ART_TARGET_CLANG_CFLAGS_mips := +ART_TARGET_CLANG_CFLAGS_mips64 := ART_TARGET_CLANG_CFLAGS_x86 := ART_TARGET_CLANG_CFLAGS_x86_64 := diff --git a/build/Android.gtest.mk b/build/Android.gtest.mk index 8180ce8638..efb45c7128 100644 --- a/build/Android.gtest.mk +++ b/build/Android.gtest.mk @@ -90,6 +90,7 @@ RUNTIME_GTEST_COMMON_SRC_FILES := \ runtime/arch/arm/instruction_set_features_arm_test.cc \ runtime/arch/arm64/instruction_set_features_arm64_test.cc \ runtime/arch/mips/instruction_set_features_mips_test.cc \ + runtime/arch/mips64/instruction_set_features_mips64_test.cc \ runtime/arch/x86/instruction_set_features_x86_test.cc \ runtime/arch/x86_64/instruction_set_features_x86_64_test.cc \ runtime/barrier_test.cc \ diff --git a/cmdline/cmdline.h b/cmdline/cmdline.h index 30012d0978..2967e27d8f 100644 --- a/cmdline/cmdline.h +++ b/cmdline/cmdline.h @@ -196,7 +196,7 @@ struct CmdlineArgs { " Example: --boot-image=/system/framework/boot.art\n" "\n"; usage += StringPrintf( // Optional. - " --instruction-set=(arm|arm64|mips|x86|x86_64): for locating the image\n" + " --instruction-set=(arm|arm64|mips|mips64|x86|x86_64): for locating the image\n" " file based on the image location set.\n" " Example: --instruction-set=x86\n" " Default: %s\n" diff --git a/compiler/Android.mk b/compiler/Android.mk index db338f0538..f2f4550f05 100644 --- a/compiler/Android.mk +++ b/compiler/Android.mk @@ -98,6 +98,8 @@ LIBART_COMPILER_SRC_FILES := \ optimizing/gvn.cc \ optimizing/inliner.cc \ optimizing/instruction_simplifier.cc \ + optimizing/intrinsics.cc \ + optimizing/intrinsics_x86_64.cc \ optimizing/locations.cc \ optimizing/nodes.cc \ optimizing/optimization.cc \ @@ -122,6 +124,8 @@ LIBART_COMPILER_SRC_FILES := \ utils/dwarf_cfi.cc \ utils/mips/assembler_mips.cc \ utils/mips/managed_register_mips.cc \ + utils/mips64/assembler_mips64.cc \ + utils/mips64/managed_register_mips64.cc \ utils/x86/assembler_x86.cc \ utils/x86/managed_register_x86.cc \ utils/x86_64/assembler_x86_64.cc \ diff --git a/compiler/common_compiler_test.cc b/compiler/common_compiler_test.cc index 7df71f5b8a..96f8e0c355 100644 --- a/compiler/common_compiler_test.cc +++ b/compiler/common_compiler_test.cc @@ -164,7 +164,7 @@ void CommonCompilerTest::SetUp() { compiler_kind, instruction_set, instruction_set_features_.get(), true, new std::set<std::string>, nullptr, - 2, true, true, timer_.get(), -1, "")); + 2, true, true, "", timer_.get(), -1, "")); } // We typically don't generate an image in unit tests, disable this optimization by default. compiler_driver_->SetSupportBootImageFixup(false); diff --git a/compiler/compiled_method.cc b/compiler/compiled_method.cc index 234e8b96f6..22be28c4d9 100644 --- a/compiler/compiled_method.cc +++ b/compiler/compiled_method.cc @@ -63,6 +63,7 @@ size_t CompiledCode::CodeDelta(InstructionSet instruction_set) { case kArm: case kArm64: case kMips: + case kMips64: case kX86: case kX86_64: return 0; @@ -82,6 +83,7 @@ const void* CompiledCode::CodePointer(const void* code_pointer, case kArm: case kArm64: case kMips: + case kMips64: case kX86: case kX86_64: return code_pointer; diff --git a/compiler/dex/quick/dex_file_method_inliner.cc b/compiler/dex/quick/dex_file_method_inliner.cc index 30398527cd..84c0d93008 100644 --- a/compiler/dex/quick/dex_file_method_inliner.cc +++ b/compiler/dex/quick/dex_file_method_inliner.cc @@ -293,9 +293,9 @@ const DexFileMethodInliner::IntrinsicDef DexFileMethodInliner::kIntrinsicMethods { { kClassCache ## c, kNameCache ## n, kProtoCache ## p }, { o, kInlineIntrinsic, { d } } } INTRINSIC(JavaLangDouble, DoubleToRawLongBits, D_J, kIntrinsicDoubleCvt, 0), - INTRINSIC(JavaLangDouble, LongBitsToDouble, J_D, kIntrinsicDoubleCvt, 0), + INTRINSIC(JavaLangDouble, LongBitsToDouble, J_D, kIntrinsicDoubleCvt, kIntrinsicFlagToFloatingPoint), INTRINSIC(JavaLangFloat, FloatToRawIntBits, F_I, kIntrinsicFloatCvt, 0), - INTRINSIC(JavaLangFloat, IntBitsToFloat, I_F, kIntrinsicFloatCvt, 0), + INTRINSIC(JavaLangFloat, IntBitsToFloat, I_F, kIntrinsicFloatCvt, kIntrinsicFlagToFloatingPoint), INTRINSIC(JavaLangInteger, ReverseBytes, I_I, kIntrinsicReverseBytes, k32), INTRINSIC(JavaLangLong, ReverseBytes, J_J, kIntrinsicReverseBytes, k64), diff --git a/compiler/driver/compiler_driver.cc b/compiler/driver/compiler_driver.cc index 9985d66469..56bed39bf1 100644 --- a/compiler/driver/compiler_driver.cc +++ b/compiler/driver/compiler_driver.cc @@ -339,7 +339,8 @@ CompilerDriver::CompilerDriver(const CompilerOptions* compiler_options, const InstructionSetFeatures* instruction_set_features, bool image, std::set<std::string>* image_classes, std::set<std::string>* compiled_classes, size_t thread_count, - bool dump_stats, bool dump_passes, CumulativeLogger* timer, + bool dump_stats, bool dump_passes, + const std::string& dump_cfg_file_name, CumulativeLogger* timer, int swap_fd, const std::string& profile_file) : swap_space_(swap_fd == -1 ? nullptr : new SwapSpace(swap_fd, 10 * MB)), swap_space_allocator_(new SwapAllocator<void>(swap_space_.get())), @@ -361,9 +362,10 @@ CompilerDriver::CompilerDriver(const CompilerOptions* compiler_options, stats_(new AOTCompilationStats), dump_stats_(dump_stats), dump_passes_(dump_passes), + dump_cfg_file_name_(dump_cfg_file_name), timings_logger_(timer), compiler_context_(nullptr), - support_boot_image_fixup_(instruction_set != kMips), + support_boot_image_fixup_(instruction_set != kMips && instruction_set != kMips64), dedupe_code_("dedupe code", *swap_space_allocator_), dedupe_src_mapping_table_("dedupe source mapping table", *swap_space_allocator_), dedupe_mapping_table_("dedupe mapping table", *swap_space_allocator_), @@ -2094,6 +2096,7 @@ static bool InstructionSetHasGenericJniStub(InstructionSet isa) { case kArm64: case kThumb2: case kMips: + case kMips64: case kX86: case kX86_64: return true; default: return false; diff --git a/compiler/driver/compiler_driver.h b/compiler/driver/compiler_driver.h index 7ddc32cdd8..11b4329e32 100644 --- a/compiler/driver/compiler_driver.h +++ b/compiler/driver/compiler_driver.h @@ -97,6 +97,7 @@ class CompilerDriver { bool image, std::set<std::string>* image_classes, std::set<std::string>* compiled_classes, size_t thread_count, bool dump_stats, bool dump_passes, + const std::string& dump_cfg_file_name, CumulativeLogger* timer, int swap_fd, const std::string& profile_file); @@ -371,6 +372,10 @@ class CompilerDriver { return dump_passes_; } + const std::string& GetDumpCfgFileName() const { + return dump_cfg_file_name_; + } + CumulativeLogger* GetTimingsLogger() const { return timings_logger_; } @@ -542,6 +547,7 @@ class CompilerDriver { bool dump_stats_; const bool dump_passes_; + const std::string& dump_cfg_file_name_; CumulativeLogger* const timings_logger_; diff --git a/compiler/elf_builder.h b/compiler/elf_builder.h index 273b62deee..94268de077 100644 --- a/compiler/elf_builder.h +++ b/compiler/elf_builder.h @@ -1108,6 +1108,14 @@ class ElfBuilder FINAL { EF_MIPS_ARCH_32R2); break; } + case kMips64: { + elf_header_.e_machine = EM_MIPS; + elf_header_.e_flags = (EF_MIPS_NOREORDER | + EF_MIPS_PIC | + EF_MIPS_CPIC | + EF_MIPS_ARCH_64R6); + break; + } default: { fatal_error_ = true; LOG(FATAL) << "Unknown instruction set: " << isa; diff --git a/compiler/jni/jni_compiler_test.cc b/compiler/jni/jni_compiler_test.cc index 281e3fe109..f513ea8124 100644 --- a/compiler/jni/jni_compiler_test.cc +++ b/compiler/jni/jni_compiler_test.cc @@ -973,6 +973,9 @@ void Java_MyClassNatives_staticMethodThatShouldTakeClass(JNIEnv*, jclass, jclass } void JniCompilerTest::UpcallArgumentTypeChecking_InstanceImpl() { + // This will lead to error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + SetUpForTest(false, "instanceMethodThatShouldTakeClass", "(ILjava/lang/Class;)V", reinterpret_cast<void*>(&Java_MyClassNatives_instanceMethodThatShouldTakeClass)); @@ -985,6 +988,9 @@ void JniCompilerTest::UpcallArgumentTypeChecking_InstanceImpl() { JNI_TEST(UpcallArgumentTypeChecking_Instance) void JniCompilerTest::UpcallArgumentTypeChecking_StaticImpl() { + // This will lead to error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + SetUpForTest(true, "staticMethodThatShouldTakeClass", "(ILjava/lang/Class;)V", reinterpret_cast<void*>(&Java_MyClassNatives_staticMethodThatShouldTakeClass)); @@ -1475,6 +1481,9 @@ void JniCompilerTest::MaxParamNumberImpl() { JNI_TEST(MaxParamNumber) void JniCompilerTest::WithoutImplementationImpl() { + // This will lead to error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + SetUpForTest(false, "withoutImplementation", "()V", nullptr); env_->CallVoidMethod(jobj_, jmethod_); diff --git a/compiler/oat_test.cc b/compiler/oat_test.cc index b3ab370c99..d3d20555d8 100644 --- a/compiler/oat_test.cc +++ b/compiler/oat_test.cc @@ -92,7 +92,7 @@ TEST_F(OatTest, WriteRead) { method_inliner_map_.get(), compiler_kind, insn_set, insn_features.get(), false, nullptr, nullptr, 2, true, - true, timer_.get(), -1, "")); + true, "", timer_.get(), -1, "")); jobject class_loader = nullptr; if (kCompile) { TimingLogger timings2("OatTest::WriteRead", false, false); diff --git a/compiler/optimizing/builder.cc b/compiler/optimizing/builder.cc index f6ca6c740e..9c2facb75e 100644 --- a/compiler/optimizing/builder.cc +++ b/compiler/optimizing/builder.cc @@ -604,7 +604,7 @@ bool HGraphBuilder::BuildInvoke(const Instruction& instruction, HInvoke* invoke = nullptr; if (optimized_invoke_type == kVirtual) { invoke = new (arena_) HInvokeVirtual( - arena_, number_of_arguments, return_type, dex_pc, table_index); + arena_, number_of_arguments, return_type, dex_pc, method_idx, table_index); } else if (optimized_invoke_type == kInterface) { invoke = new (arena_) HInvokeInterface( arena_, number_of_arguments, return_type, dex_pc, method_idx, table_index); diff --git a/compiler/optimizing/code_generator.cc b/compiler/optimizing/code_generator.cc index 0c1ff9bff5..9e8907078b 100644 --- a/compiler/optimizing/code_generator.cc +++ b/compiler/optimizing/code_generator.cc @@ -54,6 +54,7 @@ void CodeGenerator::CompileBaseline(CodeAllocator* allocator, bool is_leaf) { + GetGraph()->GetTemporariesVRegSlots() + 1 /* filler */, 0, /* the baseline compiler does not have live registers at slow path */ + 0, /* the baseline compiler does not have live registers at slow path */ GetGraph()->GetMaximumNumberOfOutVRegs() + 1 /* current method */); GenerateFrameEntry(); @@ -136,14 +137,16 @@ size_t CodeGenerator::FindTwoFreeConsecutiveAlignedEntries(bool* array, size_t l } void CodeGenerator::ComputeFrameSize(size_t number_of_spill_slots, - size_t maximum_number_of_live_registers, + size_t maximum_number_of_live_core_registers, + size_t maximum_number_of_live_fp_registers, size_t number_of_out_slots) { first_register_slot_in_slow_path_ = (number_of_out_slots + number_of_spill_slots) * kVRegSize; SetFrameSize(RoundUp( number_of_spill_slots * kVRegSize + number_of_out_slots * kVRegSize - + maximum_number_of_live_registers * GetWordSize() + + maximum_number_of_live_core_registers * GetWordSize() + + maximum_number_of_live_fp_registers * GetFloatingPointSpillSlotSize() + FrameEntrySpillSize(), kStackAlignment)); } diff --git a/compiler/optimizing/code_generator.h b/compiler/optimizing/code_generator.h index 8d28f3da25..88e50b6c88 100644 --- a/compiler/optimizing/code_generator.h +++ b/compiler/optimizing/code_generator.h @@ -109,9 +109,11 @@ class CodeGenerator { virtual HGraphVisitor* GetInstructionVisitor() = 0; virtual Assembler* GetAssembler() = 0; virtual size_t GetWordSize() const = 0; + virtual size_t GetFloatingPointSpillSlotSize() const = 0; virtual uintptr_t GetAddressOf(HBasicBlock* block) const = 0; void ComputeFrameSize(size_t number_of_spill_slots, - size_t maximum_number_of_live_registers, + size_t maximum_number_of_live_core_registers, + size_t maximum_number_of_live_fp_registers, size_t number_of_out_slots); virtual size_t FrameEntrySpillSize() const = 0; int32_t GetStackSlot(HLocal* local) const; diff --git a/compiler/optimizing/code_generator_arm.cc b/compiler/optimizing/code_generator_arm.cc index 1862061bcf..c4ba0fd3e5 100644 --- a/compiler/optimizing/code_generator_arm.cc +++ b/compiler/optimizing/code_generator_arm.cc @@ -1190,7 +1190,7 @@ void InstructionCodeGeneratorARM::VisitInvokeStaticOrDirect(HInvokeStaticOrDirec kLoadWord, temp, temp, mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value()); // temp = temp[index_in_cache] __ LoadFromOffset( - kLoadWord, temp, temp, CodeGenerator::GetCacheOffset(invoke->GetIndexInDexCache())); + kLoadWord, temp, temp, CodeGenerator::GetCacheOffset(invoke->GetDexMethodIndex())); // LR = temp[offset_of_quick_compiled_code] __ LoadFromOffset(kLoadWord, LR, temp, mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( diff --git a/compiler/optimizing/code_generator_arm.h b/compiler/optimizing/code_generator_arm.h index 8b29b159ab..267d9a2cef 100644 --- a/compiler/optimizing/code_generator_arm.h +++ b/compiler/optimizing/code_generator_arm.h @@ -169,6 +169,11 @@ class CodeGeneratorARM : public CodeGenerator { return kArmWordSize; } + size_t GetFloatingPointSpillSlotSize() const OVERRIDE { + // Allocated in S registers, which are word sized. + return kArmWordSize; + } + size_t FrameEntrySpillSize() const OVERRIDE; HGraphVisitor* GetLocationBuilder() OVERRIDE { diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc index 7b19f44e78..6d2c3de5d5 100644 --- a/compiler/optimizing/code_generator_arm64.cc +++ b/compiler/optimizing/code_generator_arm64.cc @@ -1975,7 +1975,7 @@ void InstructionCodeGeneratorARM64::VisitInvokeStaticOrDirect(HInvokeStaticOrDir // Make sure that ArtMethod* is passed in W0 as per the calling convention DCHECK(temp.Is(w0)); size_t index_in_cache = mirror::Array::DataOffset(kHeapRefSize).SizeValue() + - invoke->GetIndexInDexCache() * kHeapRefSize; + invoke->GetDexMethodIndex() * kHeapRefSize; // TODO: Implement all kinds of calls: // 1) boot -> boot diff --git a/compiler/optimizing/code_generator_arm64.h b/compiler/optimizing/code_generator_arm64.h index e4da07be43..590bc1d778 100644 --- a/compiler/optimizing/code_generator_arm64.h +++ b/compiler/optimizing/code_generator_arm64.h @@ -191,6 +191,11 @@ class CodeGeneratorARM64 : public CodeGenerator { return kArm64WordSize; } + size_t GetFloatingPointSpillSlotSize() const OVERRIDE { + // Allocated in D registers, which are word sized. + return kArm64WordSize; + } + uintptr_t GetAddressOf(HBasicBlock* block) const OVERRIDE { vixl::Label* block_entry_label = GetLabelOf(block); DCHECK(block_entry_label->IsBound()); diff --git a/compiler/optimizing/code_generator_x86.cc b/compiler/optimizing/code_generator_x86.cc index 04e36cc58a..1a0df44ea6 100644 --- a/compiler/optimizing/code_generator_x86.cc +++ b/compiler/optimizing/code_generator_x86.cc @@ -1135,7 +1135,7 @@ void InstructionCodeGeneratorX86::VisitInvokeStaticOrDirect(HInvokeStaticOrDirec // temp = temp->dex_cache_resolved_methods_; __ movl(temp, Address(temp, mirror::ArtMethod::DexCacheResolvedMethodsOffset().Int32Value())); // temp = temp[index_in_cache] - __ movl(temp, Address(temp, CodeGenerator::GetCacheOffset(invoke->GetIndexInDexCache()))); + __ movl(temp, Address(temp, CodeGenerator::GetCacheOffset(invoke->GetDexMethodIndex()))); // (temp + offset_of_quick_compiled_code)() __ call(Address( temp, mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset(kX86WordSize).Int32Value())); diff --git a/compiler/optimizing/code_generator_x86.h b/compiler/optimizing/code_generator_x86.h index acde122917..2d8adb2cf1 100644 --- a/compiler/optimizing/code_generator_x86.h +++ b/compiler/optimizing/code_generator_x86.h @@ -166,6 +166,11 @@ class CodeGeneratorX86 : public CodeGenerator { return kX86WordSize; } + size_t GetFloatingPointSpillSlotSize() const OVERRIDE { + // 8 bytes == 2 words for each spill. + return 2 * kX86WordSize; + } + size_t FrameEntrySpillSize() const OVERRIDE; HGraphVisitor* GetLocationBuilder() OVERRIDE { diff --git a/compiler/optimizing/code_generator_x86_64.cc b/compiler/optimizing/code_generator_x86_64.cc index 5fc24f71e6..3d7f122d36 100644 --- a/compiler/optimizing/code_generator_x86_64.cc +++ b/compiler/optimizing/code_generator_x86_64.cc @@ -18,6 +18,8 @@ #include "entrypoints/quick/quick_entrypoints.h" #include "gc/accounting/card_table.h" +#include "intrinsics.h" +#include "intrinsics_x86_64.h" #include "mirror/array-inl.h" #include "mirror/art_method.h" #include "mirror/class.h" @@ -61,20 +63,6 @@ class InvokeRuntimeCallingConvention : public CallingConvention<Register, FloatR #define __ reinterpret_cast<X86_64Assembler*>(codegen->GetAssembler())-> -class SlowPathCodeX86_64 : public SlowPathCode { - public: - SlowPathCodeX86_64() : entry_label_(), exit_label_() {} - - Label* GetEntryLabel() { return &entry_label_; } - Label* GetExitLabel() { return &exit_label_; } - - private: - Label entry_label_; - Label exit_label_; - - DISALLOW_COPY_AND_ASSIGN(SlowPathCodeX86_64); -}; - class NullCheckSlowPathX86_64 : public SlowPathCodeX86_64 { public: explicit NullCheckSlowPathX86_64(HNullCheck* instruction) : instruction_(instruction) {} @@ -375,6 +363,31 @@ inline Condition X86_64Condition(IfCondition cond) { return kEqual; } +void CodeGeneratorX86_64::GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, + CpuRegister temp) { + // All registers are assumed to be correctly set up. + + // TODO: Implement all kinds of calls: + // 1) boot -> boot + // 2) app -> boot + // 3) app -> app + // + // Currently we implement the app -> app logic, which looks up in the resolve cache. + + // temp = method; + LoadCurrentMethod(temp); + // temp = temp->dex_cache_resolved_methods_; + __ movl(temp, Address(temp, mirror::ArtMethod::DexCacheResolvedMethodsOffset().SizeValue())); + // temp = temp[index_in_cache] + __ movl(temp, Address(temp, CodeGenerator::GetCacheOffset(invoke->GetDexMethodIndex()))); + // (temp + offset_of_quick_compiled_code)() + __ call(Address(temp, mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( + kX86_64WordSize).SizeValue())); + + DCHECK(!IsLeafMethod()); + RecordPcInfo(invoke, invoke->GetDexPc()); +} + void CodeGeneratorX86_64::DumpCoreRegister(std::ostream& stream, int reg) const { stream << X86_64ManagedRegister::FromCpuRegister(Register(reg)); } @@ -1123,30 +1136,31 @@ Location InvokeDexCallingConventionVisitor::GetNextLocation(Primitive::Type type } void LocationsBuilderX86_64::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) { + IntrinsicLocationsBuilderX86_64 intrinsic(GetGraph()->GetArena()); + if (intrinsic.TryDispatch(invoke)) { + return; + } + HandleInvoke(invoke); } -void InstructionCodeGeneratorX86_64::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) { - CpuRegister temp = invoke->GetLocations()->GetTemp(0).AsRegister<CpuRegister>(); - // TODO: Implement all kinds of calls: - // 1) boot -> boot - // 2) app -> boot - // 3) app -> app - // - // Currently we implement the app -> app logic, which looks up in the resolve cache. +static bool TryGenerateIntrinsicCode(HInvoke* invoke, CodeGeneratorX86_64* codegen) { + if (invoke->GetLocations()->Intrinsified()) { + IntrinsicCodeGeneratorX86_64 intrinsic(codegen); + intrinsic.Dispatch(invoke); + return true; + } + return false; +} - // temp = method; - codegen_->LoadCurrentMethod(temp); - // temp = temp->dex_cache_resolved_methods_; - __ movl(temp, Address(temp, mirror::ArtMethod::DexCacheResolvedMethodsOffset().SizeValue())); - // temp = temp[index_in_cache] - __ movl(temp, Address(temp, CodeGenerator::GetCacheOffset(invoke->GetIndexInDexCache()))); - // (temp + offset_of_quick_compiled_code)() - __ call(Address(temp, mirror::ArtMethod::EntryPointFromQuickCompiledCodeOffset( - kX86_64WordSize).SizeValue())); +void InstructionCodeGeneratorX86_64::VisitInvokeStaticOrDirect(HInvokeStaticOrDirect* invoke) { + if (TryGenerateIntrinsicCode(invoke, codegen_)) { + return; + } - DCHECK(!codegen_->IsLeafMethod()); - codegen_->RecordPcInfo(invoke, invoke->GetDexPc()); + codegen_->GenerateStaticOrDirectCall( + invoke, + invoke->GetLocations()->GetTemp(0).AsRegister<CpuRegister>()); } void LocationsBuilderX86_64::HandleInvoke(HInvoke* invoke) { @@ -1182,10 +1196,19 @@ void LocationsBuilderX86_64::HandleInvoke(HInvoke* invoke) { } void LocationsBuilderX86_64::VisitInvokeVirtual(HInvokeVirtual* invoke) { + IntrinsicLocationsBuilderX86_64 intrinsic(GetGraph()->GetArena()); + if (intrinsic.TryDispatch(invoke)) { + return; + } + HandleInvoke(invoke); } void InstructionCodeGeneratorX86_64::VisitInvokeVirtual(HInvokeVirtual* invoke) { + if (TryGenerateIntrinsicCode(invoke, codegen_)) { + return; + } + CpuRegister temp = invoke->GetLocations()->GetTemp(0).AsRegister<CpuRegister>(); size_t method_offset = mirror::Class::EmbeddedVTableOffset().SizeValue() + invoke->GetVTableIndex() * sizeof(mirror::Class::VTableEntry); diff --git a/compiler/optimizing/code_generator_x86_64.h b/compiler/optimizing/code_generator_x86_64.h index 87f6b0f779..c501568a89 100644 --- a/compiler/optimizing/code_generator_x86_64.h +++ b/compiler/optimizing/code_generator_x86_64.h @@ -36,6 +36,8 @@ static constexpr FloatRegister kParameterFloatRegisters[] = static constexpr size_t kParameterCoreRegistersLength = arraysize(kParameterCoreRegisters); static constexpr size_t kParameterFloatRegistersLength = arraysize(kParameterFloatRegisters); +static constexpr bool kCoalescedImplicitNullCheck = false; + class InvokeDexCallingConvention : public CallingConvention<Register, FloatRegister> { public: InvokeDexCallingConvention() : CallingConvention( @@ -67,7 +69,20 @@ class InvokeDexCallingConventionVisitor { }; class CodeGeneratorX86_64; -class SlowPathCodeX86_64; + +class SlowPathCodeX86_64 : public SlowPathCode { + public: + SlowPathCodeX86_64() : entry_label_(), exit_label_() {} + + Label* GetEntryLabel() { return &entry_label_; } + Label* GetExitLabel() { return &exit_label_; } + + private: + Label entry_label_; + Label exit_label_; + + DISALLOW_COPY_AND_ASSIGN(SlowPathCodeX86_64); +}; class ParallelMoveResolverX86_64 : public ParallelMoveResolver { public: @@ -169,6 +184,10 @@ class CodeGeneratorX86_64 : public CodeGenerator { return kX86_64WordSize; } + size_t GetFloatingPointSpillSlotSize() const OVERRIDE { + return kX86_64WordSize; + } + size_t FrameEntrySpillSize() const OVERRIDE; HGraphVisitor* GetLocationBuilder() OVERRIDE { @@ -222,6 +241,8 @@ class CodeGeneratorX86_64 : public CodeGenerator { return false; } + void GenerateStaticOrDirectCall(HInvokeStaticOrDirect* invoke, CpuRegister temp); + private: // Labels for each block that will be compiled. GrowableArray<Label> block_labels_; diff --git a/compiler/optimizing/inliner.cc b/compiler/optimizing/inliner.cc index 493d93f052..532167c179 100644 --- a/compiler/optimizing/inliner.cc +++ b/compiler/optimizing/inliner.cc @@ -44,10 +44,10 @@ void HInliner::Run() { instr_it.Advance()) { HInvokeStaticOrDirect* current = instr_it.Current()->AsInvokeStaticOrDirect(); if (current != nullptr) { - if (!TryInline(current, current->GetIndexInDexCache(), current->GetInvokeType())) { + if (!TryInline(current, current->GetDexMethodIndex(), current->GetInvokeType())) { if (kIsDebugBuild) { std::string callee_name = - PrettyMethod(current->GetIndexInDexCache(), *outer_compilation_unit_.GetDexFile()); + PrettyMethod(current->GetDexMethodIndex(), *outer_compilation_unit_.GetDexFile()); bool should_inline = callee_name.find("$inline$") != std::string::npos; CHECK(!should_inline) << "Could not inline " << callee_name; } diff --git a/compiler/optimizing/intrinsics.cc b/compiler/optimizing/intrinsics.cc new file mode 100644 index 0000000000..fe0e7f2eb2 --- /dev/null +++ b/compiler/optimizing/intrinsics.cc @@ -0,0 +1,366 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "intrinsics.h" + +#include "dex/quick/dex_file_method_inliner.h" +#include "dex/quick/dex_file_to_method_inliner_map.h" +#include "driver/compiler_driver.h" +#include "invoke_type.h" +#include "nodes.h" +#include "quick/inline_method_analyser.h" + +namespace art { + +// Function that returns whether an intrinsic is static/direct or virtual. +static inline InvokeType GetIntrinsicInvokeType(Intrinsics i) { + switch (i) { + case Intrinsics::kNone: + return kInterface; // Non-sensical for intrinsic. +#define OPTIMIZING_INTRINSICS(Name, IsStatic) \ + case Intrinsics::k ## Name: \ + return IsStatic; +#include "intrinsics_list.h" +INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS + } + return kInterface; +} + + + +static Primitive::Type GetType(uint64_t data, bool is_op_size) { + if (is_op_size) { + switch (static_cast<OpSize>(data)) { + case kSignedByte: + return Primitive::Type::kPrimByte; + case kSignedHalf: + return Primitive::Type::kPrimShort; + case k32: + return Primitive::Type::kPrimInt; + case k64: + return Primitive::Type::kPrimLong; + default: + LOG(FATAL) << "Unknown/unsupported op size " << data; + UNREACHABLE(); + } + } else { + if ((data & kIntrinsicFlagIsLong) != 0) { + return Primitive::Type::kPrimLong; + } + if ((data & kIntrinsicFlagIsObject) != 0) { + return Primitive::Type::kPrimNot; + } + return Primitive::Type::kPrimInt; + } +} + +static Intrinsics GetIntrinsic(InlineMethod method) { + switch (method.opcode) { + // Floating-point conversions. + case kIntrinsicDoubleCvt: + return ((method.d.data & kIntrinsicFlagToFloatingPoint) == 0) ? + Intrinsics::kDoubleDoubleToRawLongBits : Intrinsics::kDoubleLongBitsToDouble; + case kIntrinsicFloatCvt: + return ((method.d.data & kIntrinsicFlagToFloatingPoint) == 0) ? + Intrinsics::kFloatFloatToRawIntBits : Intrinsics::kFloatIntBitsToFloat; + + // Bit manipulations. + case kIntrinsicReverseBits: + switch (GetType(method.d.data, true)) { + case Primitive::Type::kPrimInt: + return Intrinsics::kIntegerReverse; + case Primitive::Type::kPrimLong: + return Intrinsics::kLongReverse; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + case kIntrinsicReverseBytes: + switch (GetType(method.d.data, true)) { + case Primitive::Type::kPrimShort: + return Intrinsics::kShortReverseBytes; + case Primitive::Type::kPrimInt: + return Intrinsics::kIntegerReverseBytes; + case Primitive::Type::kPrimLong: + return Intrinsics::kLongReverseBytes; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + + // Abs. + case kIntrinsicAbsDouble: + return Intrinsics::kMathAbsDouble; + case kIntrinsicAbsFloat: + return Intrinsics::kMathAbsFloat; + case kIntrinsicAbsInt: + return Intrinsics::kMathAbsInt; + case kIntrinsicAbsLong: + return Intrinsics::kMathAbsLong; + + // Min/max. + case kIntrinsicMinMaxDouble: + return ((method.d.data & kIntrinsicFlagMin) == 0) ? + Intrinsics::kMathMaxDoubleDouble : Intrinsics::kMathMinDoubleDouble; + case kIntrinsicMinMaxFloat: + return ((method.d.data & kIntrinsicFlagMin) == 0) ? + Intrinsics::kMathMaxFloatFloat : Intrinsics::kMathMinFloatFloat; + case kIntrinsicMinMaxInt: + return ((method.d.data & kIntrinsicFlagMin) == 0) ? + Intrinsics::kMathMaxIntInt : Intrinsics::kMathMinIntInt; + case kIntrinsicMinMaxLong: + return ((method.d.data & kIntrinsicFlagMin) == 0) ? + Intrinsics::kMathMaxLongLong : Intrinsics::kMathMinLongLong; + + // Misc math. + case kIntrinsicSqrt: + return Intrinsics::kMathSqrt; + case kIntrinsicCeil: + return Intrinsics::kMathCeil; + case kIntrinsicFloor: + return Intrinsics::kMathFloor; + case kIntrinsicRint: + return Intrinsics::kMathRint; + case kIntrinsicRoundDouble: + return Intrinsics::kMathRoundDouble; + case kIntrinsicRoundFloat: + return Intrinsics::kMathRoundFloat; + + // System.arraycopy. + case kIntrinsicSystemArrayCopyCharArray: + return Intrinsics::kSystemArrayCopyChar; + + // Thread.currentThread. + case kIntrinsicCurrentThread: + return Intrinsics::kThreadCurrentThread; + + // Memory.peek. + case kIntrinsicPeek: + switch (GetType(method.d.data, true)) { + case Primitive::Type::kPrimByte: + return Intrinsics::kMemoryPeekByte; + case Primitive::Type::kPrimShort: + return Intrinsics::kMemoryPeekShortNative; + case Primitive::Type::kPrimInt: + return Intrinsics::kMemoryPeekIntNative; + case Primitive::Type::kPrimLong: + return Intrinsics::kMemoryPeekLongNative; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + + // Memory.poke. + case kIntrinsicPoke: + switch (GetType(method.d.data, true)) { + case Primitive::Type::kPrimByte: + return Intrinsics::kMemoryPokeByte; + case Primitive::Type::kPrimShort: + return Intrinsics::kMemoryPokeShortNative; + case Primitive::Type::kPrimInt: + return Intrinsics::kMemoryPokeIntNative; + case Primitive::Type::kPrimLong: + return Intrinsics::kMemoryPokeLongNative; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + + // String. + case kIntrinsicCharAt: + return Intrinsics::kStringCharAt; + case kIntrinsicCompareTo: + return Intrinsics::kStringCompareTo; + case kIntrinsicIsEmptyOrLength: + return ((method.d.data & kIntrinsicFlagIsEmpty) == 0) ? + Intrinsics::kStringLength : Intrinsics::kStringIsEmpty; + case kIntrinsicIndexOf: + return ((method.d.data & kIntrinsicFlagBase0) == 0) ? + Intrinsics::kStringIndexOfAfter : Intrinsics::kStringIndexOf; + + case kIntrinsicCas: + switch (GetType(method.d.data, false)) { + case Primitive::Type::kPrimNot: + return Intrinsics::kUnsafeCASObject; + case Primitive::Type::kPrimInt: + return Intrinsics::kUnsafeCASInt; + case Primitive::Type::kPrimLong: + return Intrinsics::kUnsafeCASLong; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + case kIntrinsicUnsafeGet: { + const bool is_volatile = (method.d.data & kIntrinsicFlagIsVolatile); + switch (GetType(method.d.data, false)) { + case Primitive::Type::kPrimInt: + return is_volatile ? Intrinsics::kUnsafeGetVolatile : Intrinsics::kUnsafeGet; + case Primitive::Type::kPrimLong: + return is_volatile ? Intrinsics::kUnsafeGetLongVolatile : Intrinsics::kUnsafeGetLong; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + } + case kIntrinsicUnsafePut: { + enum Sync { kNoSync, kVolatile, kOrdered }; + const Sync sync = + ((method.d.data & kIntrinsicFlagIsVolatile) != 0) ? kVolatile : + ((method.d.data & kIntrinsicFlagIsOrdered) != 0) ? kOrdered : + kNoSync; + switch (GetType(method.d.data, false)) { + case Primitive::Type::kPrimInt: + switch (sync) { + case kNoSync: + return Intrinsics::kUnsafePut; + case kVolatile: + return Intrinsics::kUnsafePutVolatile; + case kOrdered: + return Intrinsics::kUnsafePutOrdered; + } + break; + case Primitive::Type::kPrimLong: + switch (sync) { + case kNoSync: + return Intrinsics::kUnsafePutLong; + case kVolatile: + return Intrinsics::kUnsafePutLongVolatile; + case kOrdered: + return Intrinsics::kUnsafePutLongOrdered; + } + break; + case Primitive::Type::kPrimNot: + switch (sync) { + case kNoSync: + return Intrinsics::kUnsafePutObject; + case kVolatile: + return Intrinsics::kUnsafePutObjectVolatile; + case kOrdered: + return Intrinsics::kUnsafePutObjectOrdered; + } + break; + default: + LOG(FATAL) << "Unknown/unsupported op size " << method.d.data; + UNREACHABLE(); + } + break; + } + + // Virtual cases. + + case kIntrinsicReferenceGetReferent: + return Intrinsics::kReferenceGetReferent; + + // Quick inliner cases. Remove after refactoring. They are here so that we can use the + // compiler to warn on missing cases. + + case kInlineOpNop: + case kInlineOpReturnArg: + case kInlineOpNonWideConst: + case kInlineOpIGet: + case kInlineOpIPut: + return Intrinsics::kNone; + + // No default case to make the compiler warn on missing cases. + } + return Intrinsics::kNone; +} + +static bool CheckInvokeType(Intrinsics intrinsic, HInvoke* invoke) { + // The DexFileMethodInliner should have checked whether the methods are agreeing with + // what we expect, i.e., static methods are called as such. Add another check here for + // our expectations: + // Whenever the intrinsic is marked as static-or-direct, report an error if we find an + // InvokeVirtual. The other direction is not possible: we have intrinsics for virtual + // functions that will perform a check inline. If the precise type is known, however, + // the instruction will be sharpened to an InvokeStaticOrDirect. + InvokeType intrinsic_type = GetIntrinsicInvokeType(intrinsic); + InvokeType invoke_type = invoke->IsInvokeStaticOrDirect() ? + invoke->AsInvokeStaticOrDirect()->GetInvokeType() : + invoke->IsInvokeVirtual() ? kVirtual : kSuper; + switch (intrinsic_type) { + case kStatic: + return (invoke_type == kStatic); + case kDirect: + return (invoke_type == kDirect); + case kVirtual: + // Call might be devirtualized. + return (invoke_type == kVirtual || invoke_type == kDirect); + + default: + return false; + } +} + +// TODO: Refactor DexFileMethodInliner and have something nicer than InlineMethod. +void IntrinsicsRecognizer::Run() { + DexFileMethodInliner* inliner = driver_->GetMethodInlinerMap()->GetMethodInliner(dex_file_); + DCHECK(inliner != nullptr); + + for (HReversePostOrderIterator it(*graph_); !it.Done(); it.Advance()) { + HBasicBlock* block = it.Current(); + for (HInstructionIterator inst_it(block->GetInstructions()); !inst_it.Done(); + inst_it.Advance()) { + HInstruction* inst = inst_it.Current(); + if (inst->IsInvoke()) { + HInvoke* invoke = inst->AsInvoke(); + InlineMethod method; + if (inliner->IsIntrinsic(invoke->GetDexMethodIndex(), &method)) { + Intrinsics intrinsic = GetIntrinsic(method); + + if (intrinsic != Intrinsics::kNone) { + if (!CheckInvokeType(intrinsic, invoke)) { + LOG(WARNING) << "Found an intrinsic with unexpected invoke type: " + << intrinsic << " for " + << PrettyMethod(invoke->GetDexMethodIndex(), *dex_file_); + } else { + invoke->SetIntrinsic(intrinsic); + } + } + } + } + } + } +} + +std::ostream& operator<<(std::ostream& os, const Intrinsics& intrinsic) { + switch (intrinsic) { + case Intrinsics::kNone: + os << "No intrinsic."; + break; +#define OPTIMIZING_INTRINSICS(Name, IsStatic) \ + case Intrinsics::k ## Name: \ + os << # Name; \ + break; +#include "intrinsics_list.h" +INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef STATIC_INTRINSICS_LIST +#undef VIRTUAL_INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS + } + return os; +} + +} // namespace art + diff --git a/compiler/optimizing/intrinsics.h b/compiler/optimizing/intrinsics.h new file mode 100644 index 0000000000..29cc8efcc3 --- /dev/null +++ b/compiler/optimizing/intrinsics.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_COMPILER_OPTIMIZING_INTRINSICS_H_ +#define ART_COMPILER_OPTIMIZING_INTRINSICS_H_ + +#include "nodes.h" +#include "optimization.h" + +namespace art { + +class CompilerDriver; +class DexFile; + +// Recognize intrinsics from HInvoke nodes. +class IntrinsicsRecognizer : public HOptimization { + public: + IntrinsicsRecognizer(HGraph* graph, const DexFile* dex_file, CompilerDriver* driver) + : HOptimization(graph, true, "intrinsics_recognition"), + dex_file_(dex_file), driver_(driver) {} + + void Run() OVERRIDE; + + private: + const DexFile* dex_file_; + CompilerDriver* driver_; + + DISALLOW_COPY_AND_ASSIGN(IntrinsicsRecognizer); +}; + +class IntrinsicVisitor : public ValueObject { + public: + virtual ~IntrinsicVisitor() {} + + // Dispatch logic. + + void Dispatch(HInvoke* invoke) { + switch (invoke->GetIntrinsic()) { + case Intrinsics::kNone: + return; +#define OPTIMIZING_INTRINSICS(Name, IsStatic) \ + case Intrinsics::k ## Name: \ + Visit ## Name(invoke); \ + return; +#include "intrinsics_list.h" +INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS + + // Do not put a default case. That way the compiler will complain if we missed a case. + } + } + + // Define visitor methods. + +#define OPTIMIZING_INTRINSICS(Name, IsStatic) \ + virtual void Visit ## Name(HInvoke* invoke ATTRIBUTE_UNUSED) { \ + } +#include "intrinsics_list.h" +INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS + + protected: + IntrinsicVisitor() {} + + private: + DISALLOW_COPY_AND_ASSIGN(IntrinsicVisitor); +}; + +} // namespace art + +#endif // ART_COMPILER_OPTIMIZING_INTRINSICS_H_ diff --git a/compiler/optimizing/intrinsics_list.h b/compiler/optimizing/intrinsics_list.h new file mode 100644 index 0000000000..29ca20cca0 --- /dev/null +++ b/compiler/optimizing/intrinsics_list.h @@ -0,0 +1,87 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_COMPILER_OPTIMIZING_INTRINSICS_LIST_H_ +#define ART_COMPILER_OPTIMIZING_INTRINSICS_LIST_H_ + +// All intrinsics supported by the optimizing compiler. Format is name, then whether it is expected +// to be a HInvokeStaticOrDirect node (compared to HInvokeVirtual). + +#define INTRINSICS_LIST(V) \ + V(DoubleDoubleToRawLongBits, kStatic) \ + V(DoubleLongBitsToDouble, kStatic) \ + V(FloatFloatToRawIntBits, kStatic) \ + V(FloatIntBitsToFloat, kStatic) \ + V(IntegerReverse, kStatic) \ + V(IntegerReverseBytes, kStatic) \ + V(LongReverse, kStatic) \ + V(LongReverseBytes, kStatic) \ + V(ShortReverseBytes, kStatic) \ + V(MathAbsDouble, kStatic) \ + V(MathAbsFloat, kStatic) \ + V(MathAbsLong, kStatic) \ + V(MathAbsInt, kStatic) \ + V(MathMinDoubleDouble, kStatic) \ + V(MathMinFloatFloat, kStatic) \ + V(MathMinLongLong, kStatic) \ + V(MathMinIntInt, kStatic) \ + V(MathMaxDoubleDouble, kStatic) \ + V(MathMaxFloatFloat, kStatic) \ + V(MathMaxLongLong, kStatic) \ + V(MathMaxIntInt, kStatic) \ + V(MathSqrt, kStatic) \ + V(MathCeil, kStatic) \ + V(MathFloor, kStatic) \ + V(MathRint, kStatic) \ + V(MathRoundDouble, kStatic) \ + V(MathRoundFloat, kStatic) \ + V(SystemArrayCopyChar, kStatic) \ + V(ThreadCurrentThread, kStatic) \ + V(MemoryPeekByte, kStatic) \ + V(MemoryPeekIntNative, kStatic) \ + V(MemoryPeekLongNative, kStatic) \ + V(MemoryPeekShortNative, kStatic) \ + V(MemoryPokeByte, kStatic) \ + V(MemoryPokeIntNative, kStatic) \ + V(MemoryPokeLongNative, kStatic) \ + V(MemoryPokeShortNative, kStatic) \ + V(StringCharAt, kDirect) \ + V(StringCompareTo, kDirect) \ + V(StringIsEmpty, kDirect) \ + V(StringIndexOf, kDirect) \ + V(StringIndexOfAfter, kDirect) \ + V(StringLength, kDirect) \ + V(UnsafeCASInt, kDirect) \ + V(UnsafeCASLong, kDirect) \ + V(UnsafeCASObject, kDirect) \ + V(UnsafeGet, kDirect) \ + V(UnsafeGetVolatile, kDirect) \ + V(UnsafeGetLong, kDirect) \ + V(UnsafeGetLongVolatile, kDirect) \ + V(UnsafePut, kDirect) \ + V(UnsafePutOrdered, kDirect) \ + V(UnsafePutVolatile, kDirect) \ + V(UnsafePutObject, kDirect) \ + V(UnsafePutObjectOrdered, kDirect) \ + V(UnsafePutObjectVolatile, kDirect) \ + V(UnsafePutLong, kDirect) \ + V(UnsafePutLongOrdered, kDirect) \ + V(UnsafePutLongVolatile, kDirect) \ + \ + V(ReferenceGetReferent, kVirtual) + +#endif // ART_COMPILER_OPTIMIZING_INTRINSICS_LIST_H_ +#undef ART_COMPILER_OPTIMIZING_INTRINSICS_LIST_H_ // #define is only for lint. diff --git a/compiler/optimizing/intrinsics_x86_64.cc b/compiler/optimizing/intrinsics_x86_64.cc new file mode 100644 index 0000000000..c1f4c94b7f --- /dev/null +++ b/compiler/optimizing/intrinsics_x86_64.cc @@ -0,0 +1,984 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "intrinsics_x86_64.h" + +#include "code_generator_x86_64.h" +#include "entrypoints/quick/quick_entrypoints.h" +#include "intrinsics.h" +#include "mirror/array-inl.h" +#include "mirror/art_method.h" +#include "mirror/string.h" +#include "thread.h" +#include "utils/x86_64/assembler_x86_64.h" +#include "utils/x86_64/constants_x86_64.h" + +namespace art { + +namespace x86_64 { + +static constexpr bool kIntrinsified = true; + +X86_64Assembler* IntrinsicCodeGeneratorX86_64::GetAssembler() { + return reinterpret_cast<X86_64Assembler*>(codegen_->GetAssembler()); +} + +ArenaAllocator* IntrinsicCodeGeneratorX86_64::GetArena() { + return codegen_->GetGraph()->GetArena(); +} + +bool IntrinsicLocationsBuilderX86_64::TryDispatch(HInvoke* invoke) { + Dispatch(invoke); + const LocationSummary* res = invoke->GetLocations(); + return res != nullptr && res->Intrinsified(); +} + +#define __ reinterpret_cast<X86_64Assembler*>(codegen->GetAssembler())-> + +// TODO: trg as memory. +static void MoveFromReturnRegister(Location trg, + Primitive::Type type, + CodeGeneratorX86_64* codegen) { + if (!trg.IsValid()) { + DCHECK(type == Primitive::kPrimVoid); + return; + } + + switch (type) { + case Primitive::kPrimBoolean: + case Primitive::kPrimByte: + case Primitive::kPrimChar: + case Primitive::kPrimShort: + case Primitive::kPrimInt: + case Primitive::kPrimNot: { + CpuRegister trg_reg = trg.AsRegister<CpuRegister>(); + if (trg_reg.AsRegister() != RAX) { + __ movl(trg_reg, CpuRegister(RAX)); + } + break; + } + case Primitive::kPrimLong: { + CpuRegister trg_reg = trg.AsRegister<CpuRegister>(); + if (trg_reg.AsRegister() != RAX) { + __ movq(trg_reg, CpuRegister(RAX)); + } + break; + } + + case Primitive::kPrimVoid: + LOG(FATAL) << "Unexpected void type for valid location " << trg; + UNREACHABLE(); + + case Primitive::kPrimDouble: { + XmmRegister trg_reg = trg.AsFpuRegister<XmmRegister>(); + if (trg_reg.AsFloatRegister() != XMM0) { + __ movsd(trg_reg, XmmRegister(XMM0)); + } + break; + } + case Primitive::kPrimFloat: { + XmmRegister trg_reg = trg.AsFpuRegister<XmmRegister>(); + if (trg_reg.AsFloatRegister() != XMM0) { + __ movss(trg_reg, XmmRegister(XMM0)); + } + break; + } + } +} + +static void MoveArguments(HInvoke* invoke, ArenaAllocator* arena, CodeGeneratorX86_64* codegen) { + if (invoke->InputCount() == 0) { + return; + } + + LocationSummary* locations = invoke->GetLocations(); + InvokeDexCallingConventionVisitor calling_convention_visitor; + + // We're moving potentially two or more locations to locations that could overlap, so we need + // a parallel move resolver. + HParallelMove parallel_move(arena); + + for (size_t i = 0; i < invoke->InputCount(); i++) { + HInstruction* input = invoke->InputAt(i); + Location cc_loc = calling_convention_visitor.GetNextLocation(input->GetType()); + Location actual_loc = locations->InAt(i); + + parallel_move.AddMove(new (arena) MoveOperands(actual_loc, cc_loc, nullptr)); + } + + codegen->GetMoveResolver()->EmitNativeCode(¶llel_move); +} + +// Slow-path for fallback (calling the managed code to handle the intrinsic) in an intrinsified +// call. This will copy the arguments into the positions for a regular call. +// +// Note: The actual parameters are required to be in the locations given by the invoke's location +// summary. If an intrinsic modifies those locations before a slowpath call, they must be +// restored! +class IntrinsicSlowPathX86_64 : public SlowPathCodeX86_64 { + public: + explicit IntrinsicSlowPathX86_64(HInvoke* invoke) : invoke_(invoke) { } + + void EmitNativeCode(CodeGenerator* codegen_in) OVERRIDE { + CodeGeneratorX86_64* codegen = down_cast<CodeGeneratorX86_64*>(codegen_in); + __ Bind(GetEntryLabel()); + + codegen->SaveLiveRegisters(invoke_->GetLocations()); + + MoveArguments(invoke_, codegen->GetGraph()->GetArena(), codegen); + + if (invoke_->IsInvokeStaticOrDirect()) { + codegen->GenerateStaticOrDirectCall(invoke_->AsInvokeStaticOrDirect(), CpuRegister(RDI)); + } else { + UNIMPLEMENTED(FATAL) << "Non-direct intrinsic slow-path not yet implemented"; + UNREACHABLE(); + } + + // Copy the result back to the expected output. + Location out = invoke_->GetLocations()->Out(); + if (out.IsValid()) { + DCHECK(out.IsRegister()); // TODO: Replace this when we support output in memory. + DCHECK(!invoke_->GetLocations()->GetLiveRegisters()->ContainsCoreRegister(out.reg())); + MoveFromReturnRegister(out, invoke_->GetType(), codegen); + } + + codegen->RestoreLiveRegisters(invoke_->GetLocations()); + __ jmp(GetExitLabel()); + } + + private: + // The instruction where this slow path is happening. + HInvoke* const invoke_; + + DISALLOW_COPY_AND_ASSIGN(IntrinsicSlowPathX86_64); +}; + +#undef __ +#define __ assembler-> + +static void CreateFPToIntLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresFpuRegister()); + locations->SetOut(Location::RequiresRegister()); +} + +static void CreateIntToFPLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetOut(Location::RequiresFpuRegister()); +} + +static void MoveFPToInt(LocationSummary* locations, bool is64bit, X86_64Assembler* assembler) { + Location input = locations->InAt(0); + Location output = locations->Out(); + __ movd(output.AsRegister<CpuRegister>(), input.AsFpuRegister<XmmRegister>(), is64bit); +} + +static void MoveIntToFP(LocationSummary* locations, bool is64bit, X86_64Assembler* assembler) { + Location input = locations->InAt(0); + Location output = locations->Out(); + __ movd(output.AsFpuRegister<XmmRegister>(), input.AsRegister<CpuRegister>(), is64bit); +} + +void IntrinsicLocationsBuilderX86_64::VisitDoubleDoubleToRawLongBits(HInvoke* invoke) { + CreateFPToIntLocations(arena_, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitDoubleLongBitsToDouble(HInvoke* invoke) { + CreateIntToFPLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitDoubleDoubleToRawLongBits(HInvoke* invoke) { + MoveFPToInt(invoke->GetLocations(), true, GetAssembler()); +} +void IntrinsicCodeGeneratorX86_64::VisitDoubleLongBitsToDouble(HInvoke* invoke) { + MoveIntToFP(invoke->GetLocations(), true, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitFloatFloatToRawIntBits(HInvoke* invoke) { + CreateFPToIntLocations(arena_, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitFloatIntBitsToFloat(HInvoke* invoke) { + CreateIntToFPLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitFloatFloatToRawIntBits(HInvoke* invoke) { + MoveFPToInt(invoke->GetLocations(), false, GetAssembler()); +} +void IntrinsicCodeGeneratorX86_64::VisitFloatIntBitsToFloat(HInvoke* invoke) { + MoveIntToFP(invoke->GetLocations(), false, GetAssembler()); +} + +static void CreateIntToIntLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetOut(Location::SameAsFirstInput()); +} + +static void GenReverseBytes(LocationSummary* locations, + Primitive::Type size, + X86_64Assembler* assembler) { + CpuRegister out = locations->Out().AsRegister<CpuRegister>(); + + switch (size) { + case Primitive::kPrimShort: + // TODO: Can be done with an xchg of 8b registers. This is straight from Quick. + __ bswapl(out); + __ sarl(out, Immediate(16)); + break; + case Primitive::kPrimInt: + __ bswapl(out); + break; + case Primitive::kPrimLong: + __ bswapq(out); + break; + default: + LOG(FATAL) << "Unexpected size for reverse-bytes: " << size; + UNREACHABLE(); + } +} + +void IntrinsicLocationsBuilderX86_64::VisitIntegerReverseBytes(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitIntegerReverseBytes(HInvoke* invoke) { + GenReverseBytes(invoke->GetLocations(), Primitive::kPrimInt, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitLongReverseBytes(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitLongReverseBytes(HInvoke* invoke) { + GenReverseBytes(invoke->GetLocations(), Primitive::kPrimLong, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitShortReverseBytes(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitShortReverseBytes(HInvoke* invoke) { + GenReverseBytes(invoke->GetLocations(), Primitive::kPrimShort, GetAssembler()); +} + + +// TODO: Consider Quick's way of doing Double abs through integer operations, as the immediate we +// need is 64b. + +static void CreateFloatToFloatPlusTemps(ArenaAllocator* arena, HInvoke* invoke) { + // TODO: Enable memory operations when the assembler supports them. + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresFpuRegister()); + // TODO: Allow x86 to work with memory. This requires assembler support, see below. + // locations->SetInAt(0, Location::Any()); // X86 can work on memory directly. + locations->SetOut(Location::SameAsFirstInput()); + locations->AddTemp(Location::RequiresRegister()); // Immediate constant. + locations->AddTemp(Location::RequiresFpuRegister()); // FP version of above. +} + +static void MathAbsFP(LocationSummary* locations, bool is64bit, X86_64Assembler* assembler) { + Location output = locations->Out(); + CpuRegister cpu_temp = locations->GetTemp(0).AsRegister<CpuRegister>(); + + if (output.IsFpuRegister()) { + // In-register + XmmRegister xmm_temp = locations->GetTemp(1).AsFpuRegister<XmmRegister>(); + + if (is64bit) { + __ movq(cpu_temp, Immediate(INT64_C(0x7FFFFFFFFFFFFFFF))); + __ movd(xmm_temp, cpu_temp); + __ andpd(output.AsFpuRegister<XmmRegister>(), xmm_temp); + } else { + __ movl(cpu_temp, Immediate(INT64_C(0x7FFFFFFF))); + __ movd(xmm_temp, cpu_temp); + __ andps(output.AsFpuRegister<XmmRegister>(), xmm_temp); + } + } else { + // TODO: update when assember support is available. + UNIMPLEMENTED(FATAL) << "Needs assembler support."; +// Once assembler support is available, in-memory operations look like this: +// if (is64bit) { +// DCHECK(output.IsDoubleStackSlot()); +// // No 64b and with literal. +// __ movq(cpu_temp, Immediate(INT64_C(0x7FFFFFFFFFFFFFFF))); +// __ andq(Address(CpuRegister(RSP), output.GetStackIndex()), cpu_temp); +// } else { +// DCHECK(output.IsStackSlot()); +// // Can use and with a literal directly. +// __ andl(Address(CpuRegister(RSP), output.GetStackIndex()), Immediate(INT64_C(0x7FFFFFFF))); +// } + } +} + +void IntrinsicLocationsBuilderX86_64::VisitMathAbsDouble(HInvoke* invoke) { + CreateFloatToFloatPlusTemps(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathAbsDouble(HInvoke* invoke) { + MathAbsFP(invoke->GetLocations(), true, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathAbsFloat(HInvoke* invoke) { + CreateFloatToFloatPlusTemps(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathAbsFloat(HInvoke* invoke) { + MathAbsFP(invoke->GetLocations(), false, GetAssembler()); +} + +static void CreateIntToIntPlusTemp(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetOut(Location::SameAsFirstInput()); + locations->AddTemp(Location::RequiresRegister()); +} + +static void GenAbsInteger(LocationSummary* locations, bool is64bit, X86_64Assembler* assembler) { + Location output = locations->Out(); + CpuRegister out = output.AsRegister<CpuRegister>(); + CpuRegister mask = locations->GetTemp(0).AsRegister<CpuRegister>(); + + if (is64bit) { + // Create mask. + __ movq(mask, out); + __ sarq(mask, Immediate(63)); + // Add mask. + __ addq(out, mask); + __ xorq(out, mask); + } else { + // Create mask. + __ movl(mask, out); + __ sarl(mask, Immediate(31)); + // Add mask. + __ addl(out, mask); + __ xorl(out, mask); + } +} + +void IntrinsicLocationsBuilderX86_64::VisitMathAbsInt(HInvoke* invoke) { + CreateIntToIntPlusTemp(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathAbsInt(HInvoke* invoke) { + GenAbsInteger(invoke->GetLocations(), false, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathAbsLong(HInvoke* invoke) { + CreateIntToIntPlusTemp(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathAbsLong(HInvoke* invoke) { + GenAbsInteger(invoke->GetLocations(), true, GetAssembler()); +} + +static void GenMinMaxFP(LocationSummary* locations, bool is_min, bool is_double, + X86_64Assembler* assembler) { + Location op1_loc = locations->InAt(0); + Location op2_loc = locations->InAt(1); + Location out_loc = locations->Out(); + XmmRegister out = out_loc.AsFpuRegister<XmmRegister>(); + + // Shortcut for same input locations. + if (op1_loc.Equals(op2_loc)) { + DCHECK(out_loc.Equals(op1_loc)); + return; + } + + // (out := op1) + // out <=? op2 + // if Nan jmp Nan_label + // if out is min jmp done + // if op2 is min jmp op2_label + // handle -0/+0 + // jmp done + // Nan_label: + // out := NaN + // op2_label: + // out := op2 + // done: + // + // This removes one jmp, but needs to copy one input (op1) to out. + // + // TODO: This is straight from Quick (except literal pool). Make NaN an out-of-line slowpath? + + XmmRegister op2 = op2_loc.AsFpuRegister<XmmRegister>(); + + Label nan, done, op2_label; + if (is_double) { + __ ucomisd(out, op2); + } else { + __ ucomiss(out, op2); + } + + __ j(Condition::kParityEven, &nan); + + __ j(is_min ? Condition::kAbove : Condition::kBelow, &op2_label); + __ j(is_min ? Condition::kBelow : Condition::kAbove, &done); + + // Handle 0.0/-0.0. + if (is_min) { + if (is_double) { + __ orpd(out, op2); + } else { + __ orps(out, op2); + } + } else { + if (is_double) { + __ andpd(out, op2); + } else { + __ andps(out, op2); + } + } + __ jmp(&done); + + // NaN handling. + __ Bind(&nan); + CpuRegister cpu_temp = locations->GetTemp(0).AsRegister<CpuRegister>(); + // TODO: Literal pool. Trades 64b immediate in CPU reg for direct memory access. + if (is_double) { + __ movq(cpu_temp, Immediate(INT64_C(0x7FF8000000000000))); + } else { + __ movl(cpu_temp, Immediate(INT64_C(0x7FC00000))); + } + __ movd(out, cpu_temp, is_double); + __ jmp(&done); + + // out := op2; + __ Bind(&op2_label); + if (is_double) { + __ movsd(out, op2); + } else { + __ movss(out, op2); + } + + // Done. + __ Bind(&done); +} + +static void CreateFPFPToFPPlusTempLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresFpuRegister()); + locations->SetInAt(1, Location::RequiresFpuRegister()); + // The following is sub-optimal, but all we can do for now. It would be fine to also accept + // the second input to be the output (we can simply swap inputs). + locations->SetOut(Location::SameAsFirstInput()); + locations->AddTemp(Location::RequiresRegister()); // Immediate constant. +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMinDoubleDouble(HInvoke* invoke) { + CreateFPFPToFPPlusTempLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMinDoubleDouble(HInvoke* invoke) { + GenMinMaxFP(invoke->GetLocations(), true, true, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMinFloatFloat(HInvoke* invoke) { + CreateFPFPToFPPlusTempLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMinFloatFloat(HInvoke* invoke) { + GenMinMaxFP(invoke->GetLocations(), true, false, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMaxDoubleDouble(HInvoke* invoke) { + CreateFPFPToFPPlusTempLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMaxDoubleDouble(HInvoke* invoke) { + GenMinMaxFP(invoke->GetLocations(), false, true, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMaxFloatFloat(HInvoke* invoke) { + CreateFPFPToFPPlusTempLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMaxFloatFloat(HInvoke* invoke) { + GenMinMaxFP(invoke->GetLocations(), false, false, GetAssembler()); +} + +static void GenMinMax(LocationSummary* locations, bool is_min, bool is_long, + X86_64Assembler* assembler) { + Location op1_loc = locations->InAt(0); + Location op2_loc = locations->InAt(1); + + // Shortcut for same input locations. + if (op1_loc.Equals(op2_loc)) { + // Can return immediately, as op1_loc == out_loc. + // Note: if we ever support separate registers, e.g., output into memory, we need to check for + // a copy here. + DCHECK(locations->Out().Equals(op1_loc)); + return; + } + + CpuRegister out = locations->Out().AsRegister<CpuRegister>(); + CpuRegister op2 = op2_loc.AsRegister<CpuRegister>(); + + // (out := op1) + // out <=? op2 + // if out is min jmp done + // out := op2 + // done: + + if (is_long) { + __ cmpq(out, op2); + } else { + __ cmpl(out, op2); + } + + __ cmov(is_min ? Condition::kGreater : Condition::kLess, out, op2, is_long); +} + +static void CreateIntIntToIntLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetInAt(1, Location::RequiresRegister()); + locations->SetOut(Location::SameAsFirstInput()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMinIntInt(HInvoke* invoke) { + CreateIntIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMinIntInt(HInvoke* invoke) { + GenMinMax(invoke->GetLocations(), true, false, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMinLongLong(HInvoke* invoke) { + CreateIntIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMinLongLong(HInvoke* invoke) { + GenMinMax(invoke->GetLocations(), true, true, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMaxIntInt(HInvoke* invoke) { + CreateIntIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMaxIntInt(HInvoke* invoke) { + GenMinMax(invoke->GetLocations(), false, false, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathMaxLongLong(HInvoke* invoke) { + CreateIntIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathMaxLongLong(HInvoke* invoke) { + GenMinMax(invoke->GetLocations(), false, true, GetAssembler()); +} + +static void CreateFPToFPLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresFpuRegister()); + locations->SetOut(Location::RequiresFpuRegister()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMathSqrt(HInvoke* invoke) { + CreateFPToFPLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMathSqrt(HInvoke* invoke) { + LocationSummary* locations = invoke->GetLocations(); + XmmRegister in = locations->InAt(0).AsFpuRegister<XmmRegister>(); + XmmRegister out = locations->Out().AsFpuRegister<XmmRegister>(); + + GetAssembler()->sqrtsd(out, in); +} + +void IntrinsicLocationsBuilderX86_64::VisitStringCharAt(HInvoke* invoke) { + // The inputs plus one temp. + LocationSummary* locations = new (arena_) LocationSummary(invoke, + LocationSummary::kCallOnSlowPath, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetInAt(1, Location::RequiresRegister()); + locations->SetOut(Location::SameAsFirstInput()); + locations->AddTemp(Location::RequiresRegister()); +} + +void IntrinsicCodeGeneratorX86_64::VisitStringCharAt(HInvoke* invoke) { + LocationSummary* locations = invoke->GetLocations(); + + // Location of reference to data array + const int32_t value_offset = mirror::String::ValueOffset().Int32Value(); + // Location of count + const int32_t count_offset = mirror::String::CountOffset().Int32Value(); + // Starting offset within data array + const int32_t offset_offset = mirror::String::OffsetOffset().Int32Value(); + // Start of char data with array_ + const int32_t data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); + + CpuRegister obj = locations->InAt(0).AsRegister<CpuRegister>(); + CpuRegister idx = locations->InAt(1).AsRegister<CpuRegister>(); + CpuRegister out = locations->Out().AsRegister<CpuRegister>(); + Location temp_loc = locations->GetTemp(0); + CpuRegister temp = temp_loc.AsRegister<CpuRegister>(); + + // Note: Nullcheck has been done before in a HNullCheck before the HInvokeVirtual. If/when we + // move to (coalesced) implicit checks, we have to do a null check below. + DCHECK(!kCoalescedImplicitNullCheck); + + // TODO: Maybe we can support range check elimination. Overall, though, I think it's not worth + // the cost. + // TODO: For simplicity, the index parameter is requested in a register, so different from Quick + // we will not optimize the code for constants (which would save a register). + + SlowPathCodeX86_64* slow_path = new (GetArena()) IntrinsicSlowPathX86_64(invoke); + codegen_->AddSlowPath(slow_path); + + X86_64Assembler* assembler = GetAssembler(); + + __ cmpl(idx, Address(obj, count_offset)); + __ j(kAboveEqual, slow_path->GetEntryLabel()); + + // Get the actual element. + __ movl(temp, idx); // temp := idx. + __ addl(temp, Address(obj, offset_offset)); // temp := offset + idx. + __ movl(out, Address(obj, value_offset)); // obj := obj.array. + // out = out[2*temp]. + __ movzxw(out, Address(out, temp, ScaleFactor::TIMES_2, data_offset)); + + __ Bind(slow_path->GetExitLabel()); +} + +static void GenPeek(LocationSummary* locations, Primitive::Type size, X86_64Assembler* assembler) { + CpuRegister address = locations->InAt(0).AsRegister<CpuRegister>(); + CpuRegister out = locations->Out().AsRegister<CpuRegister>(); // == address, here for clarity. + // x86 allows unaligned access. We do not have to check the input or use specific instructions + // to avoid a SIGBUS. + switch (size) { + case Primitive::kPrimByte: + __ movsxb(out, Address(address, 0)); + break; + case Primitive::kPrimShort: + __ movsxw(out, Address(address, 0)); + break; + case Primitive::kPrimInt: + __ movl(out, Address(address, 0)); + break; + case Primitive::kPrimLong: + __ movq(out, Address(address, 0)); + break; + default: + LOG(FATAL) << "Type not recognized for peek: " << size; + UNREACHABLE(); + } +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPeekByte(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPeekByte(HInvoke* invoke) { + GenPeek(invoke->GetLocations(), Primitive::kPrimByte, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPeekIntNative(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPeekIntNative(HInvoke* invoke) { + GenPeek(invoke->GetLocations(), Primitive::kPrimInt, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPeekLongNative(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPeekLongNative(HInvoke* invoke) { + GenPeek(invoke->GetLocations(), Primitive::kPrimLong, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPeekShortNative(HInvoke* invoke) { + CreateIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPeekShortNative(HInvoke* invoke) { + GenPeek(invoke->GetLocations(), Primitive::kPrimShort, GetAssembler()); +} + +static void CreateIntIntToVoidLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetInAt(1, Location::RequiresRegister()); +} + +static void GenPoke(LocationSummary* locations, Primitive::Type size, X86_64Assembler* assembler) { + CpuRegister address = locations->InAt(0).AsRegister<CpuRegister>(); + CpuRegister value = locations->InAt(1).AsRegister<CpuRegister>(); + // x86 allows unaligned access. We do not have to check the input or use specific instructions + // to avoid a SIGBUS. + switch (size) { + case Primitive::kPrimByte: + __ movb(Address(address, 0), value); + break; + case Primitive::kPrimShort: + __ movw(Address(address, 0), value); + break; + case Primitive::kPrimInt: + __ movl(Address(address, 0), value); + break; + case Primitive::kPrimLong: + __ movq(Address(address, 0), value); + break; + default: + LOG(FATAL) << "Type not recognized for poke: " << size; + UNREACHABLE(); + } +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPokeByte(HInvoke* invoke) { + CreateIntIntToVoidLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPokeByte(HInvoke* invoke) { + GenPoke(invoke->GetLocations(), Primitive::kPrimByte, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPokeIntNative(HInvoke* invoke) { + CreateIntIntToVoidLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPokeIntNative(HInvoke* invoke) { + GenPoke(invoke->GetLocations(), Primitive::kPrimInt, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPokeLongNative(HInvoke* invoke) { + CreateIntIntToVoidLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPokeLongNative(HInvoke* invoke) { + GenPoke(invoke->GetLocations(), Primitive::kPrimLong, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitMemoryPokeShortNative(HInvoke* invoke) { + CreateIntIntToVoidLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitMemoryPokeShortNative(HInvoke* invoke) { + GenPoke(invoke->GetLocations(), Primitive::kPrimShort, GetAssembler()); +} + +void IntrinsicLocationsBuilderX86_64::VisitThreadCurrentThread(HInvoke* invoke) { + LocationSummary* locations = new (arena_) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetOut(Location::RequiresRegister()); +} + +void IntrinsicCodeGeneratorX86_64::VisitThreadCurrentThread(HInvoke* invoke) { + CpuRegister out = invoke->GetLocations()->Out().AsRegister<CpuRegister>(); + GetAssembler()->gs()->movl(out, Address::Absolute(Thread::PeerOffset<kX86_64WordSize>(), true)); +} + +static void GenUnsafeGet(LocationSummary* locations, bool is_long, + bool is_volatile ATTRIBUTE_UNUSED, X86_64Assembler* assembler) { + CpuRegister base = locations->InAt(1).AsRegister<CpuRegister>(); + CpuRegister offset = locations->InAt(2).AsRegister<CpuRegister>(); + CpuRegister trg = locations->Out().AsRegister<CpuRegister>(); + + if (is_long) { + __ movq(trg, Address(base, offset, ScaleFactor::TIMES_1, 0)); + } else { + // TODO: Distinguish object. In case we move to an actual compressed heap, retrieving an object + // pointer will entail an unpack operation. + __ movl(trg, Address(base, offset, ScaleFactor::TIMES_1, 0)); + } +} + +static void CreateIntIntIntToIntLocations(ArenaAllocator* arena, HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::RequiresRegister()); + locations->SetInAt(1, Location::RequiresRegister()); + locations->SetInAt(2, Location::RequiresRegister()); + locations->SetOut(Location::SameAsFirstInput()); +} + +void IntrinsicLocationsBuilderX86_64::VisitUnsafeGet(HInvoke* invoke) { + CreateIntIntIntToIntLocations(arena_, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafeGetVolatile(HInvoke* invoke) { + CreateIntIntIntToIntLocations(arena_, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafeGetLong(HInvoke* invoke) { + CreateIntIntIntToIntLocations(arena_, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafeGetLongVolatile(HInvoke* invoke) { + CreateIntIntIntToIntLocations(arena_, invoke); +} + +void IntrinsicCodeGeneratorX86_64::VisitUnsafeGet(HInvoke* invoke) { + GenUnsafeGet(invoke->GetLocations(), false, false, GetAssembler()); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafeGetVolatile(HInvoke* invoke) { + GenUnsafeGet(invoke->GetLocations(), false, true, GetAssembler()); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafeGetLong(HInvoke* invoke) { + GenUnsafeGet(invoke->GetLocations(), true, false, GetAssembler()); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafeGetLongVolatile(HInvoke* invoke) { + GenUnsafeGet(invoke->GetLocations(), true, true, GetAssembler()); +} + +static void CreateIntIntIntIntToVoidPlusTempsLocations(ArenaAllocator* arena, + Primitive::Type type, + HInvoke* invoke) { + LocationSummary* locations = new (arena) LocationSummary(invoke, + LocationSummary::kNoCall, + kIntrinsified); + locations->SetInAt(0, Location::NoLocation()); + locations->SetInAt(1, Location::RequiresRegister()); + locations->SetInAt(2, Location::RequiresRegister()); + locations->SetInAt(3, Location::RequiresRegister()); + if (type == Primitive::kPrimNot) { + // Need temp registers for card-marking. + locations->AddTemp(Location::RequiresRegister()); + locations->AddTemp(Location::RequiresRegister()); + } +} + +void IntrinsicLocationsBuilderX86_64::VisitUnsafePut(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimInt, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutOrdered(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimInt, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutVolatile(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimInt, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutObject(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimNot, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutObjectOrdered(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimNot, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutObjectVolatile(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimNot, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutLong(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimLong, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutLongOrdered(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimLong, invoke); +} +void IntrinsicLocationsBuilderX86_64::VisitUnsafePutLongVolatile(HInvoke* invoke) { + CreateIntIntIntIntToVoidPlusTempsLocations(arena_, Primitive::kPrimLong, invoke); +} + +// We don't care for ordered: it requires an AnyStore barrier, which is already given by the x86 +// memory model. +static void GenUnsafePut(LocationSummary* locations, Primitive::Type type, bool is_volatile, + CodeGeneratorX86_64* codegen) { + X86_64Assembler* assembler = reinterpret_cast<X86_64Assembler*>(codegen->GetAssembler()); + CpuRegister base = locations->InAt(1).AsRegister<CpuRegister>(); + CpuRegister offset = locations->InAt(2).AsRegister<CpuRegister>(); + CpuRegister value = locations->InAt(3).AsRegister<CpuRegister>(); + + if (type == Primitive::kPrimLong) { + __ movq(Address(base, offset, ScaleFactor::TIMES_1, 0), value); + } else { + __ movl(Address(base, offset, ScaleFactor::TIMES_1, 0), value); + } + + if (is_volatile) { + __ mfence(); + } + + if (type == Primitive::kPrimNot) { + codegen->MarkGCCard(locations->GetTemp(0).AsRegister<CpuRegister>(), + locations->GetTemp(1).AsRegister<CpuRegister>(), + base, + value); + } +} + +void IntrinsicCodeGeneratorX86_64::VisitUnsafePut(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimInt, false, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutOrdered(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimInt, false, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutVolatile(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimInt, true, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutObject(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimNot, false, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutObjectOrdered(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimNot, false, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutObjectVolatile(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimNot, true, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutLong(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimLong, false, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutLongOrdered(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimLong, false, codegen_); +} +void IntrinsicCodeGeneratorX86_64::VisitUnsafePutLongVolatile(HInvoke* invoke) { + GenUnsafePut(invoke->GetLocations(), Primitive::kPrimLong, true, codegen_); +} + +// Unimplemented intrinsics. + +#define UNIMPLEMENTED_INTRINSIC(Name) \ +void IntrinsicLocationsBuilderX86_64::Visit ## Name(HInvoke* invoke ATTRIBUTE_UNUSED) { \ +} \ +void IntrinsicCodeGeneratorX86_64::Visit ## Name(HInvoke* invoke ATTRIBUTE_UNUSED) { \ +} + +UNIMPLEMENTED_INTRINSIC(IntegerReverse) +UNIMPLEMENTED_INTRINSIC(LongReverse) +UNIMPLEMENTED_INTRINSIC(MathFloor) +UNIMPLEMENTED_INTRINSIC(MathCeil) +UNIMPLEMENTED_INTRINSIC(MathRint) +UNIMPLEMENTED_INTRINSIC(MathRoundDouble) +UNIMPLEMENTED_INTRINSIC(MathRoundFloat) +UNIMPLEMENTED_INTRINSIC(StringIsEmpty) // Might not want to do these two anyways, inlining should +UNIMPLEMENTED_INTRINSIC(StringLength) // be good enough here. +UNIMPLEMENTED_INTRINSIC(StringCompareTo) +UNIMPLEMENTED_INTRINSIC(StringIndexOf) +UNIMPLEMENTED_INTRINSIC(StringIndexOfAfter) +UNIMPLEMENTED_INTRINSIC(SystemArrayCopyChar) +UNIMPLEMENTED_INTRINSIC(UnsafeCASInt) +UNIMPLEMENTED_INTRINSIC(UnsafeCASLong) +UNIMPLEMENTED_INTRINSIC(UnsafeCASObject) +UNIMPLEMENTED_INTRINSIC(ReferenceGetReferent) + +} // namespace x86_64 +} // namespace art diff --git a/compiler/optimizing/intrinsics_x86_64.h b/compiler/optimizing/intrinsics_x86_64.h new file mode 100644 index 0000000000..c1fa99c2dc --- /dev/null +++ b/compiler/optimizing/intrinsics_x86_64.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_COMPILER_OPTIMIZING_INTRINSICS_X86_64_H_ +#define ART_COMPILER_OPTIMIZING_INTRINSICS_X86_64_H_ + +#include "intrinsics.h" + +namespace art { + +class ArenaAllocator; +class HInvokeStaticOrDirect; +class HInvokeVirtual; + +namespace x86_64 { + +class CodeGeneratorX86_64; +class X86_64Assembler; + +class IntrinsicLocationsBuilderX86_64 FINAL : public IntrinsicVisitor { + public: + explicit IntrinsicLocationsBuilderX86_64(ArenaAllocator* arena) : arena_(arena) {} + + // Define visitor methods. + +#define OPTIMIZING_INTRINSICS(Name, IsStatic) \ + void Visit ## Name(HInvoke* invoke) OVERRIDE; +#include "intrinsics_list.h" +INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS + + // Check whether an invoke is an intrinsic, and if so, create a location summary. Returns whether + // a corresponding LocationSummary with the intrinsified_ flag set was generated and attached to + // the invoke. + bool TryDispatch(HInvoke* invoke); + + private: + ArenaAllocator* arena_; + + DISALLOW_COPY_AND_ASSIGN(IntrinsicLocationsBuilderX86_64); +}; + +class IntrinsicCodeGeneratorX86_64 FINAL : public IntrinsicVisitor { + public: + explicit IntrinsicCodeGeneratorX86_64(CodeGeneratorX86_64* codegen) : codegen_(codegen) {} + + // Define visitor methods. + +#define OPTIMIZING_INTRINSICS(Name, IsStatic) \ + void Visit ## Name(HInvoke* invoke) OVERRIDE; +#include "intrinsics_list.h" +INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS + + private: + X86_64Assembler* GetAssembler(); + + ArenaAllocator* GetArena(); + + CodeGeneratorX86_64* codegen_; + + DISALLOW_COPY_AND_ASSIGN(IntrinsicCodeGeneratorX86_64); +}; + +} // namespace x86_64 +} // namespace art + +#endif // ART_COMPILER_OPTIMIZING_INTRINSICS_X86_64_H_ diff --git a/compiler/optimizing/locations.cc b/compiler/optimizing/locations.cc index ed5e260a5b..9f2f9ece85 100644 --- a/compiler/optimizing/locations.cc +++ b/compiler/optimizing/locations.cc @@ -20,7 +20,9 @@ namespace art { -LocationSummary::LocationSummary(HInstruction* instruction, CallKind call_kind) +LocationSummary::LocationSummary(HInstruction* instruction, + CallKind call_kind, + bool intrinsified) : inputs_(instruction->GetBlock()->GetGraph()->GetArena(), instruction->InputCount()), temps_(instruction->GetBlock()->GetGraph()->GetArena(), 0), environment_(instruction->GetBlock()->GetGraph()->GetArena(), @@ -29,7 +31,8 @@ LocationSummary::LocationSummary(HInstruction* instruction, CallKind call_kind) call_kind_(call_kind), stack_mask_(nullptr), register_mask_(0), - live_registers_() { + live_registers_(), + intrinsified_(intrinsified) { inputs_.SetSize(instruction->InputCount()); for (size_t i = 0; i < instruction->InputCount(); ++i) { inputs_.Put(i, Location()); diff --git a/compiler/optimizing/locations.h b/compiler/optimizing/locations.h index 7df99d4b6f..d41b3aecfd 100644 --- a/compiler/optimizing/locations.h +++ b/compiler/optimizing/locations.h @@ -463,7 +463,9 @@ class LocationSummary : public ArenaObject<kArenaAllocMisc> { kCall }; - LocationSummary(HInstruction* instruction, CallKind call_kind = kNoCall); + LocationSummary(HInstruction* instruction, + CallKind call_kind = kNoCall, + bool intrinsified = false); void SetInAt(uint32_t at, Location location) { DCHECK(inputs_.Get(at).IsUnallocated() || inputs_.Get(at).IsInvalid()); @@ -574,6 +576,10 @@ class LocationSummary : public ArenaObject<kArenaAllocMisc> { return output_overlaps_; } + bool Intrinsified() const { + return intrinsified_; + } + private: GrowableArray<Location> inputs_; GrowableArray<Location> temps_; @@ -593,6 +599,9 @@ class LocationSummary : public ArenaObject<kArenaAllocMisc> { // Registers that are in use at this position. RegisterSet live_registers_; + // Whether these are locations for an intrinsified call. + const bool intrinsified_; + ART_FRIEND_TEST(RegisterAllocatorTest, ExpectedInRegisterHint); ART_FRIEND_TEST(RegisterAllocatorTest, SameAsFirstInputHint); DISALLOW_COPY_AND_ASSIGN(LocationSummary); diff --git a/compiler/optimizing/nodes.h b/compiler/optimizing/nodes.h index b98bc70a9f..f2aa043849 100644 --- a/compiler/optimizing/nodes.h +++ b/compiler/optimizing/nodes.h @@ -1580,19 +1580,18 @@ class HLongConstant : public HConstant { DISALLOW_COPY_AND_ASSIGN(HLongConstant); }; +enum class Intrinsics { +#define OPTIMIZING_INTRINSICS(Name, IsStatic) k ## Name, +#include "intrinsics_list.h" + kNone, + INTRINSICS_LIST(OPTIMIZING_INTRINSICS) +#undef INTRINSICS_LIST +#undef OPTIMIZING_INTRINSICS +}; +std::ostream& operator<<(std::ostream& os, const Intrinsics& intrinsic); + class HInvoke : public HInstruction { public: - HInvoke(ArenaAllocator* arena, - uint32_t number_of_arguments, - Primitive::Type return_type, - uint32_t dex_pc) - : HInstruction(SideEffects::All()), - inputs_(arena, number_of_arguments), - return_type_(return_type), - dex_pc_(dex_pc) { - inputs_.SetSize(number_of_arguments); - } - virtual size_t InputCount() const { return inputs_.Size(); } virtual HInstruction* InputAt(size_t i) const { return inputs_.Get(i); } @@ -1612,12 +1611,38 @@ class HInvoke : public HInstruction { uint32_t GetDexPc() const { return dex_pc_; } + uint32_t GetDexMethodIndex() const { return dex_method_index_; } + + Intrinsics GetIntrinsic() { + return intrinsic_; + } + + void SetIntrinsic(Intrinsics intrinsic) { + intrinsic_ = intrinsic; + } + DECLARE_INSTRUCTION(Invoke); protected: + HInvoke(ArenaAllocator* arena, + uint32_t number_of_arguments, + Primitive::Type return_type, + uint32_t dex_pc, + uint32_t dex_method_index) + : HInstruction(SideEffects::All()), + inputs_(arena, number_of_arguments), + return_type_(return_type), + dex_pc_(dex_pc), + dex_method_index_(dex_method_index), + intrinsic_(Intrinsics::kNone) { + inputs_.SetSize(number_of_arguments); + } + GrowableArray<HInstruction*> inputs_; const Primitive::Type return_type_; const uint32_t dex_pc_; + const uint32_t dex_method_index_; + Intrinsics intrinsic_; private: DISALLOW_COPY_AND_ASSIGN(HInvoke); @@ -1629,19 +1654,16 @@ class HInvokeStaticOrDirect : public HInvoke { uint32_t number_of_arguments, Primitive::Type return_type, uint32_t dex_pc, - uint32_t index_in_dex_cache, + uint32_t dex_method_index, InvokeType invoke_type) - : HInvoke(arena, number_of_arguments, return_type, dex_pc), - index_in_dex_cache_(index_in_dex_cache), + : HInvoke(arena, number_of_arguments, return_type, dex_pc, dex_method_index), invoke_type_(invoke_type) {} - uint32_t GetIndexInDexCache() const { return index_in_dex_cache_; } InvokeType GetInvokeType() const { return invoke_type_; } DECLARE_INSTRUCTION(InvokeStaticOrDirect); private: - const uint32_t index_in_dex_cache_; const InvokeType invoke_type_; DISALLOW_COPY_AND_ASSIGN(HInvokeStaticOrDirect); @@ -1653,8 +1675,9 @@ class HInvokeVirtual : public HInvoke { uint32_t number_of_arguments, Primitive::Type return_type, uint32_t dex_pc, + uint32_t dex_method_index, uint32_t vtable_index) - : HInvoke(arena, number_of_arguments, return_type, dex_pc), + : HInvoke(arena, number_of_arguments, return_type, dex_pc, dex_method_index), vtable_index_(vtable_index) {} uint32_t GetVTableIndex() const { return vtable_index_; } @@ -1675,8 +1698,7 @@ class HInvokeInterface : public HInvoke { uint32_t dex_pc, uint32_t dex_method_index, uint32_t imt_index) - : HInvoke(arena, number_of_arguments, return_type, dex_pc), - dex_method_index_(dex_method_index), + : HInvoke(arena, number_of_arguments, return_type, dex_pc, dex_method_index), imt_index_(imt_index) {} uint32_t GetImtIndex() const { return imt_index_; } @@ -1685,7 +1707,6 @@ class HInvokeInterface : public HInvoke { DECLARE_INSTRUCTION(InvokeInterface); private: - const uint32_t dex_method_index_; const uint32_t imt_index_; DISALLOW_COPY_AND_ASSIGN(HInvokeInterface); @@ -2775,10 +2796,16 @@ class HParallelMove : public HTemplateInstruction<0> { : HTemplateInstruction(SideEffects::None()), moves_(arena, kDefaultNumberOfMoves) {} void AddMove(MoveOperands* move) { - if (kIsDebugBuild && move->GetInstruction() != nullptr) { + if (kIsDebugBuild) { + if (move->GetInstruction() != nullptr) { + for (size_t i = 0, e = moves_.Size(); i < e; ++i) { + DCHECK_NE(moves_.Get(i)->GetInstruction(), move->GetInstruction()) + << "Doing parallel moves for the same instruction."; + } + } for (size_t i = 0, e = moves_.Size(); i < e; ++i) { - DCHECK_NE(moves_.Get(i)->GetInstruction(), move->GetInstruction()) - << "Doing parallel moves for the same instruction."; + DCHECK(!move->GetDestination().Contains(moves_.Get(i)->GetDestination())) + << "Same destination for two moves in a parallel move."; } } moves_.Add(move); diff --git a/compiler/optimizing/optimizing_compiler.cc b/compiler/optimizing/optimizing_compiler.cc index 692d452f54..605637300f 100644 --- a/compiler/optimizing/optimizing_compiler.cc +++ b/compiler/optimizing/optimizing_compiler.cc @@ -25,6 +25,7 @@ #include "compiler.h" #include "constant_folding.h" #include "dead_code_elimination.h" +#include "dex/quick/dex_file_to_method_inliner_map.h" #include "driver/compiler_driver.h" #include "driver/dex_compilation_unit.h" #include "elf_writer_quick.h" @@ -32,6 +33,7 @@ #include "gvn.h" #include "inliner.h" #include "instruction_simplifier.h" +#include "intrinsics.h" #include "jni/quick/jni_compiler.h" #include "mirror/art_method-inl.h" #include "nodes.h" @@ -149,11 +151,12 @@ void OptimizingCompiler::Init() { // Enable C1visualizer output. Must be done in Init() because the compiler // driver is not fully initialized when passed to the compiler's constructor. CompilerDriver* driver = GetCompilerDriver(); - if (driver->GetDumpPasses()) { + const std::string cfg_file_name = driver->GetDumpCfgFileName(); + if (!cfg_file_name.empty()) { CHECK_EQ(driver->GetThreadCount(), 1U) << "Graph visualizer requires the compiler to run single-threaded. " << "Invoke the compiler with '-j1'."; - visualizer_output_.reset(new std::ofstream("art.cfg")); + visualizer_output_.reset(new std::ofstream(cfg_file_name)); } } @@ -214,9 +217,12 @@ static void RunOptimizations(HGraph* graph, BoundsCheckElimination bce(graph); InstructionSimplifier simplify2(graph); + IntrinsicsRecognizer intrinsics(graph, dex_compilation_unit.GetDexFile(), driver); + HOptimization* optimizations[] = { &redundant_phi, &dead_phi, + &intrinsics, &dce, &fold, &simplify1, diff --git a/compiler/optimizing/optimizing_unit_test.h b/compiler/optimizing/optimizing_unit_test.h index 04b56345c4..b3eb1e2d51 100644 --- a/compiler/optimizing/optimizing_unit_test.h +++ b/compiler/optimizing/optimizing_unit_test.h @@ -45,8 +45,12 @@ namespace art { LiveInterval* BuildInterval(const size_t ranges[][2], size_t number_of_ranges, ArenaAllocator* allocator, - int reg = -1) { - LiveInterval* interval = LiveInterval::MakeInterval(allocator, Primitive::kPrimInt); + int reg = -1, + HInstruction* defined_by = nullptr) { + LiveInterval* interval = LiveInterval::MakeInterval(allocator, Primitive::kPrimInt, defined_by); + if (defined_by != nullptr) { + defined_by->SetLiveInterval(interval); + } for (size_t i = number_of_ranges; i > 0; --i) { interval->AddRange(ranges[i - 1][0], ranges[i - 1][1]); } diff --git a/compiler/optimizing/parallel_move_test.cc b/compiler/optimizing/parallel_move_test.cc index 210f7d7f09..7ab41b6ddc 100644 --- a/compiler/optimizing/parallel_move_test.cc +++ b/compiler/optimizing/parallel_move_test.cc @@ -120,16 +120,9 @@ TEST(ParallelMoveTest, Swap) { { TestParallelMoveResolver resolver(&allocator); - static constexpr size_t moves[][2] = {{0, 1}, {1, 2}, {2, 3}, {3, 4}, {4, 1}}; + static constexpr size_t moves[][2] = {{0, 1}, {1, 2}, {2, 3}, {3, 4}, {4, 0}}; resolver.EmitNativeCode(BuildParallelMove(&allocator, moves, arraysize(moves))); - ASSERT_STREQ("(4 <-> 1) (3 <-> 4) (2 <-> 3) (0 -> 1)", resolver.GetMessage().c_str()); - } - - { - TestParallelMoveResolver resolver(&allocator); - static constexpr size_t moves[][2] = {{0, 1}, {1, 2}, {2, 3}, {3, 4}, {4, 1}, {5, 4}}; - resolver.EmitNativeCode(BuildParallelMove(&allocator, moves, arraysize(moves))); - ASSERT_STREQ("(4 <-> 1) (3 <-> 4) (2 <-> 3) (0 -> 1) (5 -> 4)", resolver.GetMessage().c_str()); + ASSERT_STREQ("(4 <-> 0) (3 <-> 4) (2 <-> 3) (1 <-> 2)", resolver.GetMessage().c_str()); } } diff --git a/compiler/optimizing/register_allocator.cc b/compiler/optimizing/register_allocator.cc index 1efc52b9ec..93ed44ee44 100644 --- a/compiler/optimizing/register_allocator.cc +++ b/compiler/optimizing/register_allocator.cc @@ -56,7 +56,8 @@ RegisterAllocator::RegisterAllocator(ArenaAllocator* allocator, blocked_core_registers_(codegen->GetBlockedCoreRegisters()), blocked_fp_registers_(codegen->GetBlockedFloatingPointRegisters()), reserved_out_slots_(0), - maximum_number_of_live_registers_(0) { + maximum_number_of_live_core_registers_(0), + maximum_number_of_live_fp_registers_(0) { codegen->SetupBlockedRegisters(); physical_core_register_intervals_.SetSize(codegen->GetNumberOfCoreRegisters()); physical_fp_register_intervals_.SetSize(codegen->GetNumberOfFloatingPointRegisters()); @@ -185,9 +186,6 @@ void RegisterAllocator::AllocateRegistersInternal() { } LinearScan(); - size_t saved_maximum_number_of_live_registers = maximum_number_of_live_registers_; - maximum_number_of_live_registers_ = 0; - inactive_.Reset(); active_.Reset(); handled_.Reset(); @@ -207,7 +205,6 @@ void RegisterAllocator::AllocateRegistersInternal() { } } LinearScan(); - maximum_number_of_live_registers_ += saved_maximum_number_of_live_registers; } void RegisterAllocator::ProcessInstruction(HInstruction* instruction) { @@ -602,8 +599,13 @@ void RegisterAllocator::LinearScan() { if (current->IsSlowPathSafepoint()) { // Synthesized interval to record the maximum number of live registers // at safepoints. No need to allocate a register for it. - maximum_number_of_live_registers_ = - std::max(maximum_number_of_live_registers_, active_.Size()); + if (processing_core_registers_) { + maximum_number_of_live_core_registers_ = + std::max(maximum_number_of_live_core_registers_, active_.Size()); + } else { + maximum_number_of_live_fp_registers_ = + std::max(maximum_number_of_live_fp_registers_, active_.Size()); + } DCHECK(unhandled_->IsEmpty() || unhandled_->Peek()->GetStart() > current->GetStart()); continue; } @@ -855,7 +857,9 @@ bool RegisterAllocator::AllocateBlockedReg(LiveInterval* current) { DCHECK(!active->IsFixed()); LiveInterval* split = Split(active, current->GetStart()); active_.DeleteAt(i); - handled_.Add(active); + if (split != active) { + handled_.Add(active); + } AddSorted(unhandled_, split); break; } @@ -876,9 +880,14 @@ bool RegisterAllocator::AllocateBlockedReg(LiveInterval* current) { if (next_intersection != kNoLifetime) { if (inactive->IsFixed()) { LiveInterval* split = Split(current, next_intersection); + DCHECK_NE(split, current); AddSorted(unhandled_, split); } else { - LiveInterval* split = Split(inactive, next_intersection); + // Split at the start of `current`, which will lead to splitting + // at the end of the lifetime hole of `inactive`. + LiveInterval* split = Split(inactive, current->GetStart()); + // If it's inactive, it must start before the current interval. + DCHECK_NE(split, inactive); inactive_.DeleteAt(i); --i; --e; @@ -1215,10 +1224,17 @@ void RegisterAllocator::ConnectSiblings(LiveInterval* interval) { locations->SetEnvironmentAt(use->GetInputIndex(), source); } else { Location expected_location = locations->InAt(use->GetInputIndex()); - if (expected_location.IsUnallocated()) { - locations->SetInAt(use->GetInputIndex(), source); - } else if (!expected_location.IsConstant()) { - AddInputMoveFor(use->GetUser(), source, expected_location); + // The expected (actual) location may be invalid in case the input is unused. Currently + // this only happens for intrinsics. + if (expected_location.IsValid()) { + if (expected_location.IsUnallocated()) { + locations->SetInAt(use->GetInputIndex(), source); + } else if (!expected_location.IsConstant()) { + AddInputMoveFor(use->GetUser(), source, expected_location); + } + } else { + DCHECK(use->GetUser()->IsInvoke()); + DCHECK(use->GetUser()->AsInvoke()->GetIntrinsic() != Intrinsics::kNone); } } use = use->GetNext(); @@ -1255,8 +1271,9 @@ void RegisterAllocator::ConnectSiblings(LiveInterval* interval) { switch (source.GetKind()) { case Location::kRegister: { locations->AddLiveRegister(source); - DCHECK_LE(locations->GetNumberOfLiveRegisters(), maximum_number_of_live_registers_); - + DCHECK_LE(locations->GetNumberOfLiveRegisters(), + maximum_number_of_live_core_registers_ + + maximum_number_of_live_fp_registers_); if (current->GetType() == Primitive::kPrimNot) { locations->SetRegisterBit(source.reg()); } @@ -1349,7 +1366,8 @@ void RegisterAllocator::ConnectSplitSiblings(LiveInterval* interval, void RegisterAllocator::Resolve() { codegen_->ComputeFrameSize( - spill_slots_.Size(), maximum_number_of_live_registers_, reserved_out_slots_); + spill_slots_.Size(), maximum_number_of_live_core_registers_, + maximum_number_of_live_fp_registers_, reserved_out_slots_); // Adjust the Out Location of instructions. // TODO: Use pointers of Location inside LiveInterval to avoid doing another iteration. diff --git a/compiler/optimizing/register_allocator.h b/compiler/optimizing/register_allocator.h index c152a8bf67..ec46a776b5 100644 --- a/compiler/optimizing/register_allocator.h +++ b/compiler/optimizing/register_allocator.h @@ -190,10 +190,14 @@ class RegisterAllocator { // Slots reserved for out arguments. size_t reserved_out_slots_; - // The maximum live registers at safepoints. - size_t maximum_number_of_live_registers_; + // The maximum live core registers at safepoints. + size_t maximum_number_of_live_core_registers_; + + // The maximum live FP registers at safepoints. + size_t maximum_number_of_live_fp_registers_; ART_FRIEND_TEST(RegisterAllocatorTest, FreeUntil); + ART_FRIEND_TEST(RegisterAllocatorTest, SpillInactive); DISALLOW_COPY_AND_ASSIGN(RegisterAllocator); }; diff --git a/compiler/optimizing/register_allocator_test.cc b/compiler/optimizing/register_allocator_test.cc index c2ea80ec33..0948643355 100644 --- a/compiler/optimizing/register_allocator_test.cc +++ b/compiler/optimizing/register_allocator_test.cc @@ -738,4 +738,106 @@ TEST(RegisterAllocatorTest, ExpectedExactInRegisterAndSameOutputHint) { } } +// Test a bug in the register allocator, where allocating a blocked +// register would lead to spilling an inactive interval at the wrong +// position. +TEST(RegisterAllocatorTest, SpillInactive) { + ArenaPool pool; + + // Create a synthesized graph to please the register_allocator and + // ssa_liveness_analysis code. + ArenaAllocator allocator(&pool); + HGraph* graph = new (&allocator) HGraph(&allocator); + HBasicBlock* entry = new (&allocator) HBasicBlock(graph); + graph->AddBlock(entry); + graph->SetEntryBlock(entry); + HInstruction* one = new (&allocator) HParameterValue(0, Primitive::kPrimInt); + HInstruction* two = new (&allocator) HParameterValue(0, Primitive::kPrimInt); + HInstruction* three = new (&allocator) HParameterValue(0, Primitive::kPrimInt); + HInstruction* four = new (&allocator) HParameterValue(0, Primitive::kPrimInt); + entry->AddInstruction(one); + entry->AddInstruction(two); + entry->AddInstruction(three); + entry->AddInstruction(four); + + HBasicBlock* block = new (&allocator) HBasicBlock(graph); + graph->AddBlock(block); + entry->AddSuccessor(block); + block->AddInstruction(new (&allocator) HExit()); + + // We create a synthesized user requesting a register, to avoid just spilling the + // intervals. + HPhi* user = new (&allocator) HPhi(&allocator, 0, 1, Primitive::kPrimInt); + user->AddInput(one); + user->SetBlock(block); + LocationSummary* locations = new (&allocator) LocationSummary(user, LocationSummary::kNoCall); + locations->SetInAt(0, Location::RequiresRegister()); + static constexpr size_t phi_ranges[][2] = {{20, 30}}; + BuildInterval(phi_ranges, arraysize(phi_ranges), &allocator, -1, user); + + // Create an interval with lifetime holes. + static constexpr size_t ranges1[][2] = {{0, 2}, {4, 6}, {8, 10}}; + LiveInterval* first = BuildInterval(ranges1, arraysize(ranges1), &allocator, -1, one); + first->first_use_ = new(&allocator) UsePosition(user, 0, false, 8, first->first_use_); + first->first_use_ = new(&allocator) UsePosition(user, 0, false, 7, first->first_use_); + first->first_use_ = new(&allocator) UsePosition(user, 0, false, 6, first->first_use_); + + locations = new (&allocator) LocationSummary(first->GetDefinedBy(), LocationSummary::kNoCall); + locations->SetOut(Location::RequiresRegister()); + first = first->SplitAt(1); + + // Create an interval that conflicts with the next interval, to force the next + // interval to call `AllocateBlockedReg`. + static constexpr size_t ranges2[][2] = {{2, 4}}; + LiveInterval* second = BuildInterval(ranges2, arraysize(ranges2), &allocator, -1, two); + locations = new (&allocator) LocationSummary(second->GetDefinedBy(), LocationSummary::kNoCall); + locations->SetOut(Location::RequiresRegister()); + + // Create an interval that will lead to splitting the first interval. The bug occured + // by splitting at a wrong position, in this case at the next intersection between + // this interval and the first interval. We would have then put the interval with ranges + // "[0, 2(, [4, 6(" in the list of handled intervals, even though we haven't processed intervals + // before lifetime position 6 yet. + static constexpr size_t ranges3[][2] = {{2, 4}, {8, 10}}; + LiveInterval* third = BuildInterval(ranges3, arraysize(ranges3), &allocator, -1, three); + third->first_use_ = new(&allocator) UsePosition(user, 0, false, 8, third->first_use_); + third->first_use_ = new(&allocator) UsePosition(user, 0, false, 4, third->first_use_); + third->first_use_ = new(&allocator) UsePosition(user, 0, false, 3, third->first_use_); + locations = new (&allocator) LocationSummary(third->GetDefinedBy(), LocationSummary::kNoCall); + locations->SetOut(Location::RequiresRegister()); + third = third->SplitAt(3); + + // Because the first part of the split interval was considered handled, this interval + // was free to allocate the same register, even though it conflicts with it. + static constexpr size_t ranges4[][2] = {{4, 6}}; + LiveInterval* fourth = BuildInterval(ranges4, arraysize(ranges4), &allocator, -1, four); + locations = new (&allocator) LocationSummary(fourth->GetDefinedBy(), LocationSummary::kNoCall); + locations->SetOut(Location::RequiresRegister()); + + x86::CodeGeneratorX86 codegen(graph); + SsaLivenessAnalysis liveness(*graph, &codegen); + + RegisterAllocator register_allocator(&allocator, &codegen, liveness); + register_allocator.unhandled_core_intervals_.Add(fourth); + register_allocator.unhandled_core_intervals_.Add(third); + register_allocator.unhandled_core_intervals_.Add(second); + register_allocator.unhandled_core_intervals_.Add(first); + + // Set just one register available to make all intervals compete for the same. + register_allocator.number_of_registers_ = 1; + register_allocator.registers_array_ = allocator.AllocArray<size_t>(1); + register_allocator.processing_core_registers_ = true; + register_allocator.unhandled_ = ®ister_allocator.unhandled_core_intervals_; + register_allocator.LinearScan(); + + // Test that there is no conflicts between intervals. + GrowableArray<LiveInterval*> intervals(&allocator, 0); + intervals.Add(first); + intervals.Add(second); + intervals.Add(third); + intervals.Add(fourth); + ASSERT_TRUE(RegisterAllocator::ValidateIntervals( + intervals, 0, 0, codegen, &allocator, true, false)); +} + } // namespace art diff --git a/compiler/optimizing/ssa_liveness_analysis.h b/compiler/optimizing/ssa_liveness_analysis.h index 74611e1cbb..b632c4d05a 100644 --- a/compiler/optimizing/ssa_liveness_analysis.h +++ b/compiler/optimizing/ssa_liveness_analysis.h @@ -429,7 +429,7 @@ class LiveInterval : public ArenaObject<kArenaAllocMisc> { LiveRange* current = first_range_; LiveRange* previous = nullptr; // Iterate over the ranges, and either find a range that covers this position, or - // a two ranges in between this position (that is, the position is in a lifetime hole). + // two ranges in between this position (that is, the position is in a lifetime hole). do { if (position >= current->GetEnd()) { // Move to next range. @@ -653,6 +653,8 @@ class LiveInterval : public ArenaObject<kArenaAllocMisc> { static constexpr int kNoRegister = -1; static constexpr int kNoSpillSlot = -1; + ART_FRIEND_TEST(RegisterAllocatorTest, SpillInactive); + DISALLOW_COPY_AND_ASSIGN(LiveInterval); }; diff --git a/compiler/trampolines/trampoline_compiler.cc b/compiler/trampolines/trampoline_compiler.cc index 385d1340fc..cb51ed8fc8 100644 --- a/compiler/trampolines/trampoline_compiler.cc +++ b/compiler/trampolines/trampoline_compiler.cc @@ -20,6 +20,7 @@ #include "utils/arm/assembler_arm.h" #include "utils/arm64/assembler_arm64.h" #include "utils/mips/assembler_mips.h" +#include "utils/mips64/assembler_mips64.h" #include "utils/x86/assembler_x86.h" #include "utils/x86_64/assembler_x86_64.h" @@ -120,6 +121,35 @@ static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention } } // namespace mips +namespace mips64 { +static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention abi, + ThreadOffset<8> offset) { + std::unique_ptr<Mips64Assembler> assembler(static_cast<Mips64Assembler*>(Assembler::Create(kMips64))); + + switch (abi) { + case kInterpreterAbi: // Thread* is first argument (A0) in interpreter ABI. + __ LoadFromOffset(kLoadDoubleword, T9, A0, offset.Int32Value()); + break; + case kJniAbi: // Load via Thread* held in JNIEnv* in first argument (A0). + __ LoadFromOffset(kLoadDoubleword, T9, A0, JNIEnvExt::SelfOffset().Int32Value()); + __ LoadFromOffset(kLoadDoubleword, T9, T9, offset.Int32Value()); + break; + case kQuickAbi: // Fall-through. + __ LoadFromOffset(kLoadDoubleword, T9, S1, offset.Int32Value()); + } + __ Jr(T9); + __ Nop(); + __ Break(); + + size_t cs = assembler->CodeSize(); + std::unique_ptr<std::vector<uint8_t>> entry_stub(new std::vector<uint8_t>(cs)); + MemoryRegion code(&(*entry_stub)[0], entry_stub->size()); + assembler->FinalizeInstructions(code); + + return entry_stub.release(); +} +} // namespace mips64 + namespace x86 { static const std::vector<uint8_t>* CreateTrampoline(ThreadOffset<4> offset) { std::unique_ptr<X86Assembler> assembler(static_cast<X86Assembler*>(Assembler::Create(kX86))); @@ -160,6 +190,8 @@ const std::vector<uint8_t>* CreateTrampoline64(InstructionSet isa, EntryPointCal switch (isa) { case kArm64: return arm64::CreateTrampoline(abi, offset); + case kMips64: + return mips64::CreateTrampoline(abi, offset); case kX86_64: return x86_64::CreateTrampoline(offset); default: diff --git a/compiler/utils/assembler.cc b/compiler/utils/assembler.cc index 68345129c3..5340dd3a25 100644 --- a/compiler/utils/assembler.cc +++ b/compiler/utils/assembler.cc @@ -23,6 +23,7 @@ #include "arm/assembler_thumb2.h" #include "arm64/assembler_arm64.h" #include "mips/assembler_mips.h" +#include "mips64/assembler_mips64.h" #include "x86/assembler_x86.h" #include "x86_64/assembler_x86_64.h" #include "globals.h" @@ -115,6 +116,8 @@ Assembler* Assembler::Create(InstructionSet instruction_set) { return new arm64::Arm64Assembler(); case kMips: return new mips::MipsAssembler(); + case kMips64: + return new mips64::Mips64Assembler(); case kX86: return new x86::X86Assembler(); case kX86_64: diff --git a/compiler/utils/assembler.h b/compiler/utils/assembler.h index 134dda4b2c..923ecdbd9d 100644 --- a/compiler/utils/assembler.h +++ b/compiler/utils/assembler.h @@ -47,6 +47,9 @@ namespace arm64 { namespace mips { class MipsAssembler; } +namespace mips64 { + class Mips64Assembler; +} namespace x86 { class X86Assembler; } @@ -120,6 +123,7 @@ class Label { friend class arm::Thumb2Assembler; friend class arm64::Arm64Assembler; friend class mips::MipsAssembler; + friend class mips64::Mips64Assembler; friend class x86::X86Assembler; friend class x86_64::X86_64Assembler; diff --git a/compiler/utils/managed_register.h b/compiler/utils/managed_register.h index bfb2829a32..bb62bca3b9 100644 --- a/compiler/utils/managed_register.h +++ b/compiler/utils/managed_register.h @@ -30,6 +30,9 @@ class Arm64ManagedRegister; namespace mips { class MipsManagedRegister; } +namespace mips64 { +class Mips64ManagedRegister; +} namespace x86 { class X86ManagedRegister; @@ -54,6 +57,7 @@ class ManagedRegister { arm::ArmManagedRegister AsArm() const; arm64::Arm64ManagedRegister AsArm64() const; mips::MipsManagedRegister AsMips() const; + mips64::Mips64ManagedRegister AsMips64() const; x86::X86ManagedRegister AsX86() const; x86_64::X86_64ManagedRegister AsX86_64() const; diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc new file mode 100644 index 0000000000..233ae7db3c --- /dev/null +++ b/compiler/utils/mips64/assembler_mips64.cc @@ -0,0 +1,1036 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "assembler_mips64.h" + +#include "base/casts.h" +#include "entrypoints/quick/quick_entrypoints.h" +#include "memory_region.h" +#include "thread.h" + +namespace art { +namespace mips64 { + +void Mips64Assembler::Emit(int32_t value) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + buffer_.Emit<int32_t>(value); +} + +void Mips64Assembler::EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, + int shamt, int funct) { + CHECK_NE(rs, kNoGpuRegister); + CHECK_NE(rt, kNoGpuRegister); + CHECK_NE(rd, kNoGpuRegister); + int32_t encoding = opcode << kOpcodeShift | + static_cast<int32_t>(rs) << kRsShift | + static_cast<int32_t>(rt) << kRtShift | + static_cast<int32_t>(rd) << kRdShift | + shamt << kShamtShift | + funct; + Emit(encoding); +} + +void Mips64Assembler::EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm) { + CHECK_NE(rs, kNoGpuRegister); + CHECK_NE(rt, kNoGpuRegister); + int32_t encoding = opcode << kOpcodeShift | + static_cast<int32_t>(rs) << kRsShift | + static_cast<int32_t>(rt) << kRtShift | + imm; + Emit(encoding); +} + +void Mips64Assembler::EmitJ(int opcode, int address) { + int32_t encoding = opcode << kOpcodeShift | + address; + Emit(encoding); +} + +void Mips64Assembler::EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, +int funct) { + CHECK_NE(ft, kNoFpuRegister); + CHECK_NE(fs, kNoFpuRegister); + CHECK_NE(fd, kNoFpuRegister); + int32_t encoding = opcode << kOpcodeShift | + fmt << kFmtShift | + static_cast<int32_t>(ft) << kFtShift | + static_cast<int32_t>(fs) << kFsShift | + static_cast<int32_t>(fd) << kFdShift | + funct; + Emit(encoding); +} + +void Mips64Assembler::EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm) { + CHECK_NE(rt, kNoFpuRegister); + int32_t encoding = opcode << kOpcodeShift | + fmt << kFmtShift | + static_cast<int32_t>(rt) << kRtShift | + imm; + Emit(encoding); +} + +void Mips64Assembler::EmitBranch(GpuRegister rt, GpuRegister rs, Label* label, bool equal) { + int offset; + if (label->IsBound()) { + offset = label->Position() - buffer_.Size(); + } else { + // Use the offset field of the branch instruction for linking the sites. + offset = label->position_; + label->LinkTo(buffer_.Size()); + } + if (equal) { + Beq(rt, rs, (offset >> 2) & kBranchOffsetMask); + } else { + Bne(rt, rs, (offset >> 2) & kBranchOffsetMask); + } +} + +void Mips64Assembler::EmitJump(Label* label, bool link) { + int offset; + if (label->IsBound()) { + offset = label->Position() - buffer_.Size(); + } else { + // Use the offset field of the jump instruction for linking the sites. + offset = label->position_; + label->LinkTo(buffer_.Size()); + } + if (link) { + Jal((offset >> 2) & kJumpOffsetMask); + } else { + J((offset >> 2) & kJumpOffsetMask); + } +} + +int32_t Mips64Assembler::EncodeBranchOffset(int offset, int32_t inst, bool is_jump) { + CHECK_ALIGNED(offset, 4); + CHECK(IsInt(POPCOUNT(kBranchOffsetMask), offset)) << offset; + + // Properly preserve only the bits supported in the instruction. + offset >>= 2; + if (is_jump) { + offset &= kJumpOffsetMask; + return (inst & ~kJumpOffsetMask) | offset; + } else { + offset &= kBranchOffsetMask; + return (inst & ~kBranchOffsetMask) | offset; + } +} + +int Mips64Assembler::DecodeBranchOffset(int32_t inst, bool is_jump) { + // Sign-extend, then left-shift by 2. + if (is_jump) { + return (((inst & kJumpOffsetMask) << 6) >> 4); + } else { + return (((inst & kBranchOffsetMask) << 16) >> 14); + } +} + +void Mips64Assembler::Bind(Label* label, bool is_jump) { + CHECK(!label->IsBound()); + int bound_pc = buffer_.Size(); + while (label->IsLinked()) { + int32_t position = label->Position(); + int32_t next = buffer_.Load<int32_t>(position); + int32_t offset = is_jump ? bound_pc - position : bound_pc - position - 4; + int32_t encoded = Mips64Assembler::EncodeBranchOffset(offset, next, is_jump); + buffer_.Store<int32_t>(position, encoded); + label->position_ = Mips64Assembler::DecodeBranchOffset(next, is_jump); + } + label->BindTo(bound_pc); +} + +void Mips64Assembler::Add(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x20); +} + +void Mips64Assembler::Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x8, rs, rt, imm16); +} + +void Mips64Assembler::Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x21); +} + +void Mips64Assembler::Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x9, rs, rt, imm16); +} + +void Mips64Assembler::Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x19, rs, rt, imm16); +} + +void Mips64Assembler::Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x22); +} + +void Mips64Assembler::Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x23); +} + +void Mips64Assembler::Mult(GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x18); +} + +void Mips64Assembler::Multu(GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x19); +} + +void Mips64Assembler::Div(GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1a); +} + +void Mips64Assembler::Divu(GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, static_cast<GpuRegister>(0), 0, 0x1b); +} + +void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x24); +} + +void Mips64Assembler::Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0xc, rs, rt, imm16); +} + +void Mips64Assembler::Or(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x25); +} + +void Mips64Assembler::Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0xd, rs, rt, imm16); +} + +void Mips64Assembler::Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x26); +} + +void Mips64Assembler::Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0xe, rs, rt, imm16); +} + +void Mips64Assembler::Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x27); +} + +void Mips64Assembler::Sll(GpuRegister rd, GpuRegister rs, int shamt) { + EmitR(0, rs, static_cast<GpuRegister>(0), rd, shamt, 0x00); +} + +void Mips64Assembler::Srl(GpuRegister rd, GpuRegister rs, int shamt) { + EmitR(0, rs, static_cast<GpuRegister>(0), rd, shamt, 0x02); +} + +void Mips64Assembler::Sra(GpuRegister rd, GpuRegister rs, int shamt) { + EmitR(0, rs, static_cast<GpuRegister>(0), rd, shamt, 0x03); +} + +void Mips64Assembler::Sllv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x04); +} + +void Mips64Assembler::Srlv(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x06); +} + +void Mips64Assembler::Srav(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x07); +} + +void Mips64Assembler::Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x20, rs, rt, imm16); +} + +void Mips64Assembler::Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x21, rs, rt, imm16); +} + +void Mips64Assembler::Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x23, rs, rt, imm16); +} + +void Mips64Assembler::Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x37, rs, rt, imm16); +} + +void Mips64Assembler::Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x24, rs, rt, imm16); +} + +void Mips64Assembler::Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x25, rs, rt, imm16); +} + +void Mips64Assembler::Lui(GpuRegister rt, uint16_t imm16) { + EmitI(0xf, static_cast<GpuRegister>(0), rt, imm16); +} + +void Mips64Assembler::Mfhi(GpuRegister rd) { + EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x10); +} + +void Mips64Assembler::Mflo(GpuRegister rd) { + EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rd, 0, 0x12); +} + +void Mips64Assembler::Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x28, rs, rt, imm16); +} + +void Mips64Assembler::Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x29, rs, rt, imm16); +} + +void Mips64Assembler::Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x2b, rs, rt, imm16); +} + +void Mips64Assembler::Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x3f, rs, rt, imm16); +} + +void Mips64Assembler::Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x2a); +} + +void Mips64Assembler::Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + EmitR(0, rs, rt, rd, 0, 0x2b); +} + +void Mips64Assembler::Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0xa, rs, rt, imm16); +} + +void Mips64Assembler::Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0xb, rs, rt, imm16); +} + +void Mips64Assembler::Beq(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x4, rs, rt, imm16); + Nop(); +} + +void Mips64Assembler::Bne(GpuRegister rt, GpuRegister rs, uint16_t imm16) { + EmitI(0x5, rs, rt, imm16); + Nop(); +} + +void Mips64Assembler::J(uint32_t address) { + EmitJ(0x2, address); + Nop(); +} + +void Mips64Assembler::Jal(uint32_t address) { + EmitJ(0x2, address); + Nop(); +} + +void Mips64Assembler::Jr(GpuRegister rs) { + EmitR(0, rs, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), 0, 0x09); // Jalr zero, rs + Nop(); +} + +void Mips64Assembler::Jalr(GpuRegister rs) { + EmitR(0, rs, static_cast<GpuRegister>(0), RA, 0, 0x09); + Nop(); +} + +void Mips64Assembler::AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x0); +} + +void Mips64Assembler::SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x1); +} + +void Mips64Assembler::MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x2); +} + +void Mips64Assembler::DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x10, ft, fs, fd, 0x3); +} + +void Mips64Assembler::AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), + static_cast<FpuRegister>(fd), 0x0); +} + +void Mips64Assembler::SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), + static_cast<FpuRegister>(fd), 0x1); +} + +void Mips64Assembler::MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), + static_cast<FpuRegister>(fd), 0x2); +} + +void Mips64Assembler::DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft) { + EmitFR(0x11, 0x11, static_cast<FpuRegister>(ft), static_cast<FpuRegister>(fs), + static_cast<FpuRegister>(fd), 0x3); +} + +void Mips64Assembler::MovS(FpuRegister fd, FpuRegister fs) { + EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x6); +} + +void Mips64Assembler::MovD(FpuRegister fd, FpuRegister fs) { + EmitFR(0x11, 0x11, static_cast<FpuRegister>(0), static_cast<FpuRegister>(fs), + static_cast<FpuRegister>(fd), 0x6); +} + +void Mips64Assembler::Mfc1(GpuRegister rt, FpuRegister fs) { + EmitFR(0x11, 0x00, static_cast<FpuRegister>(rt), fs, static_cast<FpuRegister>(0), 0x0); +} + +void Mips64Assembler::Mtc1(FpuRegister ft, GpuRegister rs) { + EmitFR(0x11, 0x04, ft, static_cast<FpuRegister>(rs), static_cast<FpuRegister>(0), 0x0); +} + +void Mips64Assembler::Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { + EmitI(0x31, rs, static_cast<GpuRegister>(ft), imm16); +} + +void Mips64Assembler::Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { + EmitI(0x35, rs, static_cast<GpuRegister>(ft), imm16); +} + +void Mips64Assembler::Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { + EmitI(0x39, rs, static_cast<GpuRegister>(ft), imm16); +} + +void Mips64Assembler::Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16) { + EmitI(0x3d, rs, static_cast<GpuRegister>(ft), imm16); +} + +void Mips64Assembler::Break() { + EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), + static_cast<GpuRegister>(0), 0, 0xD); +} + +void Mips64Assembler::Nop() { + EmitR(0x0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), + static_cast<GpuRegister>(0), 0, 0x0); +} + +void Mips64Assembler::Move(GpuRegister rt, GpuRegister rs) { + EmitI(0x19, rs, rt, 0); // Daddiu +} + +void Mips64Assembler::Clear(GpuRegister rt) { + EmitR(0, static_cast<GpuRegister>(0), static_cast<GpuRegister>(0), rt, 0, 0x20); +} + +void Mips64Assembler::Not(GpuRegister rt, GpuRegister rs) { + EmitR(0, static_cast<GpuRegister>(0), rs, rt, 0, 0x27); +} + +void Mips64Assembler::Mul(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + Mult(rs, rt); + Mflo(rd); +} + +void Mips64Assembler::Div(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + Div(rs, rt); + Mflo(rd); +} + +void Mips64Assembler::Rem(GpuRegister rd, GpuRegister rs, GpuRegister rt) { + Div(rs, rt); + Mfhi(rd); +} + +void Mips64Assembler::AddConstant64(GpuRegister rt, GpuRegister rs, int32_t value) { + CHECK((value >= -32768) && (value <= 32766)); + Daddiu(rt, rs, value); +} + +void Mips64Assembler::LoadImmediate64(GpuRegister rt, int32_t value) { + CHECK((value >= -32768) && (value <= 32766)); + Daddiu(rt, ZERO, value); +} + +void Mips64Assembler::LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, + int32_t offset) { + switch (type) { + case kLoadSignedByte: + Lb(reg, base, offset); + break; + case kLoadUnsignedByte: + Lbu(reg, base, offset); + break; + case kLoadSignedHalfword: + Lh(reg, base, offset); + break; + case kLoadUnsignedHalfword: + Lhu(reg, base, offset); + break; + case kLoadWord: + Lw(reg, base, offset); + break; + case kLoadDoubleword: + // TODO: alignment issues ??? + Ld(reg, base, offset); + break; + default: + LOG(FATAL) << "UNREACHABLE"; + } +} + +void Mips64Assembler::LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, + int32_t offset) { + CHECK((offset >= -32768) && (offset <= 32766)); + switch (type) { + case kLoadWord: + Lwc1(reg, base, offset); + break; + case kLoadDoubleword: + // TODO: alignment issues ??? + Ldc1(reg, base, offset); + break; + default: + LOG(FATAL) << "UNREACHABLE"; + } +} + +void Mips64Assembler::EmitLoad(ManagedRegister m_dst, GpuRegister src_register, int32_t src_offset, + size_t size) { + Mips64ManagedRegister dst = m_dst.AsMips64(); + if (dst.IsNoRegister()) { + CHECK_EQ(0u, size) << dst; + } else if (dst.IsGpuRegister()) { + if (size == 4) { + CHECK_EQ(4u, size) << dst; + LoadFromOffset(kLoadWord, dst.AsGpuRegister(), src_register, src_offset); + } else if (size == 8) { + CHECK_EQ(8u, size) << dst; + LoadFromOffset(kLoadDoubleword, dst.AsGpuRegister(), src_register, src_offset); + } else { + UNIMPLEMENTED(FATAL) << "We only support Load() of size 4 and 8"; + } + } else if (dst.IsFpuRegister()) { + if (size == 4) { + CHECK_EQ(4u, size) << dst; + LoadFpuFromOffset(kLoadWord, dst.AsFpuRegister(), src_register, src_offset); + } else if (size == 8) { + CHECK_EQ(8u, size) << dst; + LoadFpuFromOffset(kLoadDoubleword, dst.AsFpuRegister(), src_register, src_offset); + } else { + UNIMPLEMENTED(FATAL) << "We only support Load() of size 4 and 8"; + } + } +} + +void Mips64Assembler::StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, + int32_t offset) { + switch (type) { + case kStoreByte: + Sb(reg, base, offset); + break; + case kStoreHalfword: + Sh(reg, base, offset); + break; + case kStoreWord: + Sw(reg, base, offset); + break; + case kStoreDoubleword: + // TODO: alignment issues ??? + Sd(reg, base, offset); + break; + default: + LOG(FATAL) << "UNREACHABLE"; + } +} + +void Mips64Assembler::StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, + int32_t offset) { + switch (type) { + case kStoreWord: + Swc1(reg, base, offset); + break; + case kStoreDoubleword: + Sdc1(reg, base, offset); + break; + default: + LOG(FATAL) << "UNREACHABLE"; + } +} + +constexpr size_t kFramePointerSize = 8; + +void Mips64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, + const std::vector<ManagedRegister>& callee_save_regs, + const ManagedRegisterEntrySpills& entry_spills) { + CHECK_ALIGNED(frame_size, kStackAlignment); + + // Increase frame to required size. + IncreaseFrameSize(frame_size); + + // Push callee saves and return address + int stack_offset = frame_size - kFramePointerSize; + StoreToOffset(kStoreDoubleword, RA, SP, stack_offset); + for (int i = callee_save_regs.size() - 1; i >= 0; --i) { + stack_offset -= kFramePointerSize; + GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister(); + StoreToOffset(kStoreDoubleword, reg, SP, stack_offset); + } + + // Write out Method*. + StoreToOffset(kStoreWord, method_reg.AsMips64().AsGpuRegister(), SP, 0); + + // Write out entry spills. + int32_t offset = frame_size + sizeof(StackReference<mirror::ArtMethod>); + for (size_t i = 0; i < entry_spills.size(); ++i) { + Mips64ManagedRegister reg = entry_spills.at(i).AsMips64(); + ManagedRegisterSpill spill = entry_spills.at(i); + int32_t size = spill.getSize(); + if (reg.IsNoRegister()) { + // only increment stack offset. + offset += size; + } else if (reg.IsFpuRegister()) { + StoreFpuToOffset((size == 4) ? kStoreWord : kStoreDoubleword, reg.AsFpuRegister(), SP, offset); + offset += size; + } else if (reg.IsGpuRegister()) { + StoreToOffset((size == 4) ? kStoreWord : kStoreDoubleword, reg.AsGpuRegister(), SP, offset); + offset += size; + } + } +} + +void Mips64Assembler::RemoveFrame(size_t frame_size, + const std::vector<ManagedRegister>& callee_save_regs) { + CHECK_ALIGNED(frame_size, kStackAlignment); + + // Pop callee saves and return address + int stack_offset = frame_size - (callee_save_regs.size() * kFramePointerSize) - kFramePointerSize; + for (size_t i = 0; i < callee_save_regs.size(); ++i) { + GpuRegister reg = callee_save_regs.at(i).AsMips64().AsGpuRegister(); + LoadFromOffset(kLoadDoubleword, reg, SP, stack_offset); + stack_offset += kFramePointerSize; + } + LoadFromOffset(kLoadDoubleword, RA, SP, stack_offset); + + // Decrease frame to required size. + DecreaseFrameSize(frame_size); + + // Then jump to the return address. + Jr(RA); +} + +void Mips64Assembler::IncreaseFrameSize(size_t adjust) { + CHECK_ALIGNED(adjust, kStackAlignment); + AddConstant64(SP, SP, -adjust); +} + +void Mips64Assembler::DecreaseFrameSize(size_t adjust) { + CHECK_ALIGNED(adjust, kStackAlignment); + AddConstant64(SP, SP, adjust); +} + +void Mips64Assembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) { + Mips64ManagedRegister src = msrc.AsMips64(); + if (src.IsNoRegister()) { + CHECK_EQ(0u, size); + } else if (src.IsGpuRegister()) { + CHECK(size == 4 || size == 8) << size; + if (size == 8) { + StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); + } else if (size == 4) { + StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Store() of size 4 and 8"; + } + } else if (src.IsFpuRegister()) { + CHECK(size == 4 || size == 8) << size; + if (size == 8) { + StoreFpuToOffset(kStoreDoubleword, src.AsFpuRegister(), SP, dest.Int32Value()); + } else if (size == 4) { + StoreFpuToOffset(kStoreWord, src.AsFpuRegister(), SP, dest.Int32Value()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Store() of size 4 and 8"; + } + } +} + +void Mips64Assembler::StoreRef(FrameOffset dest, ManagedRegister msrc) { + Mips64ManagedRegister src = msrc.AsMips64(); + CHECK(src.IsGpuRegister()); + StoreToOffset(kStoreWord, src.AsGpuRegister(), SP, dest.Int32Value()); +} + +void Mips64Assembler::StoreRawPtr(FrameOffset dest, ManagedRegister msrc) { + Mips64ManagedRegister src = msrc.AsMips64(); + CHECK(src.IsGpuRegister()); + StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); +} + +void Mips64Assembler::StoreImmediateToFrame(FrameOffset dest, uint32_t imm, + ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + LoadImmediate64(scratch.AsGpuRegister(), imm); + StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); +} + +void Mips64Assembler::StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, + ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + LoadImmediate64(scratch.AsGpuRegister(), imm); + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, dest.Int32Value()); +} + +void Mips64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, + FrameOffset fr_offs, + ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + AddConstant64(scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); +} + +void Mips64Assembler::StoreStackPointerToThread64(ThreadOffset<8> thr_offs) { + StoreToOffset(kStoreDoubleword, SP, S1, thr_offs.Int32Value()); +} + +void Mips64Assembler::StoreSpanning(FrameOffset dest, ManagedRegister msrc, + FrameOffset in_off, ManagedRegister mscratch) { + Mips64ManagedRegister src = msrc.AsMips64(); + Mips64ManagedRegister scratch = mscratch.AsMips64(); + StoreToOffset(kStoreDoubleword, src.AsGpuRegister(), SP, dest.Int32Value()); + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, in_off.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value() + 8); +} + +void Mips64Assembler::Load(ManagedRegister mdest, FrameOffset src, size_t size) { + return EmitLoad(mdest, SP, src.Int32Value(), size); +} + +void Mips64Assembler::LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) { + return EmitLoad(mdest, S1, src.Int32Value(), size); +} + +void Mips64Assembler::LoadRef(ManagedRegister mdest, FrameOffset src) { + Mips64ManagedRegister dest = mdest.AsMips64(); + CHECK(dest.IsGpuRegister()); + LoadFromOffset(kLoadWord, dest.AsGpuRegister(), SP, src.Int32Value()); +} + +void Mips64Assembler::LoadRef(ManagedRegister mdest, ManagedRegister base, + MemberOffset offs) { + Mips64ManagedRegister dest = mdest.AsMips64(); + CHECK(dest.IsGpuRegister() && dest.IsGpuRegister()); + LoadFromOffset(kLoadWord, dest.AsGpuRegister(), + base.AsMips64().AsGpuRegister(), offs.Int32Value()); + if (kPoisonHeapReferences) { + Subu(dest.AsGpuRegister(), ZERO, dest.AsGpuRegister()); + } +} + +void Mips64Assembler::LoadRawPtr(ManagedRegister mdest, ManagedRegister base, + Offset offs) { + Mips64ManagedRegister dest = mdest.AsMips64(); + CHECK(dest.IsGpuRegister() && dest.IsGpuRegister()) << dest; + LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), + base.AsMips64().AsGpuRegister(), offs.Int32Value()); +} + +void Mips64Assembler::LoadRawPtrFromThread64(ManagedRegister mdest, + ThreadOffset<8> offs) { + Mips64ManagedRegister dest = mdest.AsMips64(); + CHECK(dest.IsGpuRegister()); + LoadFromOffset(kLoadDoubleword, dest.AsGpuRegister(), S1, offs.Int32Value()); +} + +void Mips64Assembler::SignExtend(ManagedRegister /*mreg*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no sign extension necessary for mips"; +} + +void Mips64Assembler::ZeroExtend(ManagedRegister /*mreg*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no zero extension necessary for mips"; +} + +void Mips64Assembler::Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) { + Mips64ManagedRegister dest = mdest.AsMips64(); + Mips64ManagedRegister src = msrc.AsMips64(); + if (!dest.Equals(src)) { + if (dest.IsGpuRegister()) { + CHECK(src.IsGpuRegister()) << src; + Move(dest.AsGpuRegister(), src.AsGpuRegister()); + } else if (dest.IsFpuRegister()) { + CHECK(src.IsFpuRegister()) << src; + if (size == 4) { + MovS(dest.AsFpuRegister(), src.AsFpuRegister()); + } else if (size == 8) { + MovD(dest.AsFpuRegister(), src.AsFpuRegister()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; + } + } + } +} + +void Mips64Assembler::CopyRef(FrameOffset dest, FrameOffset src, + ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); +} + +void Mips64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs, + ThreadOffset<8> thr_offs, + ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), S1, thr_offs.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, fr_offs.Int32Value()); +} + +void Mips64Assembler::CopyRawPtrToThread64(ThreadOffset<8> thr_offs, + FrameOffset fr_offs, + ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), + SP, fr_offs.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), + S1, thr_offs.Int32Value()); +} + +void Mips64Assembler::Copy(FrameOffset dest, FrameOffset src, + ManagedRegister mscratch, size_t size) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + CHECK(size == 4 || size == 8) << size; + if (size == 4) { + LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch.AsGpuRegister(), SP, dest.Int32Value()); + } else if (size == 8) { + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), SP, src.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, dest.Int32Value()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; + } +} + +void Mips64Assembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, + ManagedRegister mscratch, size_t size) { + GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); + CHECK(size == 4 || size == 8) << size; + if (size == 4) { + LoadFromOffset(kLoadWord, scratch, src_base.AsMips64().AsGpuRegister(), + src_offset.Int32Value()); + StoreToOffset(kStoreWord, scratch, SP, dest.Int32Value()); + } else if (size == 8) { + LoadFromOffset(kLoadDoubleword, scratch, src_base.AsMips64().AsGpuRegister(), + src_offset.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch, SP, dest.Int32Value()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; + } +} + +void Mips64Assembler::Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, + ManagedRegister mscratch, size_t size) { + GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); + CHECK(size == 4 || size == 8) << size; + if (size == 4) { + LoadFromOffset(kLoadWord, scratch, SP, src.Int32Value()); + StoreToOffset(kStoreWord, scratch, dest_base.AsMips64().AsGpuRegister(), + dest_offset.Int32Value()); + } else if (size == 8) { + LoadFromOffset(kLoadDoubleword, scratch, SP, src.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch, dest_base.AsMips64().AsGpuRegister(), + dest_offset.Int32Value()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; + } +} + +void Mips64Assembler::Copy(FrameOffset /*dest*/, FrameOffset /*src_base*/, Offset /*src_offset*/, + ManagedRegister /*mscratch*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no mips64 implementation"; +} + +void Mips64Assembler::Copy(ManagedRegister dest, Offset dest_offset, + ManagedRegister src, Offset src_offset, + ManagedRegister mscratch, size_t size) { + GpuRegister scratch = mscratch.AsMips64().AsGpuRegister(); + CHECK(size == 4 || size == 8) << size; + if (size == 4) { + LoadFromOffset(kLoadWord, scratch, src.AsMips64().AsGpuRegister(), src_offset.Int32Value()); + StoreToOffset(kStoreWord, scratch, dest.AsMips64().AsGpuRegister(), dest_offset.Int32Value()); + } else if (size == 8) { + LoadFromOffset(kLoadDoubleword, scratch, src.AsMips64().AsGpuRegister(), + src_offset.Int32Value()); + StoreToOffset(kStoreDoubleword, scratch, dest.AsMips64().AsGpuRegister(), + dest_offset.Int32Value()); + } else { + UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; + } +} + +void Mips64Assembler::Copy(FrameOffset /*dest*/, Offset /*dest_offset*/, FrameOffset /*src*/, Offset +/*src_offset*/, + ManagedRegister /*mscratch*/, size_t /*size*/) { + UNIMPLEMENTED(FATAL) << "no mips64 implementation"; +} + +void Mips64Assembler::MemoryBarrier(ManagedRegister) { + UNIMPLEMENTED(FATAL) << "no mips64 implementation"; +} + +void Mips64Assembler::CreateHandleScopeEntry(ManagedRegister mout_reg, + FrameOffset handle_scope_offset, + ManagedRegister min_reg, bool null_allowed) { + Mips64ManagedRegister out_reg = mout_reg.AsMips64(); + Mips64ManagedRegister in_reg = min_reg.AsMips64(); + CHECK(in_reg.IsNoRegister() || in_reg.IsGpuRegister()) << in_reg; + CHECK(out_reg.IsGpuRegister()) << out_reg; + if (null_allowed) { + Label null_arg; + // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is + // the address in the handle scope holding the reference. + // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) + if (in_reg.IsNoRegister()) { + LoadFromOffset(kLoadWord, out_reg.AsGpuRegister(), + SP, handle_scope_offset.Int32Value()); + in_reg = out_reg; + } + if (!out_reg.Equals(in_reg)) { + LoadImmediate64(out_reg.AsGpuRegister(), 0); + } + EmitBranch(in_reg.AsGpuRegister(), ZERO, &null_arg, true); + AddConstant64(out_reg.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); + Bind(&null_arg, false); + } else { + AddConstant64(out_reg.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); + } +} + +void Mips64Assembler::CreateHandleScopeEntry(FrameOffset out_off, + FrameOffset handle_scope_offset, + ManagedRegister mscratch, + bool null_allowed) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + if (null_allowed) { + Label null_arg; + LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), SP, + handle_scope_offset.Int32Value()); + // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is + // the address in the handle scope holding the reference. + // e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset) + EmitBranch(scratch.AsGpuRegister(), ZERO, &null_arg, true); + AddConstant64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); + Bind(&null_arg, false); + } else { + AddConstant64(scratch.AsGpuRegister(), SP, handle_scope_offset.Int32Value()); + } + StoreToOffset(kStoreDoubleword, scratch.AsGpuRegister(), SP, out_off.Int32Value()); +} + +// Given a handle scope entry, load the associated reference. +void Mips64Assembler::LoadReferenceFromHandleScope(ManagedRegister mout_reg, + ManagedRegister min_reg) { + Mips64ManagedRegister out_reg = mout_reg.AsMips64(); + Mips64ManagedRegister in_reg = min_reg.AsMips64(); + CHECK(out_reg.IsGpuRegister()) << out_reg; + CHECK(in_reg.IsGpuRegister()) << in_reg; + Label null_arg; + if (!out_reg.Equals(in_reg)) { + LoadImmediate64(out_reg.AsGpuRegister(), 0); + } + EmitBranch(in_reg.AsGpuRegister(), ZERO, &null_arg, true); + LoadFromOffset(kLoadDoubleword, out_reg.AsGpuRegister(), + in_reg.AsGpuRegister(), 0); + Bind(&null_arg, false); +} + +void Mips64Assembler::VerifyObject(ManagedRegister /*src*/, bool /*could_be_null*/) { + // TODO: not validating references +} + +void Mips64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) { + // TODO: not validating references +} + +void Mips64Assembler::Call(ManagedRegister mbase, Offset offset, ManagedRegister mscratch) { + Mips64ManagedRegister base = mbase.AsMips64(); + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(base.IsGpuRegister()) << base; + CHECK(scratch.IsGpuRegister()) << scratch; + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), + base.AsGpuRegister(), offset.Int32Value()); + Jalr(scratch.AsGpuRegister()); + // TODO: place reference map on call +} + +void Mips64Assembler::Call(FrameOffset base, Offset offset, ManagedRegister mscratch) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + CHECK(scratch.IsGpuRegister()) << scratch; + // Call *(*(SP + base) + offset) + LoadFromOffset(kLoadWord, scratch.AsGpuRegister(), + SP, base.Int32Value()); + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), + scratch.AsGpuRegister(), offset.Int32Value()); + Jalr(scratch.AsGpuRegister()); + // TODO: place reference map on call +} + +void Mips64Assembler::CallFromThread64(ThreadOffset<8> /*offset*/, ManagedRegister /*mscratch*/) { + UNIMPLEMENTED(FATAL) << "no mips64 implementation"; +} + +void Mips64Assembler::GetCurrentThread(ManagedRegister tr) { + Move(tr.AsMips64().AsGpuRegister(), S1); +} + +void Mips64Assembler::GetCurrentThread(FrameOffset offset, + ManagedRegister /*mscratch*/) { + StoreToOffset(kStoreDoubleword, S1, SP, offset.Int32Value()); +} + +void Mips64Assembler::ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) { + Mips64ManagedRegister scratch = mscratch.AsMips64(); + Mips64ExceptionSlowPath* slow = new Mips64ExceptionSlowPath(scratch, stack_adjust); + buffer_.EnqueueSlowPath(slow); + LoadFromOffset(kLoadDoubleword, scratch.AsGpuRegister(), + S1, Thread::ExceptionOffset<8>().Int32Value()); + EmitBranch(scratch.AsGpuRegister(), ZERO, slow->Entry(), false); +} + +void Mips64ExceptionSlowPath::Emit(Assembler* sasm) { + Mips64Assembler* sp_asm = down_cast<Mips64Assembler*>(sasm); +#define __ sp_asm-> + __ Bind(&entry_, false); + if (stack_adjust_ != 0) { // Fix up the frame. + __ DecreaseFrameSize(stack_adjust_); + } + // Pass exception object as argument + // Don't care about preserving A0 as this call won't return + __ Move(A0, scratch_.AsGpuRegister()); + // Set up call to Thread::Current()->pDeliverException + __ LoadFromOffset(kLoadDoubleword, T9, S1, + QUICK_ENTRYPOINT_OFFSET(4, pDeliverException).Int32Value()); + __ Jr(T9); + // Call never returns + __ Break(); +#undef __ +} + +} // namespace mips64 +} // namespace art diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h new file mode 100644 index 0000000000..36e74d7cb2 --- /dev/null +++ b/compiler/utils/mips64/assembler_mips64.h @@ -0,0 +1,294 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_COMPILER_UTILS_MIPS64_ASSEMBLER_MIPS64_H_ +#define ART_COMPILER_UTILS_MIPS64_ASSEMBLER_MIPS64_H_ + +#include <vector> + +#include "base/macros.h" +#include "constants_mips64.h" +#include "globals.h" +#include "managed_register_mips64.h" +#include "utils/assembler.h" +#include "offsets.h" +#include "utils.h" + +namespace art { +namespace mips64 { + +enum LoadOperandType { + kLoadSignedByte, + kLoadUnsignedByte, + kLoadSignedHalfword, + kLoadUnsignedHalfword, + kLoadWord, + kLoadDoubleword +}; + +enum StoreOperandType { + kStoreByte, + kStoreHalfword, + kStoreWord, + kStoreDoubleword +}; + +class Mips64Assembler FINAL : public Assembler { + public: + Mips64Assembler() {} + virtual ~Mips64Assembler() {} + + // Emit Machine Instructions. + void Add(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Addi(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Addu(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Addiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Daddiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Sub(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Subu(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Mult(GpuRegister rs, GpuRegister rt); + void Multu(GpuRegister rs, GpuRegister rt); + void Div(GpuRegister rs, GpuRegister rt); + void Divu(GpuRegister rs, GpuRegister rt); + + void And(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Andi(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Or(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Ori(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Xor(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Xori(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Nor(GpuRegister rd, GpuRegister rs, GpuRegister rt); + + void Sll(GpuRegister rd, GpuRegister rs, int shamt); + void Srl(GpuRegister rd, GpuRegister rs, int shamt); + void Sra(GpuRegister rd, GpuRegister rs, int shamt); + void Sllv(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Srlv(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Srav(GpuRegister rd, GpuRegister rs, GpuRegister rt); + + void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Lh(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Lw(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Ld(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Lbu(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Lhu(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Lui(GpuRegister rt, uint16_t imm16); + void Mfhi(GpuRegister rd); + void Mflo(GpuRegister rd); + + void Sb(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Sh(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Sw(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Sd(GpuRegister rt, GpuRegister rs, uint16_t imm16); + + void Slt(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Sltu(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Slti(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Sltiu(GpuRegister rt, GpuRegister rs, uint16_t imm16); + + void Beq(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void Bne(GpuRegister rt, GpuRegister rs, uint16_t imm16); + void J(uint32_t address); + void Jal(uint32_t address); + void Jr(GpuRegister rs); + void Jalr(GpuRegister rs); + + void AddS(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void SubS(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void MulS(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void DivS(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void AddD(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void SubD(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void MulD(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void DivD(FpuRegister fd, FpuRegister fs, FpuRegister ft); + void MovS(FpuRegister fd, FpuRegister fs); + void MovD(FpuRegister fd, FpuRegister fs); + + void Mfc1(GpuRegister rt, FpuRegister fs); + void Mtc1(FpuRegister ft, GpuRegister rs); + void Lwc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); + void Ldc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); + void Swc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); + void Sdc1(FpuRegister ft, GpuRegister rs, uint16_t imm16); + + void Break(); + void Nop(); + void Move(GpuRegister rt, GpuRegister rs); + void Clear(GpuRegister rt); + void Not(GpuRegister rt, GpuRegister rs); + void Mul(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Div(GpuRegister rd, GpuRegister rs, GpuRegister rt); + void Rem(GpuRegister rd, GpuRegister rs, GpuRegister rt); + + void AddConstant64(GpuRegister rt, GpuRegister rs, int32_t value); + void LoadImmediate64(GpuRegister rt, int32_t value); + + void EmitLoad(ManagedRegister m_dst, GpuRegister src_register, int32_t src_offset, size_t size); + void LoadFromOffset(LoadOperandType type, GpuRegister reg, GpuRegister base, int32_t offset); + void LoadFpuFromOffset(LoadOperandType type, FpuRegister reg, GpuRegister base, int32_t offset); + void StoreToOffset(StoreOperandType type, GpuRegister reg, GpuRegister base, int32_t offset); + void StoreFpuToOffset(StoreOperandType type, FpuRegister reg, GpuRegister base, int32_t offset); + + // Emit data (e.g. encoded instruction or immediate) to the instruction stream. + void Emit(int32_t value); + void EmitBranch(GpuRegister rt, GpuRegister rs, Label* label, bool equal); + void EmitJump(Label* label, bool link); + void Bind(Label* label, bool is_jump); + + // + // Overridden common assembler high-level functionality + // + + // Emit code that will create an activation on the stack + void BuildFrame(size_t frame_size, ManagedRegister method_reg, + const std::vector<ManagedRegister>& callee_save_regs, + const ManagedRegisterEntrySpills& entry_spills) OVERRIDE; + + // Emit code that will remove an activation from the stack + void RemoveFrame(size_t frame_size, + const std::vector<ManagedRegister>& callee_save_regs) OVERRIDE; + + void IncreaseFrameSize(size_t adjust) OVERRIDE; + void DecreaseFrameSize(size_t adjust) OVERRIDE; + + // Store routines + void Store(FrameOffset offs, ManagedRegister msrc, size_t size) OVERRIDE; + void StoreRef(FrameOffset dest, ManagedRegister msrc) OVERRIDE; + void StoreRawPtr(FrameOffset dest, ManagedRegister msrc) OVERRIDE; + + void StoreImmediateToFrame(FrameOffset dest, uint32_t imm, ManagedRegister mscratch) OVERRIDE; + + void StoreImmediateToThread64(ThreadOffset<8> dest, uint32_t imm, + ManagedRegister mscratch) OVERRIDE; + + void StoreStackOffsetToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, + ManagedRegister mscratch) OVERRIDE; + + void StoreStackPointerToThread64(ThreadOffset<8> thr_offs) OVERRIDE; + + void StoreSpanning(FrameOffset dest, ManagedRegister msrc, FrameOffset in_off, + ManagedRegister mscratch) OVERRIDE; + + // Load routines + void Load(ManagedRegister mdest, FrameOffset src, size_t size) OVERRIDE; + + void LoadFromThread64(ManagedRegister mdest, ThreadOffset<8> src, size_t size) OVERRIDE; + + void LoadRef(ManagedRegister dest, FrameOffset src) OVERRIDE; + + void LoadRef(ManagedRegister mdest, ManagedRegister base, MemberOffset offs) OVERRIDE; + + void LoadRawPtr(ManagedRegister mdest, ManagedRegister base, Offset offs) OVERRIDE; + + void LoadRawPtrFromThread64(ManagedRegister mdest, ThreadOffset<8> offs) OVERRIDE; + + // Copying routines + void Move(ManagedRegister mdest, ManagedRegister msrc, size_t size) OVERRIDE; + + void CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> thr_offs, + ManagedRegister mscratch) OVERRIDE; + + void CopyRawPtrToThread64(ThreadOffset<8> thr_offs, FrameOffset fr_offs, + ManagedRegister mscratch) OVERRIDE; + + void CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister mscratch) OVERRIDE; + + void Copy(FrameOffset dest, FrameOffset src, ManagedRegister mscratch, size_t size) OVERRIDE; + + void Copy(FrameOffset dest, ManagedRegister src_base, Offset src_offset, ManagedRegister mscratch, + size_t size) OVERRIDE; + + void Copy(ManagedRegister dest_base, Offset dest_offset, FrameOffset src, + ManagedRegister mscratch, size_t size) OVERRIDE; + + void Copy(FrameOffset dest, FrameOffset src_base, Offset src_offset, ManagedRegister mscratch, + size_t size) OVERRIDE; + + void Copy(ManagedRegister dest, Offset dest_offset, ManagedRegister src, Offset src_offset, + ManagedRegister mscratch, size_t size) OVERRIDE; + + void Copy(FrameOffset dest, Offset dest_offset, FrameOffset src, Offset src_offset, + ManagedRegister mscratch, size_t size) OVERRIDE; + + void MemoryBarrier(ManagedRegister) OVERRIDE; + + // Sign extension + void SignExtend(ManagedRegister mreg, size_t size) OVERRIDE; + + // Zero extension + void ZeroExtend(ManagedRegister mreg, size_t size) OVERRIDE; + + // Exploit fast access in managed code to Thread::Current() + void GetCurrentThread(ManagedRegister tr) OVERRIDE; + void GetCurrentThread(FrameOffset dest_offset, ManagedRegister mscratch) OVERRIDE; + + // Set up out_reg to hold a Object** into the handle scope, or to be NULL if the + // value is null and null_allowed. in_reg holds a possibly stale reference + // that can be used to avoid loading the handle scope entry to see if the value is + // NULL. + void CreateHandleScopeEntry(ManagedRegister out_reg, FrameOffset handlescope_offset, + ManagedRegister in_reg, bool null_allowed) OVERRIDE; + + // Set up out_off to hold a Object** into the handle scope, or to be NULL if the + // value is null and null_allowed. + void CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handlescope_offset, ManagedRegister + mscratch, bool null_allowed) OVERRIDE; + + // src holds a handle scope entry (Object**) load this into dst + void LoadReferenceFromHandleScope(ManagedRegister dst, ManagedRegister src) OVERRIDE; + + // Heap::VerifyObject on src. In some cases (such as a reference to this) we + // know that src may not be null. + void VerifyObject(ManagedRegister src, bool could_be_null) OVERRIDE; + void VerifyObject(FrameOffset src, bool could_be_null) OVERRIDE; + + // Call to address held at [base+offset] + void Call(ManagedRegister base, Offset offset, ManagedRegister mscratch) OVERRIDE; + void Call(FrameOffset base, Offset offset, ManagedRegister mscratch) OVERRIDE; + void CallFromThread64(ThreadOffset<8> offset, ManagedRegister mscratch) OVERRIDE; + + // Generate code to check if Thread::Current()->exception_ is non-null + // and branch to a ExceptionSlowPath if it is. + void ExceptionPoll(ManagedRegister mscratch, size_t stack_adjust) OVERRIDE; + + private: + void EmitR(int opcode, GpuRegister rs, GpuRegister rt, GpuRegister rd, int shamt, int funct); + void EmitI(int opcode, GpuRegister rs, GpuRegister rt, uint16_t imm); + void EmitJ(int opcode, int address); + void EmitFR(int opcode, int fmt, FpuRegister ft, FpuRegister fs, FpuRegister fd, int funct); + void EmitFI(int opcode, int fmt, FpuRegister rt, uint16_t imm); + + int32_t EncodeBranchOffset(int offset, int32_t inst, bool is_jump); + int DecodeBranchOffset(int32_t inst, bool is_jump); + + DISALLOW_COPY_AND_ASSIGN(Mips64Assembler); +}; + +// Slowpath entered when Thread::Current()->_exception is non-null +class Mips64ExceptionSlowPath FINAL : public SlowPath { + public: + explicit Mips64ExceptionSlowPath(Mips64ManagedRegister scratch, size_t stack_adjust) + : scratch_(scratch), stack_adjust_(stack_adjust) {} + virtual void Emit(Assembler *sp_asm) OVERRIDE; + private: + const Mips64ManagedRegister scratch_; + const size_t stack_adjust_; +}; + +} // namespace mips64 +} // namespace art + +#endif // ART_COMPILER_UTILS_MIPS64_ASSEMBLER_MIPS64_H_ diff --git a/compiler/utils/mips64/constants_mips64.h b/compiler/utils/mips64/constants_mips64.h new file mode 100644 index 0000000000..8b7697cac3 --- /dev/null +++ b/compiler/utils/mips64/constants_mips64.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_COMPILER_UTILS_MIPS64_CONSTANTS_MIPS64_H_ +#define ART_COMPILER_UTILS_MIPS64_CONSTANTS_MIPS64_H_ + +#include <iosfwd> + +#include "arch/mips64/registers_mips64.h" +#include "base/logging.h" +#include "base/macros.h" +#include "globals.h" + +namespace art { +namespace mips64 { + +// Constants used for the decoding or encoding of the individual fields of instructions. +enum InstructionFields { + kOpcodeShift = 26, + kOpcodeBits = 6, + kRsShift = 21, + kRsBits = 5, + kRtShift = 16, + kRtBits = 5, + kRdShift = 11, + kRdBits = 5, + kShamtShift = 6, + kShamtBits = 5, + kFunctShift = 0, + kFunctBits = 6, + + kFmtShift = 21, + kFmtBits = 5, + kFtShift = 16, + kFtBits = 5, + kFsShift = 11, + kFsBits = 5, + kFdShift = 6, + kFdBits = 5, + + kBranchOffsetMask = 0x0000ffff, + kJumpOffsetMask = 0x03ffffff, +}; + +enum ScaleFactor { + TIMES_1 = 0, + TIMES_2 = 1, + TIMES_4 = 2, + TIMES_8 = 3 +}; + +class Instr { + public: + static const uint32_t kBreakPointInstruction = 0x0000000D; + + bool IsBreakPoint() { + return ((*reinterpret_cast<const uint32_t*>(this)) & 0xFC0000CF) == kBreakPointInstruction; + } + + // Instructions are read out of a code stream. The only way to get a + // reference to an instruction is to convert a pointer. There is no way + // to allocate or create instances of class Instr. + // Use the At(pc) function to create references to Instr. + static Instr* At(uintptr_t pc) { return reinterpret_cast<Instr*>(pc); } + + private: + DISALLOW_IMPLICIT_CONSTRUCTORS(Instr); +}; + +} // namespace mips64 +} // namespace art + +#endif // ART_COMPILER_UTILS_MIPS64_CONSTANTS_MIPS64_H_ diff --git a/compiler/utils/mips64/managed_register_mips64.cc b/compiler/utils/mips64/managed_register_mips64.cc new file mode 100644 index 0000000000..dea396e4a7 --- /dev/null +++ b/compiler/utils/mips64/managed_register_mips64.cc @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "managed_register_mips64.h" + +#include "globals.h" + +namespace art { +namespace mips64 { + +bool Mips64ManagedRegister::Overlaps(const Mips64ManagedRegister& other) const { + if (IsNoRegister() || other.IsNoRegister()) return false; + CHECK(IsValidManagedRegister()); + CHECK(other.IsValidManagedRegister()); + if (Equals(other)) return true; + return false; +} + +void Mips64ManagedRegister::Print(std::ostream& os) const { + if (!IsValidManagedRegister()) { + os << "No Register"; + } else if (IsGpuRegister()) { + os << "GPU: " << static_cast<int>(AsGpuRegister()); + } else if (IsFpuRegister()) { + os << "FpuRegister: " << static_cast<int>(AsFpuRegister()); + } else { + os << "??: " << RegId(); + } +} + +std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg) { + reg.Print(os); + return os; +} + +} // namespace mips64 +} // namespace art diff --git a/compiler/utils/mips64/managed_register_mips64.h b/compiler/utils/mips64/managed_register_mips64.h new file mode 100644 index 0000000000..924a928389 --- /dev/null +++ b/compiler/utils/mips64/managed_register_mips64.h @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_ +#define ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_ + +#include "constants_mips64.h" +#include "utils/managed_register.h" + +namespace art { +namespace mips64 { + +const int kNumberOfGpuRegIds = kNumberOfGpuRegisters; +const int kNumberOfGpuAllocIds = kNumberOfGpuRegisters; + +const int kNumberOfFpuRegIds = kNumberOfFpuRegisters; +const int kNumberOfFpuAllocIds = kNumberOfFpuRegisters; + +const int kNumberOfRegIds = kNumberOfGpuRegIds + kNumberOfFpuRegIds; +const int kNumberOfAllocIds = kNumberOfGpuAllocIds + kNumberOfFpuAllocIds; + +// An instance of class 'ManagedRegister' represents a single GPU register (enum +// Register) or a double precision FP register (enum FpuRegister) +// 'ManagedRegister::NoRegister()' provides an invalid register. +// There is a one-to-one mapping between ManagedRegister and register id. +class Mips64ManagedRegister : public ManagedRegister { + public: + GpuRegister AsGpuRegister() const { + CHECK(IsGpuRegister()); + return static_cast<GpuRegister>(id_); + } + + FpuRegister AsFpuRegister() const { + CHECK(IsFpuRegister()); + return static_cast<FpuRegister>(id_ - kNumberOfGpuRegIds); + } + + bool IsGpuRegister() const { + CHECK(IsValidManagedRegister()); + return (0 <= id_) && (id_ < kNumberOfGpuRegIds); + } + + bool IsFpuRegister() const { + CHECK(IsValidManagedRegister()); + const int test = id_ - kNumberOfGpuRegIds; + return (0 <= test) && (test < kNumberOfFpuRegIds); + } + + void Print(std::ostream& os) const; + + // Returns true if the two managed-registers ('this' and 'other') overlap. + // Either managed-register may be the NoRegister. If both are the NoRegister + // then false is returned. + bool Overlaps(const Mips64ManagedRegister& other) const; + + static Mips64ManagedRegister FromGpuRegister(GpuRegister r) { + CHECK_NE(r, kNoGpuRegister); + return FromRegId(r); + } + + static Mips64ManagedRegister FromFpuRegister(FpuRegister r) { + CHECK_NE(r, kNoFpuRegister); + return FromRegId(r + kNumberOfGpuRegIds); + } + + private: + bool IsValidManagedRegister() const { + return (0 <= id_) && (id_ < kNumberOfRegIds); + } + + int RegId() const { + CHECK(!IsNoRegister()); + return id_; + } + + int AllocId() const { + CHECK(IsValidManagedRegister()); + CHECK_LT(id_, kNumberOfAllocIds); + return id_; + } + + int AllocIdLow() const; + int AllocIdHigh() const; + + friend class ManagedRegister; + + explicit Mips64ManagedRegister(int reg_id) : ManagedRegister(reg_id) {} + + static Mips64ManagedRegister FromRegId(int reg_id) { + Mips64ManagedRegister reg(reg_id); + CHECK(reg.IsValidManagedRegister()); + return reg; + } +}; + +std::ostream& operator<<(std::ostream& os, const Mips64ManagedRegister& reg); + +} // namespace mips64 + +inline mips64::Mips64ManagedRegister ManagedRegister::AsMips64() const { + mips64::Mips64ManagedRegister reg(id_); + CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); + return reg; +} + +} // namespace art + +#endif // ART_COMPILER_UTILS_MIPS64_MANAGED_REGISTER_MIPS64_H_ diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc index d843a7213f..c7414a12fc 100644 --- a/compiler/utils/x86_64/assembler_x86_64.cc +++ b/compiler/utils/x86_64/assembler_x86_64.cc @@ -184,6 +184,20 @@ void X86_64Assembler::movl(const Address& dst, const Immediate& imm) { EmitImmediate(imm); } + +void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src) { + cmov(c, dst, src, true); +} + +void X86_64Assembler::cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitOptionalRex(false, is64bit, dst.NeedsRex(), false, src.NeedsRex()); + EmitUint8(0x0F); + EmitUint8(0x40 + c); + EmitRegisterOperand(dst.LowBits(), src.LowBits()); +} + + void X86_64Assembler::movzxb(CpuRegister dst, CpuRegister src) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); EmitOptionalByteRegNormalizingRex32(dst, src); @@ -369,19 +383,26 @@ void X86_64Assembler::movsxd(CpuRegister dst, const Address& src) { void X86_64Assembler::movd(XmmRegister dst, CpuRegister src) { + movd(dst, src, true); +} + +void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) { + movd(dst, src, true); +} + +void X86_64Assembler::movd(XmmRegister dst, CpuRegister src, bool is64bit) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); EmitUint8(0x66); - EmitRex64(dst, src); + EmitOptionalRex(false, is64bit, dst.NeedsRex(), false, src.NeedsRex()); EmitUint8(0x0F); EmitUint8(0x6E); EmitOperand(dst.LowBits(), Operand(src)); } - -void X86_64Assembler::movd(CpuRegister dst, XmmRegister src) { +void X86_64Assembler::movd(CpuRegister dst, XmmRegister src, bool is64bit) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); EmitUint8(0x66); - EmitRex64(src, dst); + EmitOptionalRex(false, is64bit, src.NeedsRex(), false, dst.NeedsRex()); EmitUint8(0x0F); EmitUint8(0x7E); EmitOperand(src.LowBits(), Operand(dst)); @@ -826,6 +847,39 @@ void X86_64Assembler::andpd(XmmRegister dst, const Address& src) { EmitOperand(dst.LowBits(), src); } +void X86_64Assembler::andpd(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitUint8(0x66); + EmitOptionalRex32(dst, src); + EmitUint8(0x0F); + EmitUint8(0x54); + EmitXmmRegisterOperand(dst.LowBits(), src); +} + +void X86_64Assembler::andps(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitOptionalRex32(dst, src); + EmitUint8(0x0F); + EmitUint8(0x54); + EmitXmmRegisterOperand(dst.LowBits(), src); +} + +void X86_64Assembler::orpd(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitUint8(0x66); + EmitOptionalRex32(dst, src); + EmitUint8(0x0F); + EmitUint8(0x56); + EmitXmmRegisterOperand(dst.LowBits(), src); +} + +void X86_64Assembler::orps(XmmRegister dst, XmmRegister src) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitOptionalRex32(dst, src); + EmitUint8(0x0F); + EmitUint8(0x56); + EmitXmmRegisterOperand(dst.LowBits(), src); +} void X86_64Assembler::fldl(const Address& src) { AssemblerBuffer::EnsureCapacity ensured(&buffer_); @@ -1757,6 +1811,20 @@ void X86_64Assembler::setcc(Condition condition, CpuRegister dst) { EmitUint8(0xC0 + dst.LowBits()); } +void X86_64Assembler::bswapl(CpuRegister dst) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitOptionalRex(false, false, false, false, dst.NeedsRex()); + EmitUint8(0x0F); + EmitUint8(0xC8 + dst.LowBits()); +} + +void X86_64Assembler::bswapq(CpuRegister dst) { + AssemblerBuffer::EnsureCapacity ensured(&buffer_); + EmitOptionalRex(false, true, false, false, dst.NeedsRex()); + EmitUint8(0x0F); + EmitUint8(0xC8 + dst.LowBits()); +} + void X86_64Assembler::LoadDoubleConstant(XmmRegister dst, double value) { // TODO: Need to have a code constants table. diff --git a/compiler/utils/x86_64/assembler_x86_64.h b/compiler/utils/x86_64/assembler_x86_64.h index ac8bc9ab49..5c8d608cf2 100644 --- a/compiler/utils/x86_64/assembler_x86_64.h +++ b/compiler/utils/x86_64/assembler_x86_64.h @@ -276,6 +276,9 @@ class X86_64Assembler FINAL : public Assembler { void movl(const Address& dst, CpuRegister src); void movl(const Address& dst, const Immediate& imm); + void cmov(Condition c, CpuRegister dst, CpuRegister src); // This is the 64b version. + void cmov(Condition c, CpuRegister dst, CpuRegister src, bool is64bit); + void movzxb(CpuRegister dst, CpuRegister src); void movzxb(CpuRegister dst, const Address& src); void movsxb(CpuRegister dst, CpuRegister src); @@ -303,8 +306,10 @@ class X86_64Assembler FINAL : public Assembler { void movsxd(CpuRegister dst, CpuRegister src); void movsxd(CpuRegister dst, const Address& src); - void movd(XmmRegister dst, CpuRegister src); - void movd(CpuRegister dst, XmmRegister src); + void movd(XmmRegister dst, CpuRegister src); // Note: this is the r64 version, formally movq. + void movd(CpuRegister dst, XmmRegister src); // Note: this is the r64 version, formally movq. + void movd(XmmRegister dst, CpuRegister src, bool is64bit); + void movd(CpuRegister dst, XmmRegister src, bool is64bit); void addss(XmmRegister dst, XmmRegister src); void addss(XmmRegister dst, const Address& src); @@ -360,6 +365,11 @@ class X86_64Assembler FINAL : public Assembler { void xorps(XmmRegister dst, XmmRegister src); void andpd(XmmRegister dst, const Address& src); + void andpd(XmmRegister dst, XmmRegister src); + void andps(XmmRegister dst, XmmRegister src); + + void orpd(XmmRegister dst, XmmRegister src); + void orps(XmmRegister dst, XmmRegister src); void flds(const Address& src); void fstps(const Address& dst); @@ -504,6 +514,9 @@ class X86_64Assembler FINAL : public Assembler { void setcc(Condition condition, CpuRegister dst); + void bswapl(CpuRegister dst); + void bswapq(CpuRegister dst); + // // Macros for High-level operations. // diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc index b8d724d771..6df4144004 100644 --- a/compiler/utils/x86_64/assembler_x86_64_test.cc +++ b/compiler/utils/x86_64/assembler_x86_64_test.cc @@ -330,7 +330,6 @@ std::string shlq_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Ass assembler->shlq(*reg, shifter); str << "shlq %cl, %" << assembler_test->GetRegisterName(*reg) << "\n"; } - printf("%s\n", str.str().c_str()); return str.str(); } @@ -690,6 +689,22 @@ TEST_F(AssemblerX86_64Test, Xorpd) { DriverStr(RepeatFF(&x86_64::X86_64Assembler::xorpd, "xorpd %{reg2}, %{reg1}"), "xorpd"); } +TEST_F(AssemblerX86_64Test, Andps) { + DriverStr(RepeatFF(&x86_64::X86_64Assembler::andps, "andps %{reg2}, %{reg1}"), "andps"); +} + +TEST_F(AssemblerX86_64Test, Andpd) { + DriverStr(RepeatFF(&x86_64::X86_64Assembler::andpd, "andpd %{reg2}, %{reg1}"), "andpd"); +} + +TEST_F(AssemblerX86_64Test, Orps) { + DriverStr(RepeatFF(&x86_64::X86_64Assembler::orps, "orps %{reg2}, %{reg1}"), "orps"); +} + +TEST_F(AssemblerX86_64Test, Orpd) { + DriverStr(RepeatFF(&x86_64::X86_64Assembler::orpd, "orpd %{reg2}, %{reg1}"), "orpd"); +} + // X87 std::string x87_fn(AssemblerX86_64Test::Base* assembler_test ATTRIBUTE_UNUSED, @@ -758,6 +773,14 @@ TEST_F(AssemblerX86_64Test, RetAndLeave) { // MISC // ////////// +TEST_F(AssemblerX86_64Test, Bswapl) { + DriverStr(Repeatr(&x86_64::X86_64Assembler::bswapl, "bswap %{reg}"), "bswapl"); +} + +TEST_F(AssemblerX86_64Test, Bswapq) { + DriverStr(RepeatR(&x86_64::X86_64Assembler::bswapq, "bswap %{reg}"), "bswapq"); +} + std::string setcc_test_fn(AssemblerX86_64Test::Base* assembler_test, x86_64::X86_64Assembler* assembler) { // From Condition diff --git a/dex2oat/dex2oat.cc b/dex2oat/dex2oat.cc index 56d4582e69..b576ca295b 100644 --- a/dex2oat/dex2oat.cc +++ b/dex2oat/dex2oat.cc @@ -148,7 +148,7 @@ static void UsageError(const char* fmt, ...) { UsageError(" Example: --android-root=out/host/linux-x86"); UsageError(" Default: $ANDROID_ROOT"); UsageError(""); - UsageError(" --instruction-set=(arm|arm64|mips|x86|x86_64): compile for a particular"); + UsageError(" --instruction-set=(arm|arm64|mips|mips64|x86|x86_64): compile for a particular"); UsageError(" instruction set."); UsageError(" Example: --instruction-set=x86"); UsageError(" Default: arm"); @@ -668,6 +668,8 @@ class Dex2Oat FINAL { dump_timing_ = true; } else if (option == "--dump-passes") { dump_passes_ = true; + } else if (option.starts_with("--dump-cfg=")) { + dump_cfg_file_name_ = option.substr(strlen("--dump-cfg=")).data(); } else if (option == "--dump-stats") { dump_stats_ = true; } else if (option == "--include-debug-symbols" || option == "--no-strip-symbols") { @@ -868,6 +870,7 @@ class Dex2Oat FINAL { // TODO: fix compiler for Mips32r6. compiler_filter_string = "interpret-only"; } else if (instruction_set_ == kMips64) { + // For Mips64, can only compile in interpreter mode. // TODO: fix compiler for Mips64. compiler_filter_string = "interpret-only"; } else if (image_) { @@ -1236,6 +1239,7 @@ class Dex2Oat FINAL { thread_count_, dump_stats_, dump_passes_, + dump_cfg_file_name_, compiler_phases_timings_.get(), swap_fd_, profile_file_)); @@ -1693,6 +1697,7 @@ class Dex2Oat FINAL { bool dump_passes_; bool dump_timing_; bool dump_slow_timing_; + std::string dump_cfg_file_name_; std::string swap_file_name_; int swap_fd_; std::string profile_file_; // Profile file to use diff --git a/disassembler/Android.mk b/disassembler/Android.mk index 3ad29417fa..218b23be3d 100644 --- a/disassembler/Android.mk +++ b/disassembler/Android.mk @@ -23,6 +23,7 @@ LIBART_DISASSEMBLER_SRC_FILES := \ disassembler_arm.cc \ disassembler_arm64.cc \ disassembler_mips.cc \ + disassembler_mips64.cc \ disassembler_x86.cc # $(1): target or host diff --git a/disassembler/disassembler.cc b/disassembler/disassembler.cc index bf68204d75..fbc8dbb404 100644 --- a/disassembler/disassembler.cc +++ b/disassembler/disassembler.cc @@ -23,6 +23,7 @@ #include "disassembler_arm.h" #include "disassembler_arm64.h" #include "disassembler_mips.h" +#include "disassembler_mips64.h" #include "disassembler_x86.h" namespace art { @@ -34,6 +35,8 @@ Disassembler* Disassembler::Create(InstructionSet instruction_set, DisassemblerO return new arm64::DisassemblerArm64(options); } else if (instruction_set == kMips) { return new mips::DisassemblerMips(options); + } else if (instruction_set == kMips64) { + return new mips64::DisassemblerMips64(options); } else if (instruction_set == kX86) { return new x86::DisassemblerX86(options, false); } else if (instruction_set == kX86_64) { diff --git a/disassembler/disassembler_mips64.cc b/disassembler/disassembler_mips64.cc new file mode 100644 index 0000000000..2d3239f4f3 --- /dev/null +++ b/disassembler/disassembler_mips64.cc @@ -0,0 +1,289 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "disassembler_mips64.h" + +#include <ostream> +#include <sstream> + +#include "base/logging.h" +#include "base/stringprintf.h" +#include "thread.h" + +namespace art { +namespace mips64 { + + +struct Mips64Instruction { + uint32_t mask; + uint32_t value; + const char* name; + const char* args_fmt; + + bool Matches(uint32_t instruction) const { + return (instruction & mask) == value; + } +}; + +static const uint32_t kOpcodeShift = 26; +static const uint32_t kCop1 = (17 << kOpcodeShift); +static const uint32_t kITypeMask = (0x3f << kOpcodeShift); +static const uint32_t kJTypeMask = (0x3f << kOpcodeShift); +static const uint32_t kRTypeMask = ((0x3f << kOpcodeShift) | (0x3f)); +static const uint32_t kSpecial2Mask = (0x3f << kOpcodeShift); +static const uint32_t kFpMask = kRTypeMask; + +static const Mips64Instruction gMips64Instructions[] = { + // "sll r0, r0, 0" is the canonical "nop", used in delay slots. + { 0xffffffff, 0, "nop", "" }, + + // R-type instructions. + { kRTypeMask, 0, "sll", "DTA", }, + // 0, 1, movci + { kRTypeMask, 2, "srl", "DTA", }, + { kRTypeMask, 3, "sra", "DTA", }, + { kRTypeMask, 4, "sllv", "DTS", }, + { kRTypeMask, 6, "srlv", "DTS", }, + { kRTypeMask, 7, "srav", "DTS", }, + { kRTypeMask, 8, "jr", "S", }, + // rd = 31 is implicit. + { kRTypeMask | (0x1f << 11), 9 | (31 << 11), "jalr", "S", }, + { kRTypeMask, 9, "jalr", "DS", }, // General case. + { kRTypeMask | (0x1f << 6), 10, "movz", "DST", }, + { kRTypeMask | (0x1f << 6), 11, "movn", "DST", }, + { kRTypeMask, 12, "syscall", "", }, // TODO: code + { kRTypeMask, 13, "break", "", }, // TODO: code + { kRTypeMask, 15, "sync", "", }, // TODO: type + { kRTypeMask, 16, "mfhi", "D", }, + { kRTypeMask, 17, "mthi", "S", }, + { kRTypeMask, 18, "mflo", "D", }, + { kRTypeMask, 19, "mtlo", "S", }, + { kRTypeMask, 24, "mult", "ST", }, + { kRTypeMask, 25, "multu", "ST", }, + { kRTypeMask, 26, "div", "ST", }, + { kRTypeMask, 27, "divu", "ST", }, + { kRTypeMask, 32, "add", "DST", }, + { kRTypeMask, 33, "addu", "DST", }, + { kRTypeMask, 34, "sub", "DST", }, + { kRTypeMask, 35, "subu", "DST", }, + { kRTypeMask, 36, "and", "DST", }, + { kRTypeMask, 37, "or", "DST", }, + { kRTypeMask, 38, "xor", "DST", }, + { kRTypeMask, 39, "nor", "DST", }, + { kRTypeMask, 42, "slt", "DST", }, + { kRTypeMask, 43, "sltu", "DST", }, + { kRTypeMask, 44, "dadd", "DST", }, + { kRTypeMask, 45, "daddu", "DST", }, + { kRTypeMask, 46, "dsub", "DST", }, + { kRTypeMask, 47, "dsubu", "DST", }, + // 0, 48, tge + // 0, 49, tgeu + // 0, 50, tlt + // 0, 51, tltu + // 0, 52, teq + // 0, 54, tne + + // SPECIAL2 + { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 2, "mul", "DST" }, + { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 32, "clz", "DS" }, + { kSpecial2Mask | 0x7ff, (28 << kOpcodeShift) | 36, "dclz", "DS" }, + { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 0, "madd", "ST" }, + { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 1, "maddu", "ST" }, + { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 2, "mul", "DST" }, + { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 4, "msub", "ST" }, + { kSpecial2Mask | 0xffff, (28 << kOpcodeShift) | 5, "msubu", "ST" }, + { kSpecial2Mask | 0x3f, (28 << kOpcodeShift) | 0x3f, "sdbbp", "" }, + + // J-type instructions. + { kJTypeMask, 2 << kOpcodeShift, "j", "L" }, + { kJTypeMask, 3 << kOpcodeShift, "jal", "L" }, + + // I-type instructions. + { kITypeMask, 4 << kOpcodeShift, "beq", "STB" }, + { kITypeMask, 5 << kOpcodeShift, "bne", "STB" }, + { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (1 << 16), "bgez", "SB" }, + { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (0 << 16), "bltz", "SB" }, + { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (2 << 16), "bltzl", "SB" }, + { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (16 << 16), "bltzal", "SB" }, + { kITypeMask | (0x1f << 16), 1 << kOpcodeShift | (18 << 16), "bltzall", "SB" }, + { kITypeMask | (0x1f << 16), 6 << kOpcodeShift | (0 << 16), "blez", "SB" }, + { kITypeMask | (0x1f << 16), 7 << kOpcodeShift | (0 << 16), "bgtz", "SB" }, + + { 0xffff0000, (4 << kOpcodeShift), "b", "B" }, + { 0xffff0000, (1 << kOpcodeShift) | (17 << 16), "bal", "B" }, + + { kITypeMask, 8 << kOpcodeShift, "addi", "TSi", }, + { kITypeMask, 9 << kOpcodeShift, "addiu", "TSi", }, + { kITypeMask, 10 << kOpcodeShift, "slti", "TSi", }, + { kITypeMask, 11 << kOpcodeShift, "sltiu", "TSi", }, + { kITypeMask, 12 << kOpcodeShift, "andi", "TSi", }, + { kITypeMask, 13 << kOpcodeShift, "ori", "TSi", }, + { kITypeMask, 14 << kOpcodeShift, "ori", "TSi", }, + { kITypeMask, 15 << kOpcodeShift, "lui", "TI", }, + + { kITypeMask, 24 << kOpcodeShift, "daddi", "TSi", }, + { kITypeMask, 25 << kOpcodeShift, "daddiu", "TSi", }, + + + { kITypeMask, 32u << kOpcodeShift, "lb", "TO", }, + { kITypeMask, 33u << kOpcodeShift, "lh", "TO", }, + { kITypeMask, 35u << kOpcodeShift, "lw", "TO", }, + { kITypeMask, 36u << kOpcodeShift, "lbu", "TO", }, + { kITypeMask, 37u << kOpcodeShift, "lhu", "TO", }, + { kITypeMask, 40u << kOpcodeShift, "sb", "TO", }, + { kITypeMask, 41u << kOpcodeShift, "sh", "TO", }, + { kITypeMask, 43u << kOpcodeShift, "sw", "TO", }, + { kITypeMask, 49u << kOpcodeShift, "lwc1", "tO", }, + { kITypeMask, 53u << kOpcodeShift, "ldc1", "tO", }, + { kITypeMask, 55u << kOpcodeShift, "ld", "TO", }, + { kITypeMask, 57u << kOpcodeShift, "swc1", "tO", }, + { kITypeMask, 61u << kOpcodeShift, "sdc1", "tO", }, + { kITypeMask, 63u << kOpcodeShift, "sd", "TO", }, + + // Floating point. + { kFpMask, kCop1 | 0, "add", "fdst" }, + { kFpMask, kCop1 | 1, "sub", "fdst" }, + { kFpMask, kCop1 | 2, "mul", "fdst" }, + { kFpMask, kCop1 | 3, "div", "fdst" }, + { kFpMask | (0x1f << 16), kCop1 | 4, "sqrt", "fdst" }, + { kFpMask | (0x1f << 16), kCop1 | 5, "abs", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 6, "mov", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 7, "neg", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 8, "round.l", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 9, "trunc.l", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 10, "ceil.l", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 11, "floor.l", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 12, "round.w", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 13, "trunc.w", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 14, "ceil.w", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 15, "floor.w", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 32, "cvt.s", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 33, "cvt.d", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 36, "cvt.w", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 37, "cvt.l", "fds" }, + { kFpMask | (0x1f << 16), kCop1 | 38, "cvt.ps", "fds" }, +}; + +static uint32_t ReadU32(const uint8_t* ptr) { + // We only support little-endian MIPS64. + return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); +} + +static void DumpMips64(std::ostream& os, const uint8_t* instr_ptr) { + uint32_t instruction = ReadU32(instr_ptr); + + uint32_t rs = (instruction >> 21) & 0x1f; // I-type, R-type. + uint32_t rt = (instruction >> 16) & 0x1f; // I-type, R-type. + uint32_t rd = (instruction >> 11) & 0x1f; // R-type. + uint32_t sa = (instruction >> 6) & 0x1f; // R-type. + + std::string opcode; + std::ostringstream args; + + // TODO: remove this! + uint32_t op = (instruction >> 26) & 0x3f; + uint32_t function = (instruction & 0x3f); // R-type. + opcode = StringPrintf("op=%d fn=%d", op, function); + + for (size_t i = 0; i < arraysize(gMips64Instructions); ++i) { + if (gMips64Instructions[i].Matches(instruction)) { + opcode = gMips64Instructions[i].name; + for (const char* args_fmt = gMips64Instructions[i].args_fmt; *args_fmt; ++args_fmt) { + switch (*args_fmt) { + case 'A': // sa (shift amount). + args << sa; + break; + case 'B': // Branch offset. + { + int32_t offset = static_cast<int16_t>(instruction & 0xffff); + offset <<= 2; + offset += 4; // Delay slot. + args << StringPrintf("%p ; %+d", instr_ptr + offset, offset); + } + break; + case 'D': args << 'r' << rd; break; + case 'd': args << 'f' << rd; break; + case 'f': // Floating point "fmt". + { + size_t fmt = (instruction >> 21) & 0x7; // TODO: other fmts? + switch (fmt) { + case 0: opcode += ".s"; break; + case 1: opcode += ".d"; break; + case 4: opcode += ".w"; break; + case 5: opcode += ".l"; break; + case 6: opcode += ".ps"; break; + default: opcode += ".?"; break; + } + continue; // No ", ". + } + break; + case 'I': // Upper 16-bit immediate. + args << reinterpret_cast<void*>((instruction & 0xffff) << 16); + break; + case 'i': // Sign-extended lower 16-bit immediate. + args << static_cast<int16_t>(instruction & 0xffff); + break; + case 'L': // Jump label. + { + // TODO: is this right? + uint32_t instr_index = (instruction & 0x1ffffff); + uint32_t target = (instr_index << 2); + target |= (reinterpret_cast<uintptr_t>(instr_ptr + 4) + & 0xf0000000); + args << reinterpret_cast<void*>(target); + } + break; + case 'O': // +x(rs) + { + int32_t offset = static_cast<int16_t>(instruction & 0xffff); + args << StringPrintf("%+d(r%d)", offset, rs); + if (rs == 17) { + args << " ; "; + Thread::DumpThreadOffset<8>(args, offset); + } + } + break; + case 'S': args << 'r' << rs; break; + case 's': args << 'f' << rs; break; + case 'T': args << 'r' << rt; break; + case 't': args << 'f' << rt; break; + } + if (*(args_fmt + 1)) { + args << ", "; + } + } + break; + } + } + + os << StringPrintf("%p: %08x\t%-7s ", instr_ptr, instruction, opcode.c_str()) + << args.str() << '\n'; +} + +size_t DisassemblerMips64::Dump(std::ostream& os, const uint8_t* begin) { + DumpMips64(os, begin); + return 4; +} + +void DisassemblerMips64::Dump(std::ostream& os, const uint8_t* begin, + const uint8_t* end) { + for (const uint8_t* cur = begin; cur < end; cur += 4) { + DumpMips64(os, cur); + } +} + +} // namespace mips64 +} // namespace art diff --git a/disassembler/disassembler_mips64.h b/disassembler/disassembler_mips64.h new file mode 100644 index 0000000000..06efdc86fc --- /dev/null +++ b/disassembler/disassembler_mips64.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_DISASSEMBLER_DISASSEMBLER_MIPS64_H_ +#define ART_DISASSEMBLER_DISASSEMBLER_MIPS64_H_ + +#include <vector> + +#include "disassembler.h" + +namespace art { +namespace mips64 { + +class DisassemblerMips64 FINAL : public Disassembler { + public: + explicit DisassemblerMips64(DisassemblerOptions* options) : Disassembler(options) {} + + size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE; + void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE; + + private: + DISALLOW_COPY_AND_ASSIGN(DisassemblerMips64); +}; + +} // namespace mips64 +} // namespace art + +#endif // ART_DISASSEMBLER_DISASSEMBLER_MIPS64_H_ diff --git a/patchoat/patchoat.cc b/patchoat/patchoat.cc index 28f966826b..6c86c7b7a5 100644 --- a/patchoat/patchoat.cc +++ b/patchoat/patchoat.cc @@ -62,6 +62,8 @@ static InstructionSet ElfISAToInstructionSet(Elf32_Word isa, Elf32_Word e_flags) if (((e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R2) || ((e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6)) { return kMips; + } else if ((e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) { + return kMips64; } else { return kNone; } diff --git a/runtime/Android.mk b/runtime/Android.mk index 13a216c48b..d1040776b8 100644 --- a/runtime/Android.mk +++ b/runtime/Android.mk @@ -170,6 +170,8 @@ LIBART_COMMON_SRC_FILES += \ arch/arm64/registers_arm64.cc \ arch/mips/instruction_set_features_mips.cc \ arch/mips/registers_mips.cc \ + arch/mips64/instruction_set_features_mips64.cc \ + arch/mips64/registers_mips64.cc \ arch/x86/instruction_set_features_x86.cc \ arch/x86/registers_x86.cc \ arch/x86_64/registers_x86_64.cc \ @@ -262,9 +264,15 @@ LIBART_TARGET_SRC_FILES_mips := \ arch/mips/thread_mips.cc \ arch/mips/fault_handler_mips.cc -ifeq ($(TARGET_ARCH),mips64) -$(info TODOMips64: $(LOCAL_PATH)/Android.mk Add mips64 specific runtime files) -endif # TARGET_ARCH != mips64 +LIBART_TARGET_SRC_FILES_mips64 := \ + arch/mips64/context_mips64.cc \ + arch/mips64/entrypoints_init_mips64.cc \ + arch/mips64/jni_entrypoints_mips64.S \ + arch/mips64/memcmp16_mips64.S \ + arch/mips64/quick_entrypoints_mips64.S \ + arch/mips64/thread_mips64.cc \ + monitor_pool.cc \ + arch/mips64/fault_handler_mips64.cc LIBART_HOST_SRC_FILES := \ $(LIBART_COMMON_SRC_FILES) \ @@ -286,6 +294,7 @@ LIBART_ENUM_OPERATOR_OUT_HEADER_FILES := \ base/unix_file/fd_file.h \ dex_file.h \ dex_instruction.h \ + gc_root.h \ gc/allocator/rosalloc.h \ gc/collector/gc_type.h \ gc/allocator_type.h \ @@ -523,6 +532,7 @@ LIBART_TARGET_SRC_FILES_arm64 := LIBART_TARGET_SRC_FILES_x86 := LIBART_TARGET_SRC_FILES_x86_64 := LIBART_TARGET_SRC_FILES_mips := +LIBART_TARGET_SRC_FILES_mips64 := LIBART_HOST_SRC_FILES := LIBART_HOST_SRC_FILES_32 := LIBART_HOST_SRC_FILES_64 := diff --git a/runtime/arch/arch_test.cc b/runtime/arch/arch_test.cc index cac500c13e..ab6b00bddf 100644 --- a/runtime/arch/arch_test.cc +++ b/runtime/arch/arch_test.cc @@ -82,6 +82,16 @@ static constexpr size_t kFrameSizeRefsAndArgsCalleeSave = FRAME_SIZE_REFS_AND_AR #undef FRAME_SIZE_REFS_AND_ARGS_CALLEE_SAVE } +namespace mips64 { +#include "arch/mips64/asm_support_mips64.h" +static constexpr size_t kFrameSizeSaveAllCalleeSave = FRAME_SIZE_SAVE_ALL_CALLEE_SAVE; +#undef FRAME_SIZE_SAVE_ALL_CALLEE_SAVE +static constexpr size_t kFrameSizeRefsOnlyCalleeSave = FRAME_SIZE_REFS_ONLY_CALLEE_SAVE; +#undef FRAME_SIZE_REFS_ONLY_CALLEE_SAVE +static constexpr size_t kFrameSizeRefsAndArgsCalleeSave = FRAME_SIZE_REFS_AND_ARGS_CALLEE_SAVE; +#undef FRAME_SIZE_REFS_AND_ARGS_CALLEE_SAVE +} + namespace x86 { #include "arch/x86/asm_support_x86.h" static constexpr size_t kFrameSizeSaveAllCalleeSave = FRAME_SIZE_SAVE_ALL_CALLEE_SAVE; @@ -124,6 +134,13 @@ TEST_F(ArchTest, MIPS) { mips::kFrameSizeRefsAndArgsCalleeSave); } +TEST_F(ArchTest, MIPS64) { + CheckFrameSize(InstructionSet::kMips64, Runtime::kSaveAll, mips64::kFrameSizeSaveAllCalleeSave); + CheckFrameSize(InstructionSet::kMips64, Runtime::kRefsOnly, mips64::kFrameSizeRefsOnlyCalleeSave); + CheckFrameSize(InstructionSet::kMips64, Runtime::kRefsAndArgs, + mips64::kFrameSizeRefsAndArgsCalleeSave); +} + TEST_F(ArchTest, X86) { CheckFrameSize(InstructionSet::kX86, Runtime::kSaveAll, x86::kFrameSizeSaveAllCalleeSave); CheckFrameSize(InstructionSet::kX86, Runtime::kRefsOnly, x86::kFrameSizeRefsOnlyCalleeSave); diff --git a/runtime/arch/context.cc b/runtime/arch/context.cc index b1700bbef8..bf40a3f8ce 100644 --- a/runtime/arch/context.cc +++ b/runtime/arch/context.cc @@ -20,8 +20,10 @@ #include "arm/context_arm.h" #elif defined(__aarch64__) #include "arm64/context_arm64.h" -#elif defined(__mips__) +#elif defined(__mips__) && !defined(__LP64__) #include "mips/context_mips.h" +#elif defined(__mips__) && defined(__LP64__) +#include "mips64/context_mips64.h" #elif defined(__i386__) #include "x86/context_x86.h" #elif defined(__x86_64__) @@ -37,8 +39,10 @@ Context* Context::Create() { return new arm::ArmContext(); #elif defined(__aarch64__) return new arm64::Arm64Context(); -#elif defined(__mips__) +#elif defined(__mips__) && !defined(__LP64__) return new mips::MipsContext(); +#elif defined(__mips__) && defined(__LP64__) + return new mips64::Mips64Context(); #elif defined(__i386__) return new x86::X86Context(); #elif defined(__x86_64__) diff --git a/runtime/arch/instruction_set.cc b/runtime/arch/instruction_set.cc index 92fa727674..5ab461bc73 100644 --- a/runtime/arch/instruction_set.cc +++ b/runtime/arch/instruction_set.cc @@ -57,7 +57,7 @@ InstructionSet GetInstructionSetFromString(const char* isa_str) { } else if (strcmp("mips", isa_str) == 0) { return kMips; } else if (strcmp("mips64", isa_str) == 0) { - return kMips; + return kMips64; } return kNone; @@ -76,6 +76,8 @@ size_t GetInstructionSetAlignment(InstructionSet isa) { case kX86_64: return kX86Alignment; case kMips: + // Fall-through. + case kMips64: return kMipsAlignment; case kNone: LOG(FATAL) << "ISA kNone does not have alignment."; @@ -88,6 +90,7 @@ size_t GetInstructionSetAlignment(InstructionSet isa) { static constexpr size_t kDefaultStackOverflowReservedBytes = 16 * KB; static constexpr size_t kMipsStackOverflowReservedBytes = kDefaultStackOverflowReservedBytes; +static constexpr size_t kMips64StackOverflowReservedBytes = kDefaultStackOverflowReservedBytes; static constexpr size_t kArmStackOverflowReservedBytes = 8 * KB; static constexpr size_t kArm64StackOverflowReservedBytes = 8 * KB; @@ -106,6 +109,9 @@ size_t GetStackOverflowReservedBytes(InstructionSet isa) { case kMips: return kMipsStackOverflowReservedBytes; + case kMips64: + return kMips64StackOverflowReservedBytes; + case kX86: return kX86StackOverflowReservedBytes; diff --git a/runtime/arch/instruction_set.h b/runtime/arch/instruction_set.h index e413880094..9135e58c1a 100644 --- a/runtime/arch/instruction_set.h +++ b/runtime/arch/instruction_set.h @@ -40,8 +40,10 @@ std::ostream& operator<<(std::ostream& os, const InstructionSet& rhs); static constexpr InstructionSet kRuntimeISA = kArm; #elif defined(__aarch64__) static constexpr InstructionSet kRuntimeISA = kArm64; -#elif defined(__mips__) +#elif defined(__mips__) && !defined(__LP64__) static constexpr InstructionSet kRuntimeISA = kMips; +#elif defined(__mips__) && defined(__LP64__) +static constexpr InstructionSet kRuntimeISA = kMips64; #elif defined(__i386__) static constexpr InstructionSet kRuntimeISA = kX86; #elif defined(__x86_64__) @@ -145,6 +147,8 @@ static inline size_t GetBytesPerGprSpillLocation(InstructionSet isa) { return 8; case kMips: return 4; + case kMips64: + return 8; case kNone: LOG(FATAL) << "ISA kNone does not have spills."; UNREACHABLE(); @@ -168,6 +172,8 @@ static inline size_t GetBytesPerFprSpillLocation(InstructionSet isa) { return 8; case kMips: return 4; + case kMips64: + return 8; case kNone: LOG(FATAL) << "ISA kNone does not have spills."; UNREACHABLE(); @@ -186,8 +192,8 @@ size_t GetStackOverflowReservedBytes(InstructionSet isa); // On x86, ARM32 and MIPS, this is given for a *scalar* 64bit value. The definition thus *must* be // uint64_t or long long int. // -// On x86_64 and ARM64, structs are decomposed for allocation, so we can create a structs of two -// size_t-sized values. +// On x86_64, ARM64 and MIPS64, structs are decomposed for allocation, so we can create a structs of +// two size_t-sized values. // // We need two operations: // @@ -202,7 +208,7 @@ size_t GetStackOverflowReservedBytes(InstructionSet isa); // when the garbage collector can move objects concurrently. Ensure that required locks // are held when using! -#if defined(__i386__) || defined(__arm__) || defined(__mips__) +#if defined(__i386__) || defined(__arm__) || (defined(__mips__) && !defined(__LP64__)) typedef uint64_t TwoWordReturn; // Encodes method_ptr==nullptr and code_ptr==nullptr @@ -218,7 +224,7 @@ static inline TwoWordReturn GetTwoWordSuccessValue(uintptr_t hi, uintptr_t lo) { return ((hi64 << 32) | lo32); } -#elif defined(__x86_64__) || defined(__aarch64__) +#elif defined(__x86_64__) || defined(__aarch64__) || (defined(__mips__) && defined(__LP64__)) struct TwoWordReturn { uintptr_t lo; uintptr_t hi; diff --git a/runtime/arch/instruction_set_features.cc b/runtime/arch/instruction_set_features.cc index 10725620a4..1fd1deadef 100644 --- a/runtime/arch/instruction_set_features.cc +++ b/runtime/arch/instruction_set_features.cc @@ -23,6 +23,7 @@ #include "arm/instruction_set_features_arm.h" #include "arm64/instruction_set_features_arm64.h" #include "mips/instruction_set_features_mips.h" +#include "mips64/instruction_set_features_mips64.h" #include "x86/instruction_set_features_x86.h" #include "x86_64/instruction_set_features_x86_64.h" @@ -43,6 +44,9 @@ const InstructionSetFeatures* InstructionSetFeatures::FromVariant(InstructionSet case kMips: result = MipsInstructionSetFeatures::FromVariant(variant, error_msg); break; + case kMips64: + result = Mips64InstructionSetFeatures::FromVariant(variant, error_msg); + break; case kX86: result = X86InstructionSetFeatures::FromVariant(variant, error_msg); break; @@ -71,6 +75,9 @@ const InstructionSetFeatures* InstructionSetFeatures::FromBitmap(InstructionSet case kMips: result = MipsInstructionSetFeatures::FromBitmap(bitmap); break; + case kMips64: + result = Mips64InstructionSetFeatures::FromBitmap(bitmap); + break; case kX86: result = X86InstructionSetFeatures::FromBitmap(bitmap); break; @@ -98,6 +105,9 @@ const InstructionSetFeatures* InstructionSetFeatures::FromCppDefines() { case kMips: result = MipsInstructionSetFeatures::FromCppDefines(); break; + case kMips64: + result = Mips64InstructionSetFeatures::FromCppDefines(); + break; case kX86: result = X86InstructionSetFeatures::FromCppDefines(); break; @@ -125,6 +135,9 @@ const InstructionSetFeatures* InstructionSetFeatures::FromCpuInfo() { case kMips: result = MipsInstructionSetFeatures::FromCpuInfo(); break; + case kMips64: + result = Mips64InstructionSetFeatures::FromCpuInfo(); + break; case kX86: result = X86InstructionSetFeatures::FromCpuInfo(); break; @@ -151,6 +164,9 @@ const InstructionSetFeatures* InstructionSetFeatures::FromHwcap() { case kMips: result = MipsInstructionSetFeatures::FromHwcap(); break; + case kMips64: + result = Mips64InstructionSetFeatures::FromHwcap(); + break; case kX86: result = X86InstructionSetFeatures::FromHwcap(); break; @@ -177,6 +193,9 @@ const InstructionSetFeatures* InstructionSetFeatures::FromAssembly() { case kMips: result = MipsInstructionSetFeatures::FromAssembly(); break; + case kMips64: + result = Mips64InstructionSetFeatures::FromAssembly(); + break; case kX86: result = X86InstructionSetFeatures::FromAssembly(); break; @@ -250,6 +269,11 @@ const MipsInstructionSetFeatures* InstructionSetFeatures::AsMipsInstructionSetFe return down_cast<const MipsInstructionSetFeatures*>(this); } +const Mips64InstructionSetFeatures* InstructionSetFeatures::AsMips64InstructionSetFeatures() const { + DCHECK_EQ(kMips64, GetInstructionSet()); + return down_cast<const Mips64InstructionSetFeatures*>(this); +} + const X86InstructionSetFeatures* InstructionSetFeatures::AsX86InstructionSetFeatures() const { DCHECK(kX86 == GetInstructionSet() || kX86_64 == GetInstructionSet()); return down_cast<const X86InstructionSetFeatures*>(this); diff --git a/runtime/arch/instruction_set_features.h b/runtime/arch/instruction_set_features.h index 2c6e6995bc..e4513ef272 100644 --- a/runtime/arch/instruction_set_features.h +++ b/runtime/arch/instruction_set_features.h @@ -28,6 +28,7 @@ namespace art { class ArmInstructionSetFeatures; class Arm64InstructionSetFeatures; class MipsInstructionSetFeatures; +class Mips64InstructionSetFeatures; class X86InstructionSetFeatures; class X86_64InstructionSetFeatures; @@ -87,6 +88,9 @@ class InstructionSetFeatures { // Down cast this MipsInstructionFeatures. const MipsInstructionSetFeatures* AsMipsInstructionSetFeatures() const; + // Down cast this Mips64InstructionFeatures. + const Mips64InstructionSetFeatures* AsMips64InstructionSetFeatures() const; + // Down cast this X86InstructionFeatures. const X86InstructionSetFeatures* AsX86InstructionSetFeatures() const; diff --git a/runtime/arch/instruction_set_test.cc b/runtime/arch/instruction_set_test.cc index 932ef323fc..2f3cf18a1f 100644 --- a/runtime/arch/instruction_set_test.cc +++ b/runtime/arch/instruction_set_test.cc @@ -28,6 +28,7 @@ TEST(InstructionSetTest, GetInstructionSetFromString) { EXPECT_EQ(kX86, GetInstructionSetFromString("x86")); EXPECT_EQ(kX86_64, GetInstructionSetFromString("x86_64")); EXPECT_EQ(kMips, GetInstructionSetFromString("mips")); + EXPECT_EQ(kMips64, GetInstructionSetFromString("mips64")); EXPECT_EQ(kNone, GetInstructionSetFromString("none")); EXPECT_EQ(kNone, GetInstructionSetFromString("random-string")); } @@ -39,6 +40,7 @@ TEST(InstructionSetTest, GetInstructionSetString) { EXPECT_STREQ("x86", GetInstructionSetString(kX86)); EXPECT_STREQ("x86_64", GetInstructionSetString(kX86_64)); EXPECT_STREQ("mips", GetInstructionSetString(kMips)); + EXPECT_STREQ("mips64", GetInstructionSetString(kMips64)); EXPECT_STREQ("none", GetInstructionSetString(kNone)); } diff --git a/runtime/arch/mips64/asm_support_mips64.S b/runtime/arch/mips64/asm_support_mips64.S new file mode 100644 index 0000000000..10976bb70d --- /dev/null +++ b/runtime/arch/mips64/asm_support_mips64.S @@ -0,0 +1,71 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_ASM_SUPPORT_MIPS64_S_ +#define ART_RUNTIME_ARCH_MIPS64_ASM_SUPPORT_MIPS64_S_ + +#include "asm_support_mips64.h" + +// Define special registers. + +// Register holding suspend check count down. +#define rSUSPEND $s0 +// Register holding Thread::Current(). +#define rSELF $s1 + + + // Declare a function called name, sets up $gp. +.macro ENTRY name + .type \name, %function + .global \name + // Cache alignment for function entry. + .balign 16 +\name: + .cfi_startproc + // Ensure we get a sane starting CFA. + .cfi_def_cfa $sp,0 + // Load $gp. We expect that ".set noreorder" is in effect. + .cpload $t9 + // Declare a local convenience label to be branched to when $gp is already set up. +.L\name\()_gp_set: +.endm + + // Declare a function called name, doesn't set up $gp. +.macro ENTRY_NO_GP name + .type \name, %function + .global \name + // Cache alignment for function entry. + .balign 16 +\name: + .cfi_startproc + // Ensure we get a sane starting CFA. + .cfi_def_cfa $sp,0 +.endm + +.macro END name + .cfi_endproc + .size \name, .-\name +.endm + +.macro UNIMPLEMENTED name + ENTRY \name + break + break + END \name +.endm + + +#endif // ART_RUNTIME_ARCH_MIPS64_ASM_SUPPORT_MIPS64_S_ diff --git a/runtime/arch/mips64/asm_support_mips64.h b/runtime/arch/mips64/asm_support_mips64.h new file mode 100644 index 0000000000..995fcf37bf --- /dev/null +++ b/runtime/arch/mips64/asm_support_mips64.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_ASM_SUPPORT_MIPS64_H_ +#define ART_RUNTIME_ARCH_MIPS64_ASM_SUPPORT_MIPS64_H_ + +#include "asm_support.h" + +// 64 ($f24-$f31) + 64 ($s0-$s7) + 8 ($gp) + 8 ($s8) + 8 ($ra) + 1x8 bytes padding +#define FRAME_SIZE_SAVE_ALL_CALLEE_SAVE 160 +// 48 ($s2-$s7) + 8 ($gp) + 8 ($s8) + 8 ($ra) + 1x8 bytes padding +#define FRAME_SIZE_REFS_ONLY_CALLEE_SAVE 80 +// $f12-$f19, $a1-$a7, $s2-$s7 + $gp + $s8 + $ra, 16 total + 1x8 bytes padding + method* +#define FRAME_SIZE_REFS_AND_ARGS_CALLEE_SAVE 208 + +#endif // ART_RUNTIME_ARCH_MIPS64_ASM_SUPPORT_MIPS64_H_ diff --git a/runtime/arch/mips64/context_mips64.cc b/runtime/arch/mips64/context_mips64.cc new file mode 100644 index 0000000000..7523adee31 --- /dev/null +++ b/runtime/arch/mips64/context_mips64.cc @@ -0,0 +1,147 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "context_mips64.h" + +#include "mirror/art_method-inl.h" +#include "quick/quick_method_frame_info.h" +#include "util.h" + +namespace art { +namespace mips64 { + +static constexpr uintptr_t gZero = 0; + +void Mips64Context::Reset() { + for (size_t i = 0; i < kNumberOfGpuRegisters; i++) { + gprs_[i] = nullptr; + } + for (size_t i = 0; i < kNumberOfFpuRegisters; i++) { + fprs_[i] = nullptr; + } + gprs_[SP] = &sp_; + gprs_[RA] = &ra_; + // Initialize registers with easy to spot debug values. + sp_ = Mips64Context::kBadGprBase + SP; + ra_ = Mips64Context::kBadGprBase + RA; +} + +void Mips64Context::FillCalleeSaves(const StackVisitor& fr) { + mirror::ArtMethod* method = fr.GetMethod(); + const QuickMethodFrameInfo frame_info = method->GetQuickFrameInfo(); + size_t spill_count = POPCOUNT(frame_info.CoreSpillMask()); + size_t fp_spill_count = POPCOUNT(frame_info.FpSpillMask()); + if (spill_count > 0) { + // Lowest number spill is farthest away, walk registers and fill into context. + int j = 1; + for (size_t i = 0; i < kNumberOfGpuRegisters; i++) { + if (((frame_info.CoreSpillMask() >> i) & 1) != 0) { + gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes()); + j++; + } + } + } + if (fp_spill_count > 0) { + // Lowest number spill is farthest away, walk registers and fill into context. + int j = 1; + for (size_t i = 0; i < kNumberOfFpuRegisters; i++) { + if (((frame_info.FpSpillMask() >> i) & 1) != 0) { + fprs_[i] = fr.CalleeSaveAddress(spill_count + fp_spill_count - j, + frame_info.FrameSizeInBytes()); + j++; + } + } + } +} + +bool Mips64Context::SetGPR(uint32_t reg, uintptr_t value) { + CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); + CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. + if (gprs_[reg] != nullptr) { + *gprs_[reg] = value; + return true; + } else { + return false; + } +} + +bool Mips64Context::SetFPR(uint32_t reg, uintptr_t value) { + CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFpuRegisters)); + CHECK_NE(fprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. + if (fprs_[reg] != nullptr) { + *fprs_[reg] = value; + return true; + } else { + return false; + } +} + +void Mips64Context::SmashCallerSaves() { + // This needs to be 0 because we want a null/zero return value. + gprs_[V0] = const_cast<uintptr_t*>(&gZero); + gprs_[V1] = const_cast<uintptr_t*>(&gZero); + gprs_[A1] = nullptr; + gprs_[A0] = nullptr; + gprs_[A2] = nullptr; + gprs_[A3] = nullptr; + gprs_[A4] = nullptr; + gprs_[A5] = nullptr; + gprs_[A6] = nullptr; + gprs_[A7] = nullptr; + + // f0-f23 are caller-saved; f24-f31 are callee-saved. + fprs_[F0] = nullptr; + fprs_[F1] = nullptr; + fprs_[F2] = nullptr; + fprs_[F3] = nullptr; + fprs_[F4] = nullptr; + fprs_[F5] = nullptr; + fprs_[F6] = nullptr; + fprs_[F7] = nullptr; + fprs_[F8] = nullptr; + fprs_[F9] = nullptr; + fprs_[F10] = nullptr; + fprs_[F11] = nullptr; + fprs_[F12] = nullptr; + fprs_[F13] = nullptr; + fprs_[F14] = nullptr; + fprs_[F15] = nullptr; + fprs_[F16] = nullptr; + fprs_[F17] = nullptr; + fprs_[F18] = nullptr; + fprs_[F19] = nullptr; + fprs_[F20] = nullptr; + fprs_[F21] = nullptr; + fprs_[F22] = nullptr; + fprs_[F23] = nullptr; +} + +extern "C" void art_quick_do_long_jump(uintptr_t*, uintptr_t*); + +void Mips64Context::DoLongJump() { + uintptr_t gprs[kNumberOfGpuRegisters]; + uintptr_t fprs[kNumberOfFpuRegisters]; + for (size_t i = 0; i < kNumberOfGpuRegisters; ++i) { + gprs[i] = gprs_[i] != nullptr ? *gprs_[i] : Mips64Context::kBadGprBase + i; + } + for (size_t i = 0; i < kNumberOfFpuRegisters; ++i) { + fprs[i] = fprs_[i] != nullptr ? *fprs_[i] : Mips64Context::kBadFprBase + i; + } + art_quick_do_long_jump(gprs, fprs); +} + +} // namespace mips64 +} // namespace art diff --git a/runtime/arch/mips64/context_mips64.h b/runtime/arch/mips64/context_mips64.h new file mode 100644 index 0000000000..4ba5f13b14 --- /dev/null +++ b/runtime/arch/mips64/context_mips64.h @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_CONTEXT_MIPS64_H_ +#define ART_RUNTIME_ARCH_MIPS64_CONTEXT_MIPS64_H_ + +#include "arch/context.h" +#include "base/logging.h" +#include "registers_mips64.h" + +namespace art { +namespace mips64 { + +class Mips64Context : public Context { + public: + Mips64Context() { + Reset(); + } + virtual ~Mips64Context() {} + + void Reset() OVERRIDE; + + void FillCalleeSaves(const StackVisitor& fr) OVERRIDE SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); + + void SetSP(uintptr_t new_sp) OVERRIDE { + bool success = SetGPR(SP, new_sp); + CHECK(success) << "Failed to set SP register"; + } + + void SetPC(uintptr_t new_pc) OVERRIDE { + bool success = SetGPR(RA, new_pc); + CHECK(success) << "Failed to set RA register"; + } + + uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { + DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); + return gprs_[reg]; + } + + bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { + CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); + if (gprs_[reg] == nullptr) { + return false; + } else { + DCHECK(val != nullptr); + *val = *gprs_[reg]; + return true; + } + } + + bool SetGPR(uint32_t reg, uintptr_t value) OVERRIDE; + + bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { + CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFpuRegisters)); + if (fprs_[reg] == nullptr) { + return false; + } else { + DCHECK(val != nullptr); + *val = *fprs_[reg]; + return true; + } + } + + bool SetFPR(uint32_t reg, uintptr_t value) OVERRIDE; + + void SmashCallerSaves() OVERRIDE; + void DoLongJump() OVERRIDE; + + private: + // Pointers to registers in the stack, initialized to NULL except for the special cases below. + uintptr_t* gprs_[kNumberOfGpuRegisters]; + uint64_t* fprs_[kNumberOfFpuRegisters]; + // Hold values for sp and ra (return address) if they are not located within a stack frame. + uintptr_t sp_, ra_; +}; +} // namespace mips64 +} // namespace art + +#endif // ART_RUNTIME_ARCH_MIPS64_CONTEXT_MIPS64_H_ diff --git a/runtime/arch/mips64/entrypoints_init_mips64.cc b/runtime/arch/mips64/entrypoints_init_mips64.cc new file mode 100644 index 0000000000..4a3bf02f2f --- /dev/null +++ b/runtime/arch/mips64/entrypoints_init_mips64.cc @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "atomic.h" +#include "entrypoints/interpreter/interpreter_entrypoints.h" +#include "entrypoints/jni/jni_entrypoints.h" +#include "entrypoints/quick/quick_alloc_entrypoints.h" +#include "entrypoints/quick/quick_default_externs.h" +#include "entrypoints/quick/quick_entrypoints.h" +#include "entrypoints/entrypoint_utils.h" +#include "entrypoints/math_entrypoints.h" +#include "entrypoints/runtime_asm_entrypoints.h" +#include "interpreter/interpreter.h" + +namespace art { + +// Cast entrypoints. +extern "C" uint32_t artIsAssignableFromCode(const mirror::Class* klass, + const mirror::Class* ref_class); +// Math entrypoints. +extern int32_t CmpgDouble(double a, double b); +extern int32_t CmplDouble(double a, double b); +extern int32_t CmpgFloat(float a, float b); +extern int32_t CmplFloat(float a, float b); +extern "C" int64_t artLmul(int64_t a, int64_t b); +extern "C" int64_t artLdiv(int64_t a, int64_t b); +extern "C" int64_t artLmod(int64_t a, int64_t b); + +// Math conversions. +extern "C" int32_t __fixsfsi(float op1); // FLOAT_TO_INT +extern "C" int32_t __fixdfsi(double op1); // DOUBLE_TO_INT +extern "C" float __floatdisf(int64_t op1); // LONG_TO_FLOAT +extern "C" double __floatdidf(int64_t op1); // LONG_TO_DOUBLE +extern "C" int64_t __fixsfdi(float op1); // FLOAT_TO_LONG +extern "C" int64_t __fixdfdi(double op1); // DOUBLE_TO_LONG + +// Single-precision FP arithmetics. +extern "C" float fmodf(float a, float b); // REM_FLOAT[_2ADDR] + +// Double-precision FP arithmetics. +extern "C" double fmod(double a, double b); // REM_DOUBLE[_2ADDR] + +// Long long arithmetics - REM_LONG[_2ADDR] and DIV_LONG[_2ADDR] +extern "C" int64_t __divdi3(int64_t, int64_t); +extern "C" int64_t __moddi3(int64_t, int64_t); + +void InitEntryPoints(InterpreterEntryPoints* ipoints, JniEntryPoints* jpoints, + QuickEntryPoints* qpoints) { + // Interpreter + ipoints->pInterpreterToInterpreterBridge = artInterpreterToInterpreterBridge; + ipoints->pInterpreterToCompiledCodeBridge = artInterpreterToCompiledCodeBridge; + + // JNI + jpoints->pDlsymLookup = art_jni_dlsym_lookup_stub; + + // Alloc + ResetQuickAllocEntryPoints(qpoints); + + // Cast + qpoints->pInstanceofNonTrivial = artIsAssignableFromCode; + qpoints->pCheckCast = art_quick_check_cast; + + // DexCache + qpoints->pInitializeStaticStorage = art_quick_initialize_static_storage; + qpoints->pInitializeTypeAndVerifyAccess = art_quick_initialize_type_and_verify_access; + qpoints->pInitializeType = art_quick_initialize_type; + qpoints->pResolveString = art_quick_resolve_string; + + // Field + qpoints->pSet8Instance = art_quick_set8_instance; + qpoints->pSet8Static = art_quick_set8_static; + qpoints->pSet16Instance = art_quick_set16_instance; + qpoints->pSet16Static = art_quick_set16_static; + qpoints->pSet32Instance = art_quick_set32_instance; + qpoints->pSet32Static = art_quick_set32_static; + qpoints->pSet64Instance = art_quick_set64_instance; + qpoints->pSet64Static = art_quick_set64_static; + qpoints->pSetObjInstance = art_quick_set_obj_instance; + qpoints->pSetObjStatic = art_quick_set_obj_static; + qpoints->pGetBooleanInstance = art_quick_get_boolean_instance; + qpoints->pGetByteInstance = art_quick_get_byte_instance; + qpoints->pGetCharInstance = art_quick_get_char_instance; + qpoints->pGetShortInstance = art_quick_get_short_instance; + qpoints->pGet32Instance = art_quick_get32_instance; + qpoints->pGet64Instance = art_quick_get64_instance; + qpoints->pGetObjInstance = art_quick_get_obj_instance; + qpoints->pGetBooleanStatic = art_quick_get_boolean_static; + qpoints->pGetByteStatic = art_quick_get_byte_static; + qpoints->pGetCharStatic = art_quick_get_char_static; + qpoints->pGetShortStatic = art_quick_get_short_static; + qpoints->pGet32Static = art_quick_get32_static; + qpoints->pGet64Static = art_quick_get64_static; + qpoints->pGetObjStatic = art_quick_get_obj_static; + + // Array + qpoints->pAputObjectWithNullAndBoundCheck = art_quick_aput_obj_with_null_and_bound_check; + qpoints->pAputObjectWithBoundCheck = art_quick_aput_obj_with_bound_check; + qpoints->pAputObject = art_quick_aput_obj; + qpoints->pHandleFillArrayData = art_quick_handle_fill_data; + + // JNI + qpoints->pJniMethodStart = JniMethodStart; + qpoints->pJniMethodStartSynchronized = JniMethodStartSynchronized; + qpoints->pJniMethodEnd = JniMethodEnd; + qpoints->pJniMethodEndSynchronized = JniMethodEndSynchronized; + qpoints->pJniMethodEndWithReference = JniMethodEndWithReference; + qpoints->pJniMethodEndWithReferenceSynchronized = JniMethodEndWithReferenceSynchronized; + qpoints->pQuickGenericJniTrampoline = art_quick_generic_jni_trampoline; + + // Locks + qpoints->pLockObject = art_quick_lock_object; + qpoints->pUnlockObject = art_quick_unlock_object; + + // Math + qpoints->pCmpgDouble = CmpgDouble; + qpoints->pCmpgFloat = CmpgFloat; + qpoints->pCmplDouble = CmplDouble; + qpoints->pCmplFloat = CmplFloat; + qpoints->pFmod = fmod; + qpoints->pL2d = art_l2d; + qpoints->pFmodf = fmodf; + qpoints->pL2f = art_l2f; + qpoints->pD2iz = art_d2i; + qpoints->pF2iz = art_f2i; + qpoints->pIdivmod = NULL; + qpoints->pD2l = art_d2l; + qpoints->pF2l = art_f2l; + qpoints->pLdiv = artLdiv; + qpoints->pLmod = artLmod; + qpoints->pLmul = artLmul; + qpoints->pShlLong = NULL; + qpoints->pShrLong = NULL; + qpoints->pUshrLong = NULL; + + // Intrinsics + qpoints->pIndexOf = art_quick_indexof; + qpoints->pStringCompareTo = art_quick_string_compareto; + qpoints->pMemcpy = memcpy; + + // Invocation + qpoints->pQuickImtConflictTrampoline = art_quick_imt_conflict_trampoline; + qpoints->pQuickResolutionTrampoline = art_quick_resolution_trampoline; + qpoints->pQuickToInterpreterBridge = art_quick_to_interpreter_bridge; + qpoints->pInvokeDirectTrampolineWithAccessCheck = art_quick_invoke_direct_trampoline_with_access_check; + qpoints->pInvokeInterfaceTrampolineWithAccessCheck = art_quick_invoke_interface_trampoline_with_access_check; + qpoints->pInvokeStaticTrampolineWithAccessCheck = art_quick_invoke_static_trampoline_with_access_check; + qpoints->pInvokeSuperTrampolineWithAccessCheck = art_quick_invoke_super_trampoline_with_access_check; + qpoints->pInvokeVirtualTrampolineWithAccessCheck = art_quick_invoke_virtual_trampoline_with_access_check; + + // Thread + qpoints->pTestSuspend = art_quick_test_suspend; + + // Throws + qpoints->pDeliverException = art_quick_deliver_exception; + qpoints->pThrowArrayBounds = art_quick_throw_array_bounds; + qpoints->pThrowDivZero = art_quick_throw_div_zero; + qpoints->pThrowNoSuchMethod = art_quick_throw_no_such_method; + qpoints->pThrowNullPointer = art_quick_throw_null_pointer_exception; + qpoints->pThrowStackOverflow = art_quick_throw_stack_overflow; + + // TODO - use lld/scd instructions for Mips64 + // Atomic 64-bit load/store + qpoints->pA64Load = QuasiAtomic::Read64; + qpoints->pA64Store = QuasiAtomic::Write64; +}; + +} // namespace art diff --git a/runtime/arch/mips64/fault_handler_mips64.cc b/runtime/arch/mips64/fault_handler_mips64.cc new file mode 100644 index 0000000000..7b5cd4913c --- /dev/null +++ b/runtime/arch/mips64/fault_handler_mips64.cc @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + + +#include "fault_handler.h" +#include <sys/ucontext.h> +#include "base/macros.h" +#include "globals.h" +#include "base/logging.h" +#include "base/hex_dump.h" + + +// +// Mips64 specific fault handler functions. +// + +namespace art { + +void FaultManager::HandleNestedSignal(int sig ATTRIBUTE_UNUSED, siginfo_t* info ATTRIBUTE_UNUSED, + void* context ATTRIBUTE_UNUSED) { +} + +void FaultManager::GetMethodAndReturnPcAndSp(siginfo_t* siginfo ATTRIBUTE_UNUSED, + void* context ATTRIBUTE_UNUSED, + mirror::ArtMethod** out_method ATTRIBUTE_UNUSED, + uintptr_t* out_return_pc ATTRIBUTE_UNUSED, + uintptr_t* out_sp ATTRIBUTE_UNUSED) { +} + +bool NullPointerHandler::Action(int sig ATTRIBUTE_UNUSED, siginfo_t* info ATTRIBUTE_UNUSED, + void* context ATTRIBUTE_UNUSED) { + return false; +} + +bool SuspensionHandler::Action(int sig ATTRIBUTE_UNUSED, siginfo_t* info ATTRIBUTE_UNUSED, + void* context ATTRIBUTE_UNUSED) { + return false; +} + +bool StackOverflowHandler::Action(int sig ATTRIBUTE_UNUSED, siginfo_t* info ATTRIBUTE_UNUSED, + void* context ATTRIBUTE_UNUSED) { + return false; +} +} // namespace art diff --git a/runtime/arch/mips64/instruction_set_features_mips64.cc b/runtime/arch/mips64/instruction_set_features_mips64.cc new file mode 100644 index 0000000000..26478cbeef --- /dev/null +++ b/runtime/arch/mips64/instruction_set_features_mips64.cc @@ -0,0 +1,116 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "instruction_set_features_mips64.h" + +#include <fstream> +#include <sstream> + +#include "base/stringprintf.h" +#include "utils.h" // For Trim. + +namespace art { + +const Mips64InstructionSetFeatures* Mips64InstructionSetFeatures::FromVariant( + const std::string& variant, std::string* error_msg ATTRIBUTE_UNUSED) { + // TODO: r6 variant. + if (variant != "default") { + std::ostringstream os; + LOG(WARNING) << "Unexpected CPU variant for Mips64 using defaults: " << variant; + } + bool smp = true; // Conservative default. + return new Mips64InstructionSetFeatures(smp); +} + +const Mips64InstructionSetFeatures* Mips64InstructionSetFeatures::FromBitmap(uint32_t bitmap) { + bool smp = (bitmap & kSmpBitfield) != 0; + return new Mips64InstructionSetFeatures(smp); +} + +const Mips64InstructionSetFeatures* Mips64InstructionSetFeatures::FromCppDefines() { + const bool smp = true; + + return new Mips64InstructionSetFeatures(smp); +} + +const Mips64InstructionSetFeatures* Mips64InstructionSetFeatures::FromCpuInfo() { + // Look in /proc/cpuinfo for features we need. Only use this when we can guarantee that + // the kernel puts the appropriate feature flags in here. Sometimes it doesn't. + bool smp = false; + + std::ifstream in("/proc/cpuinfo"); + if (!in.fail()) { + while (!in.eof()) { + std::string line; + std::getline(in, line); + if (!in.eof()) { + LOG(INFO) << "cpuinfo line: " << line; + if (line.find("processor") != std::string::npos && line.find(": 1") != std::string::npos) { + smp = true; + } + } + } + in.close(); + } else { + LOG(ERROR) << "Failed to open /proc/cpuinfo"; + } + return new Mips64InstructionSetFeatures(smp); +} + +const Mips64InstructionSetFeatures* Mips64InstructionSetFeatures::FromHwcap() { + UNIMPLEMENTED(WARNING); + return FromCppDefines(); +} + +const Mips64InstructionSetFeatures* Mips64InstructionSetFeatures::FromAssembly() { + UNIMPLEMENTED(WARNING); + return FromCppDefines(); +} + +bool Mips64InstructionSetFeatures::Equals(const InstructionSetFeatures* other) const { + if (kMips64 != other->GetInstructionSet()) { + return false; + } + return (IsSmp() == other->IsSmp()); +} + +uint32_t Mips64InstructionSetFeatures::AsBitmap() const { + return (IsSmp() ? kSmpBitfield : 0); +} + +std::string Mips64InstructionSetFeatures::GetFeatureString() const { + std::string result; + if (IsSmp()) { + result += "smp"; + } else { + result += "-smp"; + } + return result; +} + +const InstructionSetFeatures* Mips64InstructionSetFeatures::AddFeaturesFromSplitString( + const bool smp, const std::vector<std::string>& features, std::string* error_msg) const { + auto i = features.begin(); + if (i != features.end()) { + // We don't have any features. + std::string feature = Trim(*i); + *error_msg = StringPrintf("Unknown instruction set feature: '%s'", feature.c_str()); + return nullptr; + } + return new Mips64InstructionSetFeatures(smp); +} + +} // namespace art diff --git a/runtime/arch/mips64/instruction_set_features_mips64.h b/runtime/arch/mips64/instruction_set_features_mips64.h new file mode 100644 index 0000000000..d5d6012007 --- /dev/null +++ b/runtime/arch/mips64/instruction_set_features_mips64.h @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_INSTRUCTION_SET_FEATURES_MIPS64_H_ +#define ART_RUNTIME_ARCH_MIPS64_INSTRUCTION_SET_FEATURES_MIPS64_H_ + +#include "arch/instruction_set_features.h" + +namespace art { + +// Instruction set features relevant to the MIPS64 architecture. +class Mips64InstructionSetFeatures FINAL : public InstructionSetFeatures { + public: + // Process a CPU variant string like "r4000" and create InstructionSetFeatures. + static const Mips64InstructionSetFeatures* FromVariant(const std::string& variant, + std::string* error_msg); + + // Parse a bitmap and create an InstructionSetFeatures. + static const Mips64InstructionSetFeatures* FromBitmap(uint32_t bitmap); + + // Turn C pre-processor #defines into the equivalent instruction set features. + static const Mips64InstructionSetFeatures* FromCppDefines(); + + // Process /proc/cpuinfo and use kRuntimeISA to produce InstructionSetFeatures. + static const Mips64InstructionSetFeatures* FromCpuInfo(); + + // Process the auxiliary vector AT_HWCAP entry and use kRuntimeISA to produce + // InstructionSetFeatures. + static const Mips64InstructionSetFeatures* FromHwcap(); + + // Use assembly tests of the current runtime (ie kRuntimeISA) to determine the + // InstructionSetFeatures. This works around kernel bugs in AT_HWCAP and /proc/cpuinfo. + static const Mips64InstructionSetFeatures* FromAssembly(); + + bool Equals(const InstructionSetFeatures* other) const OVERRIDE; + + InstructionSet GetInstructionSet() const OVERRIDE { + return kMips64; + } + + uint32_t AsBitmap() const OVERRIDE; + + std::string GetFeatureString() const OVERRIDE; + + virtual ~Mips64InstructionSetFeatures() {} + + protected: + // Parse a vector of the form "fpu32", "mips2" adding these to a new Mips64InstructionSetFeatures. + virtual const InstructionSetFeatures* + AddFeaturesFromSplitString(const bool smp, const std::vector<std::string>& features, + std::string* error_msg) const OVERRIDE; + + private: + explicit Mips64InstructionSetFeatures(bool smp) : InstructionSetFeatures(smp) { + } + + // Bitmap positions for encoding features as a bitmap. + enum { + kSmpBitfield = 1, + }; + + DISALLOW_COPY_AND_ASSIGN(Mips64InstructionSetFeatures); +}; + +} // namespace art + +#endif // ART_RUNTIME_ARCH_MIPS64_INSTRUCTION_SET_FEATURES_MIPS64_H_ diff --git a/runtime/arch/mips64/instruction_set_features_mips64_test.cc b/runtime/arch/mips64/instruction_set_features_mips64_test.cc new file mode 100644 index 0000000000..dc3450677b --- /dev/null +++ b/runtime/arch/mips64/instruction_set_features_mips64_test.cc @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "instruction_set_features_mips64.h" + +#include <gtest/gtest.h> + +namespace art { + +TEST(Mips64InstructionSetFeaturesTest, Mips64Features) { + std::string error_msg; + std::unique_ptr<const InstructionSetFeatures> mips64_features( + InstructionSetFeatures::FromVariant(kMips64, "default", &error_msg)); + ASSERT_TRUE(mips64_features.get() != nullptr) << error_msg; + EXPECT_EQ(mips64_features->GetInstructionSet(), kMips64); + EXPECT_TRUE(mips64_features->Equals(mips64_features.get())); + EXPECT_STREQ("smp", mips64_features->GetFeatureString().c_str()); + EXPECT_EQ(mips64_features->AsBitmap(), 1U); +} + +} // namespace art diff --git a/runtime/arch/mips64/jni_entrypoints_mips64.S b/runtime/arch/mips64/jni_entrypoints_mips64.S new file mode 100644 index 0000000000..90fd3ee63e --- /dev/null +++ b/runtime/arch/mips64/jni_entrypoints_mips64.S @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "asm_support_mips64.S" + + .set noreorder + .balign 16 + + /* + * Jni dlsym lookup stub. + */ + .extern artFindNativeMethod +ENTRY art_jni_dlsym_lookup_stub + daddiu $sp, $sp, -80 # save a0-a7 and $ra + .cfi_adjust_cfa_offset 80 + sd $ra, 64($sp) + .cfi_rel_offset 31, 64 + sw $a7, 56($sp) + .cfi_rel_offset 11, 56 + sw $a6, 48($sp) + .cfi_rel_offset 10, 48 + sw $a5, 40($sp) + .cfi_rel_offset 9, 40 + sw $a4, 32($sp) + .cfi_rel_offset 8, 32 + sw $a3, 24($sp) + .cfi_rel_offset 7, 24 + sw $a2, 16($sp) + .cfi_rel_offset 6, 16 + sw $a1, 8($sp) + .cfi_rel_offset 5, 8 + sw $a0, 0($sp) + .cfi_rel_offset 4, 0 + jal artFindNativeMethod # (Thread*) + move $a0, $s1 # pass Thread::Current() + ld $a0, 0($sp) # restore registers from stack + .cfi_restore 4 + ld $a1, 8($sp) + .cfi_restore 5 + ld $a2, 16($sp) + .cfi_restore 6 + ld $a3, 24($sp) + .cfi_restore 7 + ld $a4, 32($sp) + .cfi_restore 8 + ld $a5, 40($sp) + .cfi_restore 9 + ld $a6, 48($sp) + .cfi_restore 10 + ld $a7, 56($sp) + .cfi_restore 11 + ld $ra, 64($sp) + .cfi_restore 31 + beq $v0, $zero, .Lno_native_code_found + daddiu $sp, $sp, 80 # restore the stack + .cfi_adjust_cfa_offset -80 + move $t9, $v0 # put method code result in $t9 + jalr $zero, $t9 # leaf call to method's code + nop +.Lno_native_code_found: + jalr $zero, $ra + nop +END art_jni_dlsym_lookup_stub diff --git a/runtime/arch/mips64/memcmp16_mips64.S b/runtime/arch/mips64/memcmp16_mips64.S new file mode 100644 index 0000000000..962977ee13 --- /dev/null +++ b/runtime/arch/mips64/memcmp16_mips64.S @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_MEMCMP16_MIPS64_S_ +#define ART_RUNTIME_ARCH_MIPS64_MEMCMP16_MIPS64_S_ + +#include "asm_support_mips64.S" + +.set noreorder + +// u4 __memcmp16(const u2*, const u2*, size_t); +ENTRY_NO_GP __memcmp16 + move $t0, $zero + move $t1, $zero + beqz $a2, done /* 0 length string */ + nop + beq $a0, $a1, done /* addresses are identical */ + nop + +1: + lhu $t0, 0($a0) + lhu $t1, 0($a1) + bne $t0, $t1, done + nop + daddu $a0, 2 + daddu $a1, 2 + dsubu $a2, 1 + bnez $a2, 1b + nop + +done: + dsubu $v0, $t0, $t1 + j $ra + nop +END __memcmp16 + +#endif // ART_RUNTIME_ARCH_MIPS64_MEMCMP16_MIPS64_S_ diff --git a/runtime/arch/mips64/quick_entrypoints_mips64.S b/runtime/arch/mips64/quick_entrypoints_mips64.S new file mode 100644 index 0000000000..3430eb5e3b --- /dev/null +++ b/runtime/arch/mips64/quick_entrypoints_mips64.S @@ -0,0 +1,897 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "asm_support_mips64.S" + +#include "arch/quick_alloc_entrypoints.S" + + .set noreorder + .balign 16 + + /* Deliver the given exception */ + .extern artDeliverExceptionFromCode + /* Deliver an exception pending on a thread */ + .extern artDeliverPendingExceptionFromCode + + /* + * Macro that sets up the callee save frame to conform with + * Runtime::CreateCalleeSaveMethod(kSaveAll) + * callee-save: padding + $f24-$f31 + $s0-$s7 + $gp + $ra + $s8 = 19 total + 1x8 bytes padding + */ +.macro SETUP_SAVE_ALL_CALLEE_SAVE_FRAME + daddiu $sp, $sp, -160 + .cfi_adjust_cfa_offset 160 + + // Ugly compile-time check, but we only have the preprocessor. +#if (FRAME_SIZE_SAVE_ALL_CALLEE_SAVE != 160) +#error "SAVE_ALL_CALLEE_SAVE_FRAME(MIPS64) size not as expected." +#endif + + sd $ra, 152($sp) + .cfi_rel_offset 31, 152 + sd $s8, 144($sp) + .cfi_rel_offset 30, 144 + sd $gp, 136($sp) + .cfi_rel_offset 28, 136 + sd $s7, 128($sp) + .cfi_rel_offset 23, 128 + sd $s6, 120($sp) + .cfi_rel_offset 22, 120 + sd $s5, 112($sp) + .cfi_rel_offset 21, 112 + sd $s4, 104($sp) + .cfi_rel_offset 20, 104 + sd $s3, 96($sp) + .cfi_rel_offset 19, 96 + sd $s2, 88($sp) + .cfi_rel_offset 18, 88 + sd $s1, 80($sp) + .cfi_rel_offset 17, 80 + sd $s0, 72($sp) + .cfi_rel_offset 16, 72 + + // FP callee-saves + s.d $f31, 64($sp) + s.d $f30, 56($sp) + s.d $f29, 48($sp) + s.d $f28, 40($sp) + s.d $f27, 32($sp) + s.d $f26, 24($sp) + s.d $f25, 16($sp) + s.d $f24, 8($sp) + + # load appropriate callee-save-method + ld $v0, %got(_ZN3art7Runtime9instance_E)($gp) + ld $v0, 0($v0) + THIS_LOAD_REQUIRES_READ_BARRIER + ld $v0, RUNTIME_SAVE_ALL_CALLEE_SAVE_FRAME_OFFSET($v0) + sw $v0, 0($sp) # Place Method* at bottom of stack. + sd $sp, THREAD_TOP_QUICK_FRAME_OFFSET(rSELF) # Place sp in Thread::Current()->top_quick_frame. +.endm + + /* + * Macro that sets up the callee save frame to conform with + * Runtime::CreateCalleeSaveMethod(kRefsOnly). Restoration assumes + * non-moving GC. + * Does not include rSUSPEND or rSELF + * callee-save: padding + $s2-$s7 + $gp + $ra + $s8 = 9 total + 1x8 bytes padding + */ +.macro SETUP_REFS_ONLY_CALLEE_SAVE_FRAME + daddiu $sp, $sp, -80 + .cfi_adjust_cfa_offset 80 + + // Ugly compile-time check, but we only have the preprocessor. +#if (FRAME_SIZE_REFS_ONLY_CALLEE_SAVE != 80) +#error "REFS_ONLY_CALLEE_SAVE_FRAME(MIPS64) size not as expected." +#endif + + sd $ra, 72($sp) + .cfi_rel_offset 31, 72 + sd $s8, 64($sp) + .cfi_rel_offset 30, 64 + sd $gp, 56($sp) + .cfi_rel_offset 28, 56 + sd $s7, 48($sp) + .cfi_rel_offset 23, 48 + sd $s6, 40($sp) + .cfi_rel_offset 22, 40 + sd $s5, 32($sp) + .cfi_rel_offset 21, 32 + sd $s4, 24($sp) + .cfi_rel_offset 20, 24 + sd $s3, 16($sp) + .cfi_rel_offset 19, 16 + sd $s2, 8($sp) + .cfi_rel_offset 18, 8 + # load appropriate callee-save-method + ld $v0, %got(_ZN3art7Runtime9instance_E)($gp) + ld $v0, 0($v0) + THIS_LOAD_REQUIRES_READ_BARRIER + ld $v0, RUNTIME_REFS_ONLY_CALLEE_SAVE_FRAME_OFFSET($v0) + sw $v0, 0($sp) # Place Method* at bottom of stack. + sd $sp, THREAD_TOP_QUICK_FRAME_OFFSET(rSELF) # Place sp in Thread::Current()->top_quick_frame. +.endm + +.macro RESTORE_REFS_ONLY_CALLEE_SAVE_FRAME + ld $ra, 72($sp) + .cfi_restore 31 + ld $s8, 64($sp) + .cfi_restore 30 + ld $gp, 56($sp) + .cfi_restore 28 + ld $s7, 48($sp) + .cfi_restore 23 + ld $s6, 40($sp) + .cfi_restore 22 + ld $s5, 32($sp) + .cfi_restore 21 + ld $s4, 24($sp) + .cfi_restore 20 + ld $s3, 16($sp) + .cfi_restore 19 + ld $s2, 8($sp) + .cfi_restore 18 + daddiu $sp, $sp, 80 + .cfi_adjust_cfa_offset -80 +.endm + +.macro RESTORE_REFS_ONLY_CALLEE_SAVE_FRAME_AND_RETURN + ld $ra, 72($sp) + .cfi_restore 31 + ld $s8, 64($sp) + .cfi_restore 30 + ld $gp, 56($sp) + .cfi_restore 28 + ld $s7, 48($sp) + .cfi_restore 23 + ld $s6, 40($sp) + .cfi_restore 22 + ld $s5, 32($sp) + .cfi_restore 21 + ld $s4, 24($sp) + .cfi_restore 20 + ld $s3, 16($sp) + .cfi_restore 19 + ld $s2, 8($sp) + .cfi_restore 18 + jalr $zero, $ra + daddiu $sp, $sp, 80 + .cfi_adjust_cfa_offset -80 +.endm + +// This assumes the top part of these stack frame types are identical. +#define REFS_AND_ARGS_MINUS_REFS_SIZE (FRAME_SIZE_REFS_AND_ARGS_CALLEE_SAVE - FRAME_SIZE_REFS_ONLY_CALLEE_SAVE) + + /* + * Macro that sets up the callee save frame to conform with + * Runtime::CreateCalleeSaveMethod(kRefsAndArgs). Restoration assumes + * non-moving GC. + * callee-save: padding + $f12-$f19 + $a1-$a7 + $s2-$s7 + $gp + $ra + $s8 = 24 total + 1 words padding + Method* + */ +.macro SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME_INTERNAL + daddiu $sp, $sp, -208 + .cfi_adjust_cfa_offset 208 + + // Ugly compile-time check, but we only have the preprocessor. +#if (FRAME_SIZE_REFS_AND_ARGS_CALLEE_SAVE != 208) +#error "REFS_AND_ARGS_CALLEE_SAVE_FRAME(MIPS64) size not as expected." +#endif + + sd $ra, 200($sp) # = kQuickCalleeSaveFrame_RefAndArgs_LrOffset + .cfi_rel_offset 31, 200 + sd $s8, 192($sp) + .cfi_rel_offset 30, 192 + sd $gp, 184($sp) + .cfi_rel_offset 28, 184 + sd $s7, 176($sp) + .cfi_rel_offset 23, 176 + sd $s6, 168($sp) + .cfi_rel_offset 22, 168 + sd $s5, 160($sp) + .cfi_rel_offset 21, 160 + sd $s4, 152($sp) + .cfi_rel_offset 20, 152 + sd $s3, 144($sp) + .cfi_rel_offset 19, 144 + sd $s2, 136($sp) + .cfi_rel_offset 18, 136 + + sd $a7, 128($sp) + .cfi_rel_offset 11, 128 + sd $a6, 120($sp) + .cfi_rel_offset 10, 120 + sd $a5, 112($sp) + .cfi_rel_offset 9, 112 + sd $a4, 104($sp) + .cfi_rel_offset 8, 104 + sd $a3, 96($sp) + .cfi_rel_offset 7, 96 + sd $a2, 88($sp) + .cfi_rel_offset 6, 88 + sd $a1, 80($sp) # = kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset + .cfi_rel_offset 5, 80 + + s.d $f19, 72($sp) + s.d $f18, 64($sp) + s.d $f17, 56($sp) + s.d $f16, 48($sp) + s.d $f15, 40($sp) + s.d $f14, 32($sp) + s.d $f13, 24($sp) # = kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset + s.d $f12, 16($sp) # This isn't necessary to store. + + # 1x8 bytes paddig + Method* + ld $v0, %got(_ZN3art7Runtime9instance_E)($gp) + ld $v0, 0($v0) + THIS_LOAD_REQUIRES_READ_BARRIER + ld $v0, RUNTIME_REFS_ONLY_CALLEE_SAVE_FRAME_OFFSET($v0) + sw $v0, 0($sp) # Place Method* at bottom of stack. + sd $sp, THREAD_TOP_QUICK_FRAME_OFFSET(rSELF) # Place sp in Thread::Current()->top_quick_frame. +.endm + +.macro SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME + SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME_INTERNAL + # load appropriate callee-save-method + ld $v0, %got(_ZN3art7Runtime9instance_E)($gp) + ld $v0, 0($v0) + THIS_LOAD_REQUIRES_READ_BARRIER + ld $v0, RUNTIME_REFS_AND_ARGS_CALLEE_SAVE_FRAME_OFFSET($v0) + sw $v0, 0($sp) # Place Method* at bottom of stack. + sd $sp, THREAD_TOP_QUICK_FRAME_OFFSET(rSELF) # Place sp in Thread::Current()->top_quick_frame. +.endm + +.macro RESTORE_REFS_AND_ARGS_CALLEE_SAVE_FRAME + ld $ra, 200($sp) + .cfi_restore 31 + ld $s8, 192($sp) + .cfi_restore 30 + ld $gp, 184($sp) + .cfi_restore 28 + ld $s7, 176($sp) + .cfi_restore 23 + ld $s6, 168($sp) + .cfi_restore 22 + ld $s5, 160($sp) + .cfi_restore 21 + ld $s4, 152($sp) + .cfi_restore 20 + ld $s3, 144($sp) + .cfi_restore 19 + ld $s2, 136($sp) + .cfi_restore 18 + + ld $a7, 128($sp) + .cfi_restore 11 + ld $a6, 120($sp) + .cfi_restore 10 + ld $a5, 112($sp) + .cfi_restore 9 + ld $a4, 104($sp) + .cfi_restore 8 + ld $a3, 96($sp) + .cfi_restore 7 + ld $a2, 88($sp) + .cfi_restore 6 + ld $a1, 80($sp) + .cfi_restore 5 + + l.d $f19, 72($sp) + l.d $f18, 64($sp) + l.d $f17, 56($sp) + l.d $f16, 48($sp) + l.d $f15, 40($sp) + l.d $f14, 32($sp) + l.d $f13, 24($sp) + l.d $f12, 16($sp) + + daddiu $sp, $sp, 208 + .cfi_adjust_cfa_offset -208 +.endm + + /* + * Macro that set calls through to artDeliverPendingExceptionFromCode, + * where the pending + * exception is Thread::Current()->exception_ + */ +.macro DELIVER_PENDING_EXCEPTION + SETUP_SAVE_ALL_CALLEE_SAVE_FRAME # save callee saves for throw + dla $t9, artDeliverPendingExceptionFromCode + jalr $zero, $t9 # artDeliverPendingExceptionFromCode(Thread*) + move $a0, rSELF # pass Thread::Current +.endm + +.macro RETURN_IF_NO_EXCEPTION + ld $t0, THREAD_EXCEPTION_OFFSET(rSELF) # load Thread::Current()->exception_ + RESTORE_REFS_ONLY_CALLEE_SAVE_FRAME + bne $t0, $zero, 1f # success if no exception is pending + nop + jalr $zero, $ra + nop +1: + DELIVER_PENDING_EXCEPTION +.endm + +.macro RETURN_IF_ZERO + RESTORE_REFS_ONLY_CALLEE_SAVE_FRAME + bne $v0, $zero, 1f # success? + nop + jalr $zero, $ra # return on success + nop +1: + DELIVER_PENDING_EXCEPTION +.endm + +.macro RETURN_IF_RESULT_IS_NON_ZERO_OR_DELIVER + RESTORE_REFS_ONLY_CALLEE_SAVE_FRAME + beq $v0, $zero, 1f # success? + nop + jalr $zero, $ra # return on success + nop +1: + DELIVER_PENDING_EXCEPTION +.endm + + /* + * On entry $a0 is uint32_t* gprs_ and $a1 is uint32_t* fprs_ + * FIXME: just guessing about the shape of the jmpbuf. Where will pc be? + */ +ENTRY art_quick_do_long_jump + l.d $f0, 0($a1) + l.d $f1, 8($a1) + l.d $f2, 16($a1) + l.d $f3, 24($a1) + l.d $f4, 32($a1) + l.d $f5, 40($a1) + l.d $f6, 48($a1) + l.d $f7, 56($a1) + l.d $f8, 64($a1) + l.d $f9, 72($a1) + l.d $f10, 80($a1) + l.d $f11, 88($a1) + l.d $f12, 96($a1) + l.d $f13, 104($a1) + l.d $f14, 112($a1) + l.d $f15, 120($a1) + l.d $f16, 128($a1) + l.d $f17, 136($a1) + l.d $f18, 144($a1) + l.d $f19, 152($a1) + l.d $f20, 160($a1) + l.d $f21, 168($a1) + l.d $f22, 176($a1) + l.d $f23, 184($a1) + l.d $f24, 192($a1) + l.d $f25, 200($a1) + l.d $f26, 208($a1) + l.d $f27, 216($a1) + l.d $f28, 224($a1) + l.d $f29, 232($a1) + l.d $f30, 240($a1) + l.d $f31, 248($a1) + .set push + .set nomacro + .set noat +# no need to load zero + ld $at, 8($a0) + .set pop + ld $v0, 16($a0) + ld $v1, 24($a0) +# a0 has to be loaded last + ld $a1, 40($a0) + ld $a2, 48($a0) + ld $a3, 56($a0) + ld $a4, 64($a0) + ld $a5, 72($a0) + ld $a6, 80($a0) + ld $a7, 88($a0) + ld $t0, 96($a0) + ld $t1, 104($a0) + ld $t2, 112($a0) + ld $t3, 120($a0) + ld $s0, 128($a0) + ld $s1, 136($a0) + ld $s2, 144($a0) + ld $s3, 152($a0) + ld $s4, 160($a0) + ld $s5, 168($a0) + ld $s6, 176($a0) + ld $s7, 184($a0) + ld $t8, 192($a0) + ld $t9, 200($a0) +# no need to load k0, k1 + ld $gp, 224($a0) + ld $sp, 232($a0) + ld $s8, 240($a0) + ld $ra, 248($a0) + ld $a0, 32($a0) + move $v0, $zero # clear result registers v0 and v1 + jalr $zero, $ra # do long jump + move $v1, $zero +END art_quick_do_long_jump + +UNIMPLEMENTED art_quick_deliver_exception +UNIMPLEMENTED art_quick_throw_null_pointer_exception +UNIMPLEMENTED art_quick_throw_div_zero +UNIMPLEMENTED art_quick_throw_array_bounds +UNIMPLEMENTED art_quick_throw_stack_overflow +UNIMPLEMENTED art_quick_throw_no_such_method + +UNIMPLEMENTED art_quick_invoke_interface_trampoline +UNIMPLEMENTED art_quick_invoke_interface_trampoline_with_access_check + +UNIMPLEMENTED art_quick_invoke_static_trampoline_with_access_check +UNIMPLEMENTED art_quick_invoke_direct_trampoline_with_access_check +UNIMPLEMENTED art_quick_invoke_super_trampoline_with_access_check +UNIMPLEMENTED art_quick_invoke_virtual_trampoline_with_access_check + + # On entry: + # t0 = shorty + # t1 = ptr to arg_array + # t2 = number of argument bytes remain + # v0 = ptr to stack frame where to copy arg_array + # This macro modifies t3, t9 and v0 +.macro LOOP_OVER_SHORTY_LOADING_REG gpu, fpu, label + lbu $t3, 0($t0) # get argument type from shorty + beqz $t3, \label + daddiu $t0, 1 + li $t9, 68 # put char 'D' into t9 + beq $t9, $t3, 1f # branch if result type char == 'D' + li $t9, 70 # put char 'F' into t9 + beq $t9, $t3, 2f # branch if result type char == 'F' + li $t9, 74 # put char 'J' into t9 + beq $t9, $t3, 3f # branch if result type char == 'J' + nop + lwu $\gpu, 0($t1) + sw $\gpu, 0($v0) + daddiu $v0, 4 + daddiu $t1, 4 + b 4f + daddiu $t2, -4 # delay slot + +1: # found double + lwu $t3, 0($t1) + mtc1 $t3, $\fpu + sw $t3, 0($v0) + lwu $t3, 4($t1) + mthc1 $t3, $\fpu + sw $t3, 4($v0) + daddiu $v0, 8 + daddiu $t1, 8 + b 4f + daddiu $t2, -8 # delay slot + +2: # found float + lwu $t3, 0($t1) + mtc1 $t3, $\fpu + sw $t3, 0($v0) + daddiu $v0, 4 + daddiu $t1, 4 + b 4f + daddiu $t2, -4 # delay slot + +3: # found long (8 bytes) + lwu $t3, 0($t1) + sw $t3, 0($v0) + lwu $t9, 4($t1) + sw $t9, 4($v0) + dsll $t9, $t9, 32 + or $\gpu, $t9, $t3 + daddiu $v0, 8 + daddiu $t1, 8 + daddiu $t2, -8 +4: +.endm + + /* + * Invocation stub for quick code. + * On entry: + * a0 = method pointer + * a1 = argument array that must at least contain the this ptr. + * a2 = size of argument array in bytes + * a3 = (managed) thread pointer + * a4 = JValue* result + * a5 = shorty + */ +ENTRY art_quick_invoke_stub + # push a4, a5, s0(rSUSPEND), s1(rSELF), s8, ra onto the stack + daddiu $sp, $sp, -48 + .cfi_adjust_cfa_offset 48 + sd $ra, 40($sp) + .cfi_rel_offset 31, 40 + sd $s8, 32($sp) + .cfi_rel_offset 30, 32 + sd $s1, 24($sp) + .cfi_rel_offset 17, 24 + sd $s0, 16($sp) + .cfi_rel_offset 16, 16 + sd $a5, 8($sp) + .cfi_rel_offset 9, 8 + sd $a4, 0($sp) + .cfi_rel_offset 8, 0 + + daddiu $s0, $zero, SUSPEND_CHECK_INTERVAL # reset rSUSPEND to SUSPEND_CHECK_INTERVAL + move $s1, $a3 # move managed thread pointer into s1 (rSELF) + move $s8, $sp # save sp in s8 (fp) + + daddiu $t3, $a2, 20 # add 4 for method* and 16 for stack alignment + dsrl $t3, $t3, 4 # shift the frame size right 4 + dsll $t3, $t3, 4 # shift the frame size left 4 to align to 16 bytes + dsubu $sp, $sp, $t3 # reserve stack space for argument array + + daddiu $t0, $a5, 1 # t0 = shorty[1] (skip 1 for return type) + daddiu $t1, $a1, 4 # t1 = ptr to arg_array[4] (skip this ptr) + daddiu $t2, $a2, -4 # t2 = number of argument bytes remain (skip this ptr) + daddiu $v0, $sp, 8 # v0 points to where to copy arg_array + LOOP_OVER_SHORTY_LOADING_REG a2, f14, call_fn + LOOP_OVER_SHORTY_LOADING_REG a3, f15, call_fn + LOOP_OVER_SHORTY_LOADING_REG a4, f16, call_fn + LOOP_OVER_SHORTY_LOADING_REG a5, f17, call_fn + LOOP_OVER_SHORTY_LOADING_REG a6, f18, call_fn + LOOP_OVER_SHORTY_LOADING_REG a7, f19, call_fn + + # copy arguments onto stack (t2 should be multiples of 4) + ble $t2, $zero, call_fn # t2 = number of argument bytes remain +1: + lw $t3, 0($t1) # load from argument array + daddiu $t1, $t1, 4 + sw $t3, 0($v0) # save to stack + daddiu $t2, -4 + bgt $t2, $zero, 1b # t2 = number of argument bytes remain + daddiu $v0, $v0, 4 + +call_fn: + # call method (a0 and a1 have been untouched) + lwu $a1, 0($a1) # make a1 = this ptr + sw $a1, 4($sp) # copy this ptr (skip 4 bytes for method*) + sw $zero, 0($sp) # store NULL for method* at bottom of frame + ld $t9, MIRROR_ART_METHOD_QUICK_CODE_OFFSET_64($a0) # get pointer to the code + jalr $t9 # call the method + nop + move $sp, $s8 # restore sp + + # pop a4, a5, s1(rSELF), s8, ra off of the stack + ld $a4, 0($sp) + .cfi_restore 8 + ld $a5, 8($sp) + .cfi_restore 9 + ld $s0, 16($sp) + .cfi_restore 16 + ld $s1, 24($sp) + .cfi_restore 17 + ld $s8, 32($sp) + .cfi_restore 30 + ld $ra, 40($sp) + .cfi_restore 31 + daddiu $sp, $sp, 48 + .cfi_adjust_cfa_offset -48 + + # a4 = JValue* result + # a5 = shorty string + lbu $t1, 0($a5) # get result type from shorty + li $t2, 68 # put char 'D' into t2 + beq $t1, $t2, 1f # branch if result type char == 'D' + li $t3, 70 # put char 'F' into t3 + beq $t1, $t3, 1f # branch if result type char == 'F' + sw $v0, 0($a4) # store the result + dsrl $v1, $v0, 32 + jalr $zero, $ra + sw $v1, 4($a4) # store the other half of the result +1: + mfc1 $v0, $f0 + mfhc1 $v1, $f0 + sw $v0, 0($a4) # store the result + jalr $zero, $ra + sw $v1, 4($a4) # store the other half of the result +END art_quick_invoke_stub + + /* + * Invocation static stub for quick code. + * On entry: + * a0 = method pointer + * a1 = argument array that must at least contain the this ptr. + * a2 = size of argument array in bytes + * a3 = (managed) thread pointer + * a4 = JValue* result + * a5 = shorty + */ +ENTRY art_quick_invoke_static_stub + + # push a4, a5, s0(rSUSPEND), s1(rSELF), s8, ra, onto the stack + daddiu $sp, $sp, -48 + .cfi_adjust_cfa_offset 48 + sd $ra, 40($sp) + .cfi_rel_offset 31, 40 + sd $s8, 32($sp) + .cfi_rel_offset 30, 32 + sd $s1, 24($sp) + .cfi_rel_offset 17, 24 + sd $s0, 16($sp) + .cfi_rel_offset 16, 16 + sd $a5, 8($sp) + .cfi_rel_offset 9, 8 + sd $a4, 0($sp) + .cfi_rel_offset 8, 0 + + daddiu $s0, $zero, SUSPEND_CHECK_INTERVAL # reset rSUSPEND to SUSPEND_CHECK_INTERVAL + move $s1, $a3 # move managed thread pointer into s1 (rSELF) + move $s8, $sp # save sp in s8 (fp) + + daddiu $t3, $a2, 20 # add 4 for method* and 16 for stack alignment + dsrl $t3, $t3, 4 # shift the frame size right 4 + dsll $t3, $t3, 4 # shift the frame size left 4 to align to 16 bytes + dsubu $sp, $sp, $t3 # reserve stack space for argument array + + daddiu $t0, $a5, 1 # t0 = shorty[1] (skip 1 for return type) + move $t1, $a1 # t1 = arg_array + move $t2, $a2 # t2 = number of argument bytes remain + daddiu $v0, $sp, 4 # v0 points to where to copy arg_array + LOOP_OVER_SHORTY_LOADING_REG a1, f13, call_sfn + LOOP_OVER_SHORTY_LOADING_REG a2, f14, call_sfn + LOOP_OVER_SHORTY_LOADING_REG a3, f15, call_sfn + LOOP_OVER_SHORTY_LOADING_REG a4, f16, call_sfn + LOOP_OVER_SHORTY_LOADING_REG a5, f17, call_sfn + LOOP_OVER_SHORTY_LOADING_REG a6, f18, call_sfn + LOOP_OVER_SHORTY_LOADING_REG a7, f19, call_sfn + + # copy arguments onto stack (t2 should be multiples of 4) + ble $t2, $zero, call_sfn # t2 = number of argument bytes remain +1: + lw $t3, 0($t1) # load from argument array + daddiu $t1, $t1, 4 + sw $t3, 0($v0) # save to stack + daddiu $t2, -4 + bgt $t2, $zero, 1b # t2 = number of argument bytes remain + daddiu $v0, $v0, 4 + +call_sfn: + # call method (a0 has been untouched) + sw $zero, 0($sp) # store NULL for method* at bottom of frame + ld $t9, MIRROR_ART_METHOD_QUICK_CODE_OFFSET_64($a0) # get pointer to the code + jalr $t9 # call the method + nop + move $sp, $s8 # restore sp + + # pop a4, a5, s0(rSUSPEND), s1(rSELF), s8, ra off of the stack + ld $a4, 0($sp) + .cfi_restore 8 + ld $a5, 8($sp) + .cfi_restore 9 + ld $s0, 16($sp) + .cfi_restore 16 + ld $s1, 24($sp) + .cfi_restore 17 + ld $s8, 32($sp) + .cfi_restore 30 + ld $ra, 40($sp) + .cfi_restore 31 + daddiu $sp, $sp, 48 + .cfi_adjust_cfa_offset -48 + + # a4 = JValue* result + # a5 = shorty string + lbu $t1, 0($a5) # get result type from shorty + li $t2, 68 # put char 'D' into t2 + beq $t1, $t2, 1f # branch if result type char == 'D' + li $t3, 70 # put char 'F' into t3 + beq $t1, $t3, 1f # branch if result type char == 'F' + sw $v0, 0($a4) # store the result + dsrl $v1, $v0, 32 + jalr $zero, $ra + sw $v1, 4($a4) # store the other half of the result +1: + mfc1 $v0, $f0 + mfhc1 $v1, $f0 + sw $v0, 0($a4) # store the result + jalr $zero, $ra + sw $v1, 4($a4) # store the other half of the result +END art_quick_invoke_static_stub + + + +UNIMPLEMENTED art_quick_handle_fill_data +UNIMPLEMENTED art_quick_lock_object +UNIMPLEMENTED art_quick_unlock_object +UNIMPLEMENTED art_quick_check_cast +UNIMPLEMENTED art_quick_aput_obj_with_null_and_bound_check +UNIMPLEMENTED art_quick_aput_obj_with_bound_check +UNIMPLEMENTED art_quick_aput_obj +UNIMPLEMENTED art_quick_initialize_static_storage +UNIMPLEMENTED art_quick_initialize_type +UNIMPLEMENTED art_quick_initialize_type_and_verify_access +UNIMPLEMENTED art_quick_get_boolean_static +UNIMPLEMENTED art_quick_get_byte_static +UNIMPLEMENTED art_quick_get_char_static +UNIMPLEMENTED art_quick_get_short_static +UNIMPLEMENTED art_quick_get32_static +UNIMPLEMENTED art_quick_get64_static +UNIMPLEMENTED art_quick_get_obj_static +UNIMPLEMENTED art_quick_get_boolean_instance +UNIMPLEMENTED art_quick_get_byte_instance +UNIMPLEMENTED art_quick_get_char_instance +UNIMPLEMENTED art_quick_get_short_instance +UNIMPLEMENTED art_quick_get32_instance +UNIMPLEMENTED art_quick_get64_instance +UNIMPLEMENTED art_quick_get_obj_instance +UNIMPLEMENTED art_quick_set8_static +UNIMPLEMENTED art_quick_set16_static +UNIMPLEMENTED art_quick_set32_static +UNIMPLEMENTED art_quick_set64_static +UNIMPLEMENTED art_quick_set_obj_static +UNIMPLEMENTED art_quick_set8_instance +UNIMPLEMENTED art_quick_set16_instance +UNIMPLEMENTED art_quick_set32_instance +UNIMPLEMENTED art_quick_set64_instance +UNIMPLEMENTED art_quick_set_obj_instance +UNIMPLEMENTED art_quick_resolve_string + +// Macro to facilitate adding new allocation entrypoints. +.macro TWO_ARG_DOWNCALL name, entrypoint, return +ENTRY \name + break + break +END \name +.endm + +.macro THREE_ARG_DOWNCALL name, entrypoint, return +ENTRY \name + break + break +END \name +.endm + +// Generate the allocation entrypoints for each allocator. +GENERATE_ALL_ALLOC_ENTRYPOINTS + +UNIMPLEMENTED art_quick_test_suspend +UNIMPLEMENTED art_quick_proxy_invoke_handler +UNIMPLEMENTED art_quick_imt_conflict_trampoline +UNIMPLEMENTED art_quick_resolution_trampoline + + .extern artQuickGenericJniTrampoline + .extern artQuickGenericJniEndTrampoline +ENTRY art_quick_generic_jni_trampoline + SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME_INTERNAL + sd $a0, 0($sp) # store native ArtMethod* to bottom of stack + move $s8, $sp # save $sp + + # prepare for call to artQuickGenericJniTrampoline(Thread*, SP) + move $a0, rSELF # pass Thread::Current + move $a1, $sp # pass $sp + jal artQuickGenericJniTrampoline # (Thread*, SP) + daddiu $sp, $sp, -5120 # reserve space on the stack + + # The C call will have registered the complete save-frame on success. + # The result of the call is: + # v0: ptr to native code, 0 on error. + # v1: ptr to the bottom of the used area of the alloca, can restore stack till here. + beq $v0, $zero, 1f # check entry error + move $t9, $v0 # save the code ptr + move $sp, $v1 # release part of the alloca + + # Load parameters from stack into registers + ld $a0, 0($sp) + ld $a1, 8($sp) + ld $a2, 16($sp) + ld $a3, 24($sp) + ld $a4, 32($sp) + ld $a5, 40($sp) + ld $a6, 48($sp) + ld $a7, 56($sp) + # Load FPRs the same as GPRs. Look at BuildNativeCallFrameStateMachine. + l.d $f12, 0($sp) + l.d $f13, 8($sp) + l.d $f14, 16($sp) + l.d $f15, 24($sp) + l.d $f16, 32($sp) + l.d $f17, 40($sp) + l.d $f18, 48($sp) + l.d $f19, 56($sp) + jalr $t9 # native call + daddiu $sp, $sp, 64 + + # result sign extension is handled in C code + # prepare for call to artQuickGenericJniEndTrampoline(Thread*, result, result_f) + move $a0, rSELF # pass Thread::Current + move $a1, $v0 + jal artQuickGenericJniEndTrampoline + dmfc1 $a2, $f0 + + ld $t0, THREAD_EXCEPTION_OFFSET(rSELF) # load Thread::Current()->exception_ + bne $t0, $zero, 2f # check for pending exceptions + move $sp, $s8 # tear down the alloca + + # tear dpown the callee-save frame + RESTORE_REFS_AND_ARGS_CALLEE_SAVE_FRAME + + jalr $zero, $ra + dmtc1 $v0, $f0 # place return value to FP return value + +1: + move $sp, $s8 # tear down the alloca +2: + RESTORE_REFS_AND_ARGS_CALLEE_SAVE_FRAME + DELIVER_PENDING_EXCEPTION +END art_quick_generic_jni_trampoline + + .extern artQuickToInterpreterBridge +ENTRY art_quick_to_interpreter_bridge + SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME + move $a1, rSELF # pass Thread::Current + jal artQuickToInterpreterBridge # (Method* method, Thread*, SP) + move $a2, $sp # pass $sp + ld $t0, THREAD_EXCEPTION_OFFSET(rSELF) # load Thread::Current()->exception_ + daddiu $sp, $sp, REFS_AND_ARGS_MINUS_REFS_SIZE # skip a0-a7 and f12-f19 + RESTORE_REFS_ONLY_CALLEE_SAVE_FRAME + bne $t0, $zero, 1f + dmtc1 $v0, $f0 # place return value to FP return value + jalr $zero, $ra + dmtc1 $v1, $f1 # place return value to FP return value +1: + DELIVER_PENDING_EXCEPTION +END art_quick_to_interpreter_bridge + + /* + * Routine that intercepts method calls and returns. + */ + .extern artInstrumentationMethodEntryFromCode + .extern artInstrumentationMethodExitFromCode +ENTRY art_quick_instrumentation_entry + SETUP_REFS_AND_ARGS_CALLEE_SAVE_FRAME + daddiu $sp, $sp, -16 # space for saving arg0 + .cfi_adjust_cfa_offset 16 + sd $a0, 0($sp) # save arg0 + move $a3, $ra # pass $ra + jal artInstrumentationMethodEntryFromCode # (Method*, Object*, Thread*, RA) + move $a2, rSELF # pass Thread::Current + move $t9, $v0 # $t9 holds reference to code + ld $a0, 0($sp) # restore arg0 + daddiu $sp, $sp, 16 # remove args + .cfi_adjust_cfa_offset -16 + RESTORE_REFS_AND_ARGS_CALLEE_SAVE_FRAME + jalr $t9 # call method + nop +END art_quick_instrumentation_entry + /* intentional fallthrough */ + .global art_quick_instrumentation_exit +art_quick_instrumentation_exit: + .cfi_startproc + daddiu $t9, $ra, 4 # put current address into $t9 to rebuild $gp + .cpload $t9 + move $ra, $zero # link register is to here, so clobber with 0 for later checks + SETUP_REFS_ONLY_CALLEE_SAVE_FRAME + move $t0, $sp # remember bottom of caller's frame + daddiu $sp, $sp, -16 # save return values and set up args + .cfi_adjust_cfa_offset 16 + sd $v0, 0($sp) + .cfi_rel_offset 2, 0 + s.d $f0, 8($sp) + mov.d $f15, $f0 # pass fpr result + move $a2, $v0 # pass gpr result + move $a1, $t0 # pass $sp + jal artInstrumentationMethodExitFromCode # (Thread*, SP, gpr_res, fpr_res) + move $a0, rSELF # pass Thread::Current + move $t0, $v0 # set aside returned link register + move $ra, $v1 # set link register for deoptimization + ld $v0, 0($sp) # restore return values + l.d $f0, 8($sp) + jalr $zero, $t0 # return + daddiu $sp, $sp, 16+FRAME_SIZE_REFS_ONLY_CALLEE_SAVE # 16 bytes of saved values + ref_only callee save frame + .cfi_adjust_cfa_offset -(16+FRAME_SIZE_REFS_ONLY_CALLEE_SAVE) +END art_quick_instrumentation_exit + +UNIMPLEMENTED art_quick_deoptimize +UNIMPLEMENTED art_quick_indexof +UNIMPLEMENTED art_quick_string_compareto diff --git a/runtime/arch/mips64/quick_method_frame_info_mips64.h b/runtime/arch/mips64/quick_method_frame_info_mips64.h new file mode 100644 index 0000000000..de55e81654 --- /dev/null +++ b/runtime/arch/mips64/quick_method_frame_info_mips64.h @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_QUICK_METHOD_FRAME_INFO_MIPS64_H_ +#define ART_RUNTIME_ARCH_MIPS64_QUICK_METHOD_FRAME_INFO_MIPS64_H_ + +#include "quick/quick_method_frame_info.h" +#include "registers_mips64.h" +#include "runtime.h" // for Runtime::CalleeSaveType. + +namespace art { +namespace mips64 { + +static constexpr uint32_t kMips64CalleeSaveRefSpills = + (1 << art::mips64::S2) | (1 << art::mips64::S3) | (1 << art::mips64::S4) | + (1 << art::mips64::S5) | (1 << art::mips64::S6) | (1 << art::mips64::S7) | + (1 << art::mips64::GP) | (1 << art::mips64::S8); +static constexpr uint32_t kMips64CalleeSaveArgSpills = + (1 << art::mips64::A1) | (1 << art::mips64::A2) | (1 << art::mips64::A3) | + (1 << art::mips64::A4) | (1 << art::mips64::A5) | (1 << art::mips64::A6) | + (1 << art::mips64::A7); +static constexpr uint32_t kMips64CalleeSaveAllSpills = + (1 << art::mips64::S0) | (1 << art::mips64::S1); + +static constexpr uint32_t kMips64CalleeSaveFpRefSpills = 0; +static constexpr uint32_t kMips64CalleeSaveFpArgSpills = + (1 << art::mips64::F12) | (1 << art::mips64::F13) | (1 << art::mips64::F14) | + (1 << art::mips64::F15) | (1 << art::mips64::F16) | (1 << art::mips64::F17) | + (1 << art::mips64::F18) | (1 << art::mips64::F19); +// F12 should not be necessary to spill, as A0 is always in use. +static constexpr uint32_t kMips64CalleeSaveFpAllSpills = + (1 << art::mips64::F24) | (1 << art::mips64::F25) | (1 << art::mips64::F26) | + (1 << art::mips64::F27) | (1 << art::mips64::F28) | (1 << art::mips64::F29) | + (1 << art::mips64::F30) | (1 << art::mips64::F31); + +constexpr uint32_t Mips64CalleeSaveCoreSpills(Runtime::CalleeSaveType type) { + return kMips64CalleeSaveRefSpills | + (type == Runtime::kRefsAndArgs ? kMips64CalleeSaveArgSpills : 0) | + (type == Runtime::kSaveAll ? kMips64CalleeSaveAllSpills : 0) | (1 << art::mips64::RA); +} + +constexpr uint32_t Mips64CalleeSaveFpSpills(Runtime::CalleeSaveType type) { + return kMips64CalleeSaveFpRefSpills | + (type == Runtime::kRefsAndArgs ? kMips64CalleeSaveFpArgSpills: 0) | + (type == Runtime::kSaveAll ? kMips64CalleeSaveFpAllSpills : 0); +} + +constexpr uint32_t Mips64CalleeSaveFrameSize(Runtime::CalleeSaveType type) { + return RoundUp((POPCOUNT(Mips64CalleeSaveCoreSpills(type)) /* gprs */ + + POPCOUNT(Mips64CalleeSaveFpSpills(type)) /* fprs */ + + + 1 /* Method* */) * kMips64PointerSize, kStackAlignment); +} + +constexpr QuickMethodFrameInfo Mips64CalleeSaveMethodFrameInfo(Runtime::CalleeSaveType type) { + return QuickMethodFrameInfo(Mips64CalleeSaveFrameSize(type), + Mips64CalleeSaveCoreSpills(type), + Mips64CalleeSaveFpSpills(type)); +} + +} // namespace mips64 +} // namespace art + +#endif // ART_RUNTIME_ARCH_MIPS64_QUICK_METHOD_FRAME_INFO_MIPS64_H_ diff --git a/runtime/arch/mips64/registers_mips64.cc b/runtime/arch/mips64/registers_mips64.cc new file mode 100644 index 0000000000..495920809f --- /dev/null +++ b/runtime/arch/mips64/registers_mips64.cc @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "registers_mips64.h" + +#include <ostream> + +namespace art { +namespace mips64 { + +static const char* kRegisterNames[] = { + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; + +std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs) { + if (rhs >= ZERO && rhs < kNumberOfGpuRegisters) { + os << kRegisterNames[rhs]; + } else { + os << "GpuRegister[" << static_cast<int>(rhs) << "]"; + } + return os; +} + +std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs) { + if (rhs >= F0 && rhs < kNumberOfFpuRegisters) { + os << "f" << static_cast<int>(rhs); + } else { + os << "FpuRegister[" << static_cast<int>(rhs) << "]"; + } + return os; +} + +} // namespace mips64 +} // namespace art diff --git a/runtime/arch/mips64/registers_mips64.h b/runtime/arch/mips64/registers_mips64.h new file mode 100644 index 0000000000..38bc8f2687 --- /dev/null +++ b/runtime/arch/mips64/registers_mips64.h @@ -0,0 +1,109 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ +#define ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ + +#include <iosfwd> + +#include "base/logging.h" +#include "base/macros.h" +#include "globals.h" + +namespace art { +namespace mips64 { + +enum GpuRegister { + ZERO = 0, + AT = 1, // Assembler temporary. + V0 = 2, // Values. + V1 = 3, + A0 = 4, // Arguments. + A1 = 5, + A2 = 6, + A3 = 7, + A4 = 8, + A5 = 9, + A6 = 10, + A7 = 11, + T0 = 12, // Temporaries. + T1 = 13, + T2 = 14, + T3 = 15, + S0 = 16, // Saved values. + S1 = 17, + S2 = 18, + S3 = 19, + S4 = 20, + S5 = 21, + S6 = 22, + S7 = 23, + T8 = 24, // More temporaries. + T9 = 25, + K0 = 26, // Reserved for trap handler. + K1 = 27, + GP = 28, // Global pointer. + SP = 29, // Stack pointer. + S8 = 30, // Saved value/frame pointer. + RA = 31, // Return address. + kNumberOfGpuRegisters = 32, + kNoGpuRegister = -1 // Signals an illegal register. +}; +std::ostream& operator<<(std::ostream& os, const GpuRegister& rhs); + +// Values for floating point registers. +enum FpuRegister { + F0 = 0, + F1 = 1, + F2 = 2, + F3 = 3, + F4 = 4, + F5 = 5, + F6 = 6, + F7 = 7, + F8 = 8, + F9 = 9, + F10 = 10, + F11 = 11, + F12 = 12, + F13 = 13, + F14 = 14, + F15 = 15, + F16 = 16, + F17 = 17, + F18 = 18, + F19 = 19, + F20 = 20, + F21 = 21, + F22 = 22, + F23 = 23, + F24 = 24, + F25 = 25, + F26 = 26, + F27 = 27, + F28 = 28, + F29 = 29, + F30 = 30, + F31 = 31, + kNumberOfFpuRegisters = 32, + kNoFpuRegister = -1, +}; +std::ostream& operator<<(std::ostream& os, const FpuRegister& rhs); + +} // namespace mips64 +} // namespace art + +#endif // ART_RUNTIME_ARCH_MIPS64_REGISTERS_MIPS64_H_ diff --git a/runtime/arch/mips64/thread_mips64.cc b/runtime/arch/mips64/thread_mips64.cc new file mode 100644 index 0000000000..c55537ccc2 --- /dev/null +++ b/runtime/arch/mips64/thread_mips64.cc @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "thread.h" + +#include "asm_support_mips64.h" +#include "base/logging.h" + +namespace art { + +void Thread::InitCpu() { + CHECK_EQ(THREAD_FLAGS_OFFSET, ThreadFlagsOffset<8>().Int32Value()); + CHECK_EQ(THREAD_CARD_TABLE_OFFSET, CardTableOffset<8>().Int32Value()); + CHECK_EQ(THREAD_EXCEPTION_OFFSET, ExceptionOffset<8>().Int32Value()); +} + +void Thread::CleanupCpu() { + // Do nothing. +} + +} // namespace art diff --git a/runtime/arch/stub_test.cc b/runtime/arch/stub_test.cc index 285007c48d..986b7ecd59 100644 --- a/runtime/arch/stub_test.cc +++ b/runtime/arch/stub_test.cc @@ -799,6 +799,9 @@ static void TestUnlockObject(StubTest* test) NO_THREAD_SAFETY_ANALYSIS { } TEST_F(StubTest, UnlockObject) { + // This will lead to monitor error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + TestUnlockObject(this); } @@ -992,6 +995,9 @@ TEST_F(StubTest, AllocObject) { TEST_DISABLED_FOR_HEAP_REFERENCE_POISONING(); #if defined(__i386__) || defined(__arm__) || defined(__aarch64__) || (defined(__x86_64__) && !defined(__APPLE__)) + // This will lead to OOM error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + // TODO: Check the "Unresolved" allocation stubs Thread* self = Thread::Current(); @@ -1116,6 +1122,9 @@ TEST_F(StubTest, AllocObjectArray) { #if defined(__i386__) || defined(__arm__) || defined(__aarch64__) || (defined(__x86_64__) && !defined(__APPLE__)) // TODO: Check the "Unresolved" allocation stubs + // This will lead to OOM error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + Thread* self = Thread::Current(); // Create an object ScopedObjectAccess soa(self); diff --git a/runtime/atomic.h b/runtime/atomic.h index cf61277053..87de506a85 100644 --- a/runtime/atomic.h +++ b/runtime/atomic.h @@ -46,6 +46,9 @@ class Mutex; class QuasiAtomic { #if defined(__mips__) && !defined(__LP64__) static constexpr bool kNeedSwapMutexes = true; +#elif defined(__mips__) && defined(__LP64__) + // TODO - mips64 still need this for Cas64 ??? + static constexpr bool kNeedSwapMutexes = true; #else static constexpr bool kNeedSwapMutexes = false; #endif diff --git a/runtime/base/logging.cc b/runtime/base/logging.cc index f3e0918d33..0764b877a1 100644 --- a/runtime/base/logging.cc +++ b/runtime/base/logging.cc @@ -303,4 +303,13 @@ void LogMessage::LogLineLowStack(const char* file, unsigned int line, LogSeverit #endif } +ScopedLogSeverity::ScopedLogSeverity(LogSeverity level) { + old_ = gMinimumLogSeverity; + gMinimumLogSeverity = level; +} + +ScopedLogSeverity::~ScopedLogSeverity() { + gMinimumLogSeverity = old_; +} + } // namespace art diff --git a/runtime/base/logging.h b/runtime/base/logging.h index ae83e331fd..cc1a4a1e62 100644 --- a/runtime/base/logging.h +++ b/runtime/base/logging.h @@ -254,6 +254,16 @@ class LogMessage { DISALLOW_COPY_AND_ASSIGN(LogMessage); }; +// Allows to temporarily change the minimum severity level for logging. +class ScopedLogSeverity { + public: + explicit ScopedLogSeverity(LogSeverity level); + ~ScopedLogSeverity(); + + private: + LogSeverity old_; +}; + } // namespace art #endif // ART_RUNTIME_BASE_LOGGING_H_ diff --git a/runtime/base/mutex.cc b/runtime/base/mutex.cc index a4eb318d4c..17b2ac98c6 100644 --- a/runtime/base/mutex.cc +++ b/runtime/base/mutex.cc @@ -612,7 +612,7 @@ bool ReaderWriterMutex::ExclusiveLockWithTimeout(Thread* self, int64_t ms, int32 #if ART_USE_FUTEXES bool done = false; timespec end_abs_ts; - InitTimeSpec(true, CLOCK_REALTIME, ms, ns, &end_abs_ts); + InitTimeSpec(true, CLOCK_MONOTONIC, ms, ns, &end_abs_ts); do { int32_t cur_state = state_.LoadRelaxed(); if (cur_state == 0) { @@ -621,7 +621,7 @@ bool ReaderWriterMutex::ExclusiveLockWithTimeout(Thread* self, int64_t ms, int32 } else { // Failed to acquire, hang up. timespec now_abs_ts; - InitTimeSpec(true, CLOCK_REALTIME, 0, 0, &now_abs_ts); + InitTimeSpec(true, CLOCK_MONOTONIC, 0, 0, &now_abs_ts); timespec rel_ts; if (ComputeRelativeTimeSpec(&rel_ts, end_abs_ts, now_abs_ts)) { return false; // Timed out. diff --git a/runtime/class_linker.cc b/runtime/class_linker.cc index 438cebfff4..05b6b1dba5 100644 --- a/runtime/class_linker.cc +++ b/runtime/class_linker.cc @@ -1748,23 +1748,23 @@ void ClassLinker::VisitClassRoots(RootCallback* callback, void* arg, VisitRootFl WriterMutexLock mu(Thread::Current(), *Locks::classlinker_classes_lock_); if ((flags & kVisitRootFlagAllRoots) != 0) { for (GcRoot<mirror::Class>& root : class_table_) { - root.VisitRoot(callback, arg, 0, kRootStickyClass); + root.VisitRoot(callback, arg, RootInfo(kRootStickyClass)); } for (GcRoot<mirror::Class>& root : pre_zygote_class_table_) { - root.VisitRoot(callback, arg, 0, kRootStickyClass); + root.VisitRoot(callback, arg, RootInfo(kRootStickyClass)); } } else if ((flags & kVisitRootFlagNewRoots) != 0) { for (auto& root : new_class_roots_) { mirror::Class* old_ref = root.Read<kWithoutReadBarrier>(); - root.VisitRoot(callback, arg, 0, kRootStickyClass); + root.VisitRoot(callback, arg, RootInfo(kRootStickyClass)); mirror::Class* new_ref = root.Read<kWithoutReadBarrier>(); if (UNLIKELY(new_ref != old_ref)) { // Uh ohes, GC moved a root in the log. Need to search the class_table and update the // corresponding object. This is slow, but luckily for us, this may only happen with a // concurrent moving GC. auto it = class_table_.Find(GcRoot<mirror::Class>(old_ref)); - class_table_.Erase(it); - class_table_.Insert(GcRoot<mirror::Class>(new_ref)); + DCHECK(it != class_table_.end()); + *it = GcRoot<mirror::Class>(new_ref); } } } @@ -1784,17 +1784,17 @@ void ClassLinker::VisitClassRoots(RootCallback* callback, void* arg, VisitRootFl // reinit references to when reinitializing a ClassLinker from a // mapped image. void ClassLinker::VisitRoots(RootCallback* callback, void* arg, VisitRootFlags flags) { - class_roots_.VisitRoot(callback, arg, 0, kRootVMInternal); + class_roots_.VisitRoot(callback, arg, RootInfo(kRootVMInternal)); Thread* self = Thread::Current(); { ReaderMutexLock mu(self, dex_lock_); if ((flags & kVisitRootFlagAllRoots) != 0) { for (GcRoot<mirror::DexCache>& dex_cache : dex_caches_) { - dex_cache.VisitRoot(callback, arg, 0, kRootVMInternal); + dex_cache.VisitRoot(callback, arg, RootInfo(kRootVMInternal)); } } else if ((flags & kVisitRootFlagNewRoots) != 0) { for (size_t index : new_dex_cache_roots_) { - dex_caches_[index].VisitRoot(callback, arg, 0, kRootVMInternal); + dex_caches_[index].VisitRoot(callback, arg, RootInfo(kRootVMInternal)); } } if ((flags & kVisitRootFlagClearRootLog) != 0) { @@ -1807,12 +1807,10 @@ void ClassLinker::VisitRoots(RootCallback* callback, void* arg, VisitRootFlags f } } VisitClassRoots(callback, arg, flags); - array_iftable_.VisitRoot(callback, arg, 0, kRootVMInternal); + array_iftable_.VisitRoot(callback, arg, RootInfo(kRootVMInternal)); DCHECK(!array_iftable_.IsNull()); for (size_t i = 0; i < kFindArrayCacheSize; ++i) { - if (!find_array_class_cache_[i].IsNull()) { - find_array_class_cache_[i].VisitRoot(callback, arg, 0, kRootVMInternal); - } + find_array_class_cache_[i].VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); } } @@ -4486,6 +4484,171 @@ bool ClassLinker::LinkClass(Thread* self, const char* descriptor, Handle<mirror: return true; } +static void CountMethodsAndFields(ClassDataItemIterator& dex_data, + size_t* virtual_methods, + size_t* direct_methods, + size_t* static_fields, + size_t* instance_fields) { + *virtual_methods = *direct_methods = *static_fields = *instance_fields = 0; + + while (dex_data.HasNextStaticField()) { + dex_data.Next(); + (*static_fields)++; + } + while (dex_data.HasNextInstanceField()) { + dex_data.Next(); + (*instance_fields)++; + } + while (dex_data.HasNextDirectMethod()) { + (*direct_methods)++; + dex_data.Next(); + } + while (dex_data.HasNextVirtualMethod()) { + (*virtual_methods)++; + dex_data.Next(); + } + DCHECK(!dex_data.HasNext()); +} + +static void DumpClass(std::ostream& os, + const DexFile& dex_file, const DexFile::ClassDef& dex_class_def, + const char* suffix) { + ClassDataItemIterator dex_data(dex_file, dex_file.GetClassData(dex_class_def)); + os << dex_file.GetClassDescriptor(dex_class_def) << suffix << ":\n"; + os << " Static fields:\n"; + while (dex_data.HasNextStaticField()) { + const DexFile::FieldId& id = dex_file.GetFieldId(dex_data.GetMemberIndex()); + os << " " << dex_file.GetFieldTypeDescriptor(id) << " " << dex_file.GetFieldName(id) << "\n"; + dex_data.Next(); + } + os << " Instance fields:\n"; + while (dex_data.HasNextInstanceField()) { + const DexFile::FieldId& id = dex_file.GetFieldId(dex_data.GetMemberIndex()); + os << " " << dex_file.GetFieldTypeDescriptor(id) << " " << dex_file.GetFieldName(id) << "\n"; + dex_data.Next(); + } + os << " Direct methods:\n"; + while (dex_data.HasNextDirectMethod()) { + const DexFile::MethodId& id = dex_file.GetMethodId(dex_data.GetMemberIndex()); + os << " " << dex_file.GetMethodName(id) << dex_file.GetMethodSignature(id).ToString() << "\n"; + dex_data.Next(); + } + os << " Virtual methods:\n"; + while (dex_data.HasNextVirtualMethod()) { + const DexFile::MethodId& id = dex_file.GetMethodId(dex_data.GetMemberIndex()); + os << " " << dex_file.GetMethodName(id) << dex_file.GetMethodSignature(id).ToString() << "\n"; + dex_data.Next(); + } +} + +static std::string DumpClasses(const DexFile& dex_file1, const DexFile::ClassDef& dex_class_def1, + const DexFile& dex_file2, const DexFile::ClassDef& dex_class_def2) { + std::ostringstream os; + DumpClass(os, dex_file1, dex_class_def1, " (Compile time)"); + DumpClass(os, dex_file2, dex_class_def2, " (Runtime)"); + return os.str(); +} + + +// Very simple structural check on whether the classes match. Only compares the number of +// methods and fields. +static bool SimpleStructuralCheck(const DexFile& dex_file1, const DexFile::ClassDef& dex_class_def1, + const DexFile& dex_file2, const DexFile::ClassDef& dex_class_def2, + std::string* error_msg) { + ClassDataItemIterator dex_data1(dex_file1, dex_file1.GetClassData(dex_class_def1)); + ClassDataItemIterator dex_data2(dex_file2, dex_file2.GetClassData(dex_class_def2)); + + // Counters for current dex file. + size_t dex_virtual_methods1, dex_direct_methods1, dex_static_fields1, dex_instance_fields1; + CountMethodsAndFields(dex_data1, &dex_virtual_methods1, &dex_direct_methods1, &dex_static_fields1, + &dex_instance_fields1); + // Counters for compile-time dex file. + size_t dex_virtual_methods2, dex_direct_methods2, dex_static_fields2, dex_instance_fields2; + CountMethodsAndFields(dex_data2, &dex_virtual_methods2, &dex_direct_methods2, &dex_static_fields2, + &dex_instance_fields2); + + if (dex_virtual_methods1 != dex_virtual_methods2) { + std::string class_dump = DumpClasses(dex_file1, dex_class_def1, dex_file2, dex_class_def2); + *error_msg = StringPrintf("Virtual method count off: %zu vs %zu\n%s", dex_virtual_methods1, + dex_virtual_methods2, class_dump.c_str()); + return false; + } + if (dex_direct_methods1 != dex_direct_methods2) { + std::string class_dump = DumpClasses(dex_file1, dex_class_def1, dex_file2, dex_class_def2); + *error_msg = StringPrintf("Direct method count off: %zu vs %zu\n%s", dex_direct_methods1, + dex_direct_methods2, class_dump.c_str()); + return false; + } + if (dex_static_fields1 != dex_static_fields2) { + std::string class_dump = DumpClasses(dex_file1, dex_class_def1, dex_file2, dex_class_def2); + *error_msg = StringPrintf("Static field count off: %zu vs %zu\n%s", dex_static_fields1, + dex_static_fields2, class_dump.c_str()); + return false; + } + if (dex_instance_fields1 != dex_instance_fields2) { + std::string class_dump = DumpClasses(dex_file1, dex_class_def1, dex_file2, dex_class_def2); + *error_msg = StringPrintf("Instance field count off: %zu vs %zu\n%s", dex_instance_fields1, + dex_instance_fields2, class_dump.c_str()); + return false; + } + + return true; +} + +// Checks whether a the super-class changed from what we had at compile-time. This would +// invalidate quickening. +static bool CheckSuperClassChange(Handle<mirror::Class> klass, + const DexFile& dex_file, + const DexFile::ClassDef& class_def, + mirror::Class* super_class) + SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { + // Check for unexpected changes in the superclass. + // Quick check 1) is the super_class class-loader the boot class loader? This always has + // precedence. + if (super_class->GetClassLoader() != nullptr && + // Quick check 2) different dex cache? Breaks can only occur for different dex files, + // which is implied by different dex cache. + klass->GetDexCache() != super_class->GetDexCache()) { + // Now comes the expensive part: things can be broken if (a) the klass' dex file has a + // definition for the super-class, and (b) the files are in separate oat files. The oat files + // are referenced from the dex file, so do (b) first. Only relevant if we have oat files. + const OatFile* class_oat_file = dex_file.GetOatFile(); + if (class_oat_file != nullptr) { + const OatFile* loaded_super_oat_file = super_class->GetDexFile().GetOatFile(); + if (loaded_super_oat_file != nullptr && class_oat_file != loaded_super_oat_file) { + // Now check (a). + const DexFile::ClassDef* super_class_def = dex_file.FindClassDef(class_def.superclass_idx_); + if (super_class_def != nullptr) { + // Uh-oh, we found something. Do our check. + std::string error_msg; + if (!SimpleStructuralCheck(dex_file, *super_class_def, + super_class->GetDexFile(), *super_class->GetClassDef(), + &error_msg)) { + // Print a warning to the log. This exception might be caught, e.g., as common in test + // drivers. When the class is later tried to be used, we re-throw a new instance, as we + // only save the type of the exception. + LOG(WARNING) << "Incompatible structural change detected: " << + StringPrintf( + "Structural change of %s is hazardous (%s at compile time, %s at runtime): %s", + PrettyType(super_class_def->class_idx_, dex_file).c_str(), + class_oat_file->GetLocation().c_str(), + loaded_super_oat_file->GetLocation().c_str(), + error_msg.c_str()); + ThrowIncompatibleClassChangeError(klass.Get(), + "Structural change of %s is hazardous (%s at compile time, %s at runtime): %s", + PrettyType(super_class_def->class_idx_, dex_file).c_str(), + class_oat_file->GetLocation().c_str(), + loaded_super_oat_file->GetLocation().c_str(), + error_msg.c_str()); + return false; + } + } + } + } + } + return true; +} + bool ClassLinker::LoadSuperAndInterfaces(Handle<mirror::Class> klass, const DexFile& dex_file) { CHECK_EQ(mirror::Class::kStatusIdx, klass->GetStatus()); const DexFile::ClassDef& class_def = dex_file.GetClassDef(klass->GetDexClassDefIndex()); @@ -4505,6 +4668,11 @@ bool ClassLinker::LoadSuperAndInterfaces(Handle<mirror::Class> klass, const DexF } CHECK(super_class->IsResolved()); klass->SetSuperClass(super_class); + + if (!CheckSuperClassChange(klass, dex_file, class_def, super_class)) { + DCHECK(Thread::Current()->IsExceptionPending()); + return false; + } } const DexFile::TypeList* interfaces = dex_file.GetInterfacesList(class_def); if (interfaces != nullptr) { diff --git a/runtime/class_linker_test.cc b/runtime/class_linker_test.cc index 6c7c1e2b50..64e129c384 100644 --- a/runtime/class_linker_test.cc +++ b/runtime/class_linker_test.cc @@ -365,7 +365,7 @@ class ClassLinkerTest : public CommonRuntimeTest { } } - static void TestRootVisitor(mirror::Object** root, void*, uint32_t, RootType) { + static void TestRootVisitor(mirror::Object** root, void*, const RootInfo&) { EXPECT_TRUE(*root != nullptr); } }; diff --git a/runtime/common_runtime_test.cc b/runtime/common_runtime_test.cc index e017699b04..d48ac9d6b1 100644 --- a/runtime/common_runtime_test.cc +++ b/runtime/common_runtime_test.cc @@ -20,6 +20,7 @@ #include <dlfcn.h> #include <fcntl.h> #include <ScopedLocalRef.h> +#include <stdlib.h> #include "../../external/icu/icu4c/source/common/unicode/uvernum.h" #include "base/macros.h" @@ -43,6 +44,11 @@ #include "well_known_classes.h" int main(int argc, char **argv) { + // Gtests can be very noisy. For example, an executable with multiple tests will trigger native + // bridge warnings. The following line reduces the minimum log severity to ERROR and suppresses + // everything else. In case you want to see all messages, comment out the line. + setenv("ANDROID_LOG_TAGS", "*:e", 1); + art::InitLogging(argv); LOG(::art::INFO) << "Running main() from common_runtime_test.cc..."; testing::InitGoogleTest(&argc, argv); diff --git a/runtime/debugger.cc b/runtime/debugger.cc index 229a1af6b1..c595de738c 100644 --- a/runtime/debugger.cc +++ b/runtime/debugger.cc @@ -342,19 +342,18 @@ uint32_t Dbg::instrumentation_events_ = 0; // Breakpoints. static std::vector<Breakpoint> gBreakpoints GUARDED_BY(Locks::breakpoint_lock_); -void DebugInvokeReq::VisitRoots(RootCallback* callback, void* arg, uint32_t tid, - RootType root_type) { +void DebugInvokeReq::VisitRoots(RootCallback* callback, void* arg, const RootInfo& root_info) { if (receiver != nullptr) { - callback(&receiver, arg, tid, root_type); + callback(&receiver, arg, root_info); } if (thread != nullptr) { - callback(&thread, arg, tid, root_type); + callback(&thread, arg, root_info); } if (klass != nullptr) { - callback(reinterpret_cast<mirror::Object**>(&klass), arg, tid, root_type); + callback(reinterpret_cast<mirror::Object**>(&klass), arg, root_info); } if (method != nullptr) { - callback(reinterpret_cast<mirror::Object**>(&method), arg, tid, root_type); + callback(reinterpret_cast<mirror::Object**>(&method), arg, root_info); } } @@ -366,10 +365,9 @@ void DebugInvokeReq::Clear() { method = nullptr; } -void SingleStepControl::VisitRoots(RootCallback* callback, void* arg, uint32_t tid, - RootType root_type) { +void SingleStepControl::VisitRoots(RootCallback* callback, void* arg, const RootInfo& root_info) { if (method != nullptr) { - callback(reinterpret_cast<mirror::Object**>(&method), arg, tid, root_type); + callback(reinterpret_cast<mirror::Object**>(&method), arg, root_info); } } diff --git a/runtime/debugger.h b/runtime/debugger.h index 8f0db76c2b..e79e8e4083 100644 --- a/runtime/debugger.h +++ b/runtime/debugger.h @@ -28,6 +28,7 @@ #include <string> #include <vector> +#include "gc_root.h" #include "jdwp/jdwp.h" #include "jni.h" #include "jvalue.h" @@ -87,7 +88,7 @@ struct DebugInvokeReq { Mutex lock DEFAULT_MUTEX_ACQUIRED_AFTER; ConditionVariable cond GUARDED_BY(lock); - void VisitRoots(RootCallback* callback, void* arg, uint32_t tid, RootType root_type) + void VisitRoots(RootCallback* callback, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); void Clear(); @@ -122,7 +123,7 @@ struct SingleStepControl { // single-step depth. int stack_depth; - void VisitRoots(RootCallback* callback, void* arg, uint32_t tid, RootType root_type) + void VisitRoots(RootCallback* callback, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); bool ContainsDexPc(uint32_t dex_pc) const; diff --git a/runtime/dex_file.cc b/runtime/dex_file.cc index 3f6175f663..dc85f6c2c9 100644 --- a/runtime/dex_file.cc +++ b/runtime/dex_file.cc @@ -250,6 +250,7 @@ std::unique_ptr<const DexFile> DexFile::OpenMemory(const std::string& location, location, location_checksum, mem_map, + nullptr, error_msg); } @@ -337,9 +338,12 @@ std::unique_ptr<const DexFile> DexFile::OpenMemory(const uint8_t* base, size_t size, const std::string& location, uint32_t location_checksum, - MemMap* mem_map, std::string* error_msg) { + MemMap* mem_map, + const OatFile* oat_file, + std::string* error_msg) { CHECK_ALIGNED(base, 4); // various dex file structures must be word aligned - std::unique_ptr<DexFile> dex_file(new DexFile(base, size, location, location_checksum, mem_map)); + std::unique_ptr<DexFile> dex_file( + new DexFile(base, size, location, location_checksum, mem_map, oat_file)); if (!dex_file->Init(error_msg)) { dex_file.reset(); } @@ -349,7 +353,8 @@ std::unique_ptr<const DexFile> DexFile::OpenMemory(const uint8_t* base, DexFile::DexFile(const uint8_t* base, size_t size, const std::string& location, uint32_t location_checksum, - MemMap* mem_map) + MemMap* mem_map, + const OatFile* oat_file) : begin_(base), size_(size), location_(location), @@ -363,7 +368,8 @@ DexFile::DexFile(const uint8_t* base, size_t size, proto_ids_(reinterpret_cast<const ProtoId*>(base + header_->proto_ids_off_)), class_defs_(reinterpret_cast<const ClassDef*>(base + header_->class_defs_off_)), find_class_def_misses_(0), - class_def_index_(nullptr) { + class_def_index_(nullptr), + oat_file_(oat_file) { CHECK(begin_ != NULL) << GetLocation(); CHECK_GT(size_, 0U) << GetLocation(); } diff --git a/runtime/dex_file.h b/runtime/dex_file.h index 019c8e6e9a..9b8f254448 100644 --- a/runtime/dex_file.h +++ b/runtime/dex_file.h @@ -44,6 +44,7 @@ namespace mirror { } // namespace mirror class ClassLinker; class MemMap; +class OatFile; class Signature; template<class T> class Handle; class StringPiece; @@ -391,8 +392,9 @@ class DexFile { static std::unique_ptr<const DexFile> Open(const uint8_t* base, size_t size, const std::string& location, uint32_t location_checksum, + const OatFile* oat_file, std::string* error_msg) { - return OpenMemory(base, size, location, location_checksum, NULL, error_msg); + return OpenMemory(base, size, location, location_checksum, NULL, oat_file, error_msg); } // Open all classesXXX.dex files from a zip archive. @@ -891,6 +893,10 @@ class DexFile { // the dex_location where it's file name part has been made canonical. static std::string GetDexCanonicalLocation(const char* dex_location); + const OatFile* GetOatFile() const { + return oat_file_; + } + private: // Opens a .dex file static std::unique_ptr<const DexFile> OpenFile(int fd, const char* location, @@ -927,12 +933,14 @@ class DexFile { const std::string& location, uint32_t location_checksum, MemMap* mem_map, + const OatFile* oat_file, std::string* error_msg); DexFile(const uint8_t* base, size_t size, const std::string& location, uint32_t location_checksum, - MemMap* mem_map); + MemMap* mem_map, + const OatFile* oat_file); // Top-level initializer that calls other Init methods. bool Init(std::string* error_msg); @@ -1015,6 +1023,10 @@ class DexFile { }; typedef HashMap<const char*, const ClassDef*, UTF16EmptyFn, UTF16HashCmp, UTF16HashCmp> Index; mutable Atomic<Index*> class_def_index_; + + // The oat file this dex file was loaded from. May be null in case the dex file is not coming + // from an oat file, e.g., directly from an apk. + const OatFile* oat_file_; }; std::ostream& operator<<(std::ostream& os, const DexFile& dex_file); diff --git a/runtime/elf_file.cc b/runtime/elf_file.cc index b6df6097bd..1b91aa64d2 100644 --- a/runtime/elf_file.cc +++ b/runtime/elf_file.cc @@ -1335,6 +1335,8 @@ bool ElfFileImpl<Elf_Ehdr, Elf_Phdr, Elf_Shdr, Elf_Word, if ((GetHeader().e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R2 || (GetHeader().e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_32R6) { elf_ISA = kMips; + } else if ((GetHeader().e_flags & EF_MIPS_ARCH) == EF_MIPS_ARCH_64R6) { + elf_ISA = kMips64; } break; } diff --git a/runtime/elf_utils.h b/runtime/elf_utils.h index 3579e27953..418d937b12 100644 --- a/runtime/elf_utils.h +++ b/runtime/elf_utils.h @@ -31,6 +31,7 @@ namespace art { #define EF_MIPS_ABI_O32 0x00001000 #define EF_MIPS_ARCH_32R2 0x70000000 #define EF_MIPS_ARCH_32R6 0x90000000 +#define EF_MIPS_ARCH_64R6 0xa0000000 #define EI_ABIVERSION 8 #define EM_ARM 40 diff --git a/runtime/entrypoints/quick/callee_save_frame.h b/runtime/entrypoints/quick/callee_save_frame.h index 9ffd199786..8cd6ca6777 100644 --- a/runtime/entrypoints/quick/callee_save_frame.h +++ b/runtime/entrypoints/quick/callee_save_frame.h @@ -27,6 +27,7 @@ #include "arch/arm/quick_method_frame_info_arm.h" #include "arch/arm64/quick_method_frame_info_arm64.h" #include "arch/mips/quick_method_frame_info_mips.h" +#include "arch/mips64/quick_method_frame_info_mips64.h" #include "arch/x86/quick_method_frame_info_x86.h" #include "arch/x86_64/quick_method_frame_info_x86_64.h" @@ -76,6 +77,7 @@ static constexpr size_t GetCalleeSaveFrameSize(InstructionSet isa, Runtime::Call return (isa == kArm || isa == kThumb2) ? arm::ArmCalleeSaveFrameSize(type) : isa == kArm64 ? arm64::Arm64CalleeSaveFrameSize(type) : isa == kMips ? mips::MipsCalleeSaveFrameSize(type) : + isa == kMips64 ? mips64::Mips64CalleeSaveFrameSize(type) : isa == kX86 ? x86::X86CalleeSaveFrameSize(type) : isa == kX86_64 ? x86_64::X86_64CalleeSaveFrameSize(type) : isa == kNone ? (LOG(FATAL) << "kNone has no frame size", 0) : @@ -88,6 +90,7 @@ static constexpr size_t GetConstExprPointerSize(InstructionSet isa) { return (isa == kArm || isa == kThumb2) ? kArmPointerSize : isa == kArm64 ? kArm64PointerSize : isa == kMips ? kMipsPointerSize : + isa == kMips64 ? kMips64PointerSize : isa == kX86 ? kX86PointerSize : isa == kX86_64 ? kX86_64PointerSize : isa == kNone ? (LOG(FATAL) << "kNone has no pointer size", 0) : diff --git a/runtime/entrypoints/quick/quick_trampoline_entrypoints.cc b/runtime/entrypoints/quick/quick_trampoline_entrypoints.cc index ac640b4454..cd34d8880d 100644 --- a/runtime/entrypoints/quick/quick_trampoline_entrypoints.cc +++ b/runtime/entrypoints/quick/quick_trampoline_entrypoints.cc @@ -64,6 +64,7 @@ class QuickArgumentVisitor { static constexpr bool kQuickDoubleRegAlignedFloatBackFilled = !kArm32QuickCodeUseSoftFloat; static constexpr size_t kNumQuickGprArgs = 3; static constexpr size_t kNumQuickFprArgs = kArm32QuickCodeUseSoftFloat ? 0 : 16; + static constexpr bool kGprFprLockstep = false; static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset = arm::ArmCalleeSaveFpr1Offset(Runtime::kRefsAndArgs); // Offset of first FPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset = @@ -99,6 +100,7 @@ class QuickArgumentVisitor { static constexpr bool kQuickDoubleRegAlignedFloatBackFilled = false; static constexpr size_t kNumQuickGprArgs = 7; // 7 arguments passed in GPRs. static constexpr size_t kNumQuickFprArgs = 8; // 8 arguments passed in FPRs. + static constexpr bool kGprFprLockstep = false; static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset = arm64::Arm64CalleeSaveFpr1Offset(Runtime::kRefsAndArgs); // Offset of first FPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset = @@ -108,7 +110,7 @@ class QuickArgumentVisitor { static size_t GprIndexToGprOffset(uint32_t gpr_index) { return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); } -#elif defined(__mips__) +#elif defined(__mips__) && !defined(__LP64__) // The callee save frame is pointed to by SP. // | argN | | // | ... | | @@ -128,12 +130,60 @@ class QuickArgumentVisitor { static constexpr bool kQuickDoubleRegAlignedFloatBackFilled = false; static constexpr size_t kNumQuickGprArgs = 3; // 3 arguments passed in GPRs. static constexpr size_t kNumQuickFprArgs = 0; // 0 arguments passed in FPRs. + static constexpr bool kGprFprLockstep = false; static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset = 0; // Offset of first FPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset = 4; // Offset of first GPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_LrOffset = 60; // Offset of return address. static size_t GprIndexToGprOffset(uint32_t gpr_index) { return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); } +#elif defined(__mips__) && defined(__LP64__) + // The callee save frame is pointed to by SP. + // | argN | | + // | ... | | + // | arg4 | | + // | arg3 spill | | Caller's frame + // | arg2 spill | | + // | arg1 spill | | + // | Method* | --- + // | RA | + // | ... | callee saves + // | F7 | f_arg7 + // | F6 | f_arg6 + // | F5 | f_arg5 + // | F6 | f_arg6 + // | F5 | f_arg5 + // | F4 | f_arg4 + // | F3 | f_arg3 + // | F2 | f_arg2 + // | F1 | f_arg1 + // | F0 | f_arg0 + // | A7 | arg7 + // | A6 | arg6 + // | A5 | arg5 + // | A4 | arg4 + // | A3 | arg3 + // | A2 | arg2 + // | A1 | arg1 + // | | padding + // | A0/Method* | <- sp + // NOTE: for Mip64, when A0 is skipped, F0 is also skipped. + static constexpr bool kAlignPairRegister = false; + static constexpr bool kQuickSoftFloatAbi = false; + static constexpr bool kQuickDoubleRegAlignedFloatBackFilled = false; + // These values are set to zeros because GPR and FPR register + // assignments for Mips64 are interleaved, which the current VisitArguments() + // function does not support. + static constexpr size_t kNumQuickGprArgs = 7; // 7 arguments passed in GPRs. + static constexpr size_t kNumQuickFprArgs = 7; // 7 arguments passed in FPRs. + static constexpr bool kGprFprLockstep = true; + + static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset = 24; // Offset of first FPR arg (F1). + static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset = 80; // Offset of first GPR arg (A1). + static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_LrOffset = 200; // Offset of return address. + static size_t GprIndexToGprOffset(uint32_t gpr_index) { + return gpr_index * GetBytesPerGprSpillLocation(kRuntimeISA); + } #elif defined(__i386__) // The callee save frame is pointed to by SP. // | argN | | @@ -154,6 +204,7 @@ class QuickArgumentVisitor { static constexpr bool kQuickDoubleRegAlignedFloatBackFilled = false; static constexpr size_t kNumQuickGprArgs = 3; // 3 arguments passed in GPRs. static constexpr size_t kNumQuickFprArgs = 0; // 0 arguments passed in FPRs. + static constexpr bool kGprFprLockstep = false; static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset = 0; // Offset of first FPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset = 4; // Offset of first GPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_LrOffset = 28; // Offset of return address. @@ -193,6 +244,7 @@ class QuickArgumentVisitor { static constexpr bool kQuickDoubleRegAlignedFloatBackFilled = false; static constexpr size_t kNumQuickGprArgs = 5; // 5 arguments passed in GPRs. static constexpr size_t kNumQuickFprArgs = 8; // 8 arguments passed in FPRs. + static constexpr bool kGprFprLockstep = false; static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Fpr1Offset = 16; // Offset of first FPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_Gpr1Offset = 80 + 4*8; // Offset of first GPR arg. static constexpr size_t kQuickCalleeSaveFrame_RefAndArgs_LrOffset = 168 + 4*8; // Offset of return address. @@ -314,6 +366,20 @@ class QuickArgumentVisitor { + stack_index_ * kBytesStackArgLocation); } + void IncGprIndex() { + gpr_index_++; + if (kGprFprLockstep) { + fpr_index_++; + } + } + + void IncFprIndex() { + fpr_index_++; + if (kGprFprLockstep) { + gpr_index_++; + } + } + void VisitArguments() SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { // (a) 'stack_args_' should point to the first method's argument // (b) whatever the argument type it is, the 'stack_index_' should @@ -330,7 +396,7 @@ class QuickArgumentVisitor { Visit(); stack_index_++; if (kNumQuickGprArgs > 0) { - gpr_index_++; + IncGprIndex(); } } for (uint32_t shorty_index = 1; shorty_index < shorty_len_; ++shorty_index) { @@ -346,7 +412,7 @@ class QuickArgumentVisitor { Visit(); stack_index_++; if (gpr_index_ < kNumQuickGprArgs) { - gpr_index_++; + IncGprIndex(); } break; case Primitive::kPrimFloat: @@ -355,11 +421,11 @@ class QuickArgumentVisitor { stack_index_++; if (kQuickSoftFloatAbi) { if (gpr_index_ < kNumQuickGprArgs) { - gpr_index_++; + IncGprIndex(); } } else { if (fpr_index_ + 1 < kNumQuickFprArgs + 1) { - fpr_index_++; + IncFprIndex(); if (kQuickDoubleRegAlignedFloatBackFilled) { // Double should not overlap with float. // For example, if fpr_index_ = 3, fpr_double_index_ should be at least 4. @@ -378,7 +444,7 @@ class QuickArgumentVisitor { if (cur_type_ == Primitive::kPrimLong && kAlignPairRegister && gpr_index_ == 0) { // Currently, this is only for ARM, where the first available parameter register // is R1. So we skip it, and use R2 instead. - gpr_index_++; + IncGprIndex(); } is_split_long_or_double_ = (GetBytesPerGprSpillLocation(kRuntimeISA) == 4) && ((gpr_index_ + 1) == kNumQuickGprArgs); @@ -390,10 +456,10 @@ class QuickArgumentVisitor { stack_index_++; } if (gpr_index_ < kNumQuickGprArgs) { - gpr_index_++; + IncGprIndex(); if (GetBytesPerGprSpillLocation(kRuntimeISA) == 4) { if (gpr_index_ < kNumQuickGprArgs) { - gpr_index_++; + IncGprIndex(); } } } @@ -416,10 +482,10 @@ class QuickArgumentVisitor { } } } else if (fpr_index_ + 1 < kNumQuickFprArgs + 1) { - fpr_index_++; + IncFprIndex(); if (GetBytesPerFprSpillLocation(kRuntimeISA) == 4) { if (fpr_index_ + 1 < kNumQuickFprArgs + 1) { - fpr_index_++; + IncFprIndex(); } } } @@ -939,7 +1005,8 @@ template<class T> class BuildNativeCallFrameStateMachine { static constexpr size_t kRegistersNeededForLong = 2; static constexpr size_t kRegistersNeededForDouble = 2; static constexpr bool kMultiRegistersAligned = true; - static constexpr bool kMultiRegistersWidened = false; + static constexpr bool kMultiFPRegistersWidened = false; + static constexpr bool kMultiGPRegistersWidened = false; static constexpr bool kAlignLongOnStack = true; static constexpr bool kAlignDoubleOnStack = true; #elif defined(__aarch64__) @@ -950,10 +1017,11 @@ template<class T> class BuildNativeCallFrameStateMachine { static constexpr size_t kRegistersNeededForLong = 1; static constexpr size_t kRegistersNeededForDouble = 1; static constexpr bool kMultiRegistersAligned = false; - static constexpr bool kMultiRegistersWidened = false; + static constexpr bool kMultiFPRegistersWidened = false; + static constexpr bool kMultiGPRegistersWidened = false; static constexpr bool kAlignLongOnStack = false; static constexpr bool kAlignDoubleOnStack = false; -#elif defined(__mips__) +#elif defined(__mips__) && !defined(__LP64__) static constexpr bool kNativeSoftFloatAbi = true; // This is a hard float ABI. static constexpr size_t kNumNativeGprArgs = 4; // 4 arguments passed in GPRs. static constexpr size_t kNumNativeFprArgs = 0; // 0 arguments passed in FPRs. @@ -961,9 +1029,23 @@ template<class T> class BuildNativeCallFrameStateMachine { static constexpr size_t kRegistersNeededForLong = 2; static constexpr size_t kRegistersNeededForDouble = 2; static constexpr bool kMultiRegistersAligned = true; - static constexpr bool kMultiRegistersWidened = true; + static constexpr bool kMultiFPRegistersWidened = true; + static constexpr bool kMultiGPRegistersWidened = false; static constexpr bool kAlignLongOnStack = true; static constexpr bool kAlignDoubleOnStack = true; +#elif defined(__mips__) && defined(__LP64__) + // Let the code prepare GPRs only and we will load the FPRs with same data. + static constexpr bool kNativeSoftFloatAbi = true; + static constexpr size_t kNumNativeGprArgs = 8; + static constexpr size_t kNumNativeFprArgs = 0; + + static constexpr size_t kRegistersNeededForLong = 1; + static constexpr size_t kRegistersNeededForDouble = 1; + static constexpr bool kMultiRegistersAligned = false; + static constexpr bool kMultiFPRegistersWidened = false; + static constexpr bool kMultiGPRegistersWidened = true; + static constexpr bool kAlignLongOnStack = false; + static constexpr bool kAlignDoubleOnStack = false; #elif defined(__i386__) // TODO: Check these! static constexpr bool kNativeSoftFloatAbi = false; // Not using int registers for fp @@ -973,7 +1055,8 @@ template<class T> class BuildNativeCallFrameStateMachine { static constexpr size_t kRegistersNeededForLong = 2; static constexpr size_t kRegistersNeededForDouble = 2; static constexpr bool kMultiRegistersAligned = false; // x86 not using regs, anyways - static constexpr bool kMultiRegistersWidened = false; + static constexpr bool kMultiFPRegistersWidened = false; + static constexpr bool kMultiGPRegistersWidened = false; static constexpr bool kAlignLongOnStack = false; static constexpr bool kAlignDoubleOnStack = false; #elif defined(__x86_64__) @@ -984,7 +1067,8 @@ template<class T> class BuildNativeCallFrameStateMachine { static constexpr size_t kRegistersNeededForLong = 1; static constexpr size_t kRegistersNeededForDouble = 1; static constexpr bool kMultiRegistersAligned = false; - static constexpr bool kMultiRegistersWidened = false; + static constexpr bool kMultiFPRegistersWidened = false; + static constexpr bool kMultiGPRegistersWidened = false; static constexpr bool kAlignLongOnStack = false; static constexpr bool kAlignDoubleOnStack = false; #else @@ -1043,10 +1127,20 @@ template<class T> class BuildNativeCallFrameStateMachine { void AdvanceInt(uint32_t val) { if (HaveIntGpr()) { gpr_index_--; - PushGpr(val); + if (kMultiGPRegistersWidened) { + DCHECK_EQ(sizeof(uintptr_t), sizeof(int64_t)); + PushGpr(static_cast<int64_t>(bit_cast<uint32_t, int32_t>(val))); + } else { + PushGpr(val); + } } else { stack_entries_++; - PushStack(val); + if (kMultiGPRegistersWidened) { + DCHECK_EQ(sizeof(uintptr_t), sizeof(int64_t)); + PushStack(static_cast<int64_t>(bit_cast<uint32_t, int32_t>(val))); + } else { + PushStack(val); + } gpr_index_ = 0; } } @@ -1108,7 +1202,7 @@ template<class T> class BuildNativeCallFrameStateMachine { if (HaveFloatFpr()) { fpr_index_--; if (kRegistersNeededForDouble == 1) { - if (kMultiRegistersWidened) { + if (kMultiFPRegistersWidened) { PushFpr8(bit_cast<double, uint64_t>(val)); } else { // No widening, just use the bits. @@ -1119,7 +1213,7 @@ template<class T> class BuildNativeCallFrameStateMachine { } } else { stack_entries_++; - if (kRegistersNeededForDouble == 1 && kMultiRegistersWidened) { + if (kRegistersNeededForDouble == 1 && kMultiFPRegistersWidened) { // Need to widen before storing: Note the "double" in the template instantiation. // Note: We need to jump through those hoops to make the compiler happy. DCHECK_EQ(sizeof(uintptr_t), sizeof(uint64_t)); diff --git a/runtime/gc/collector/mark_compact.cc b/runtime/gc/collector/mark_compact.cc index b2482acaf5..18af0054d7 100644 --- a/runtime/gc/collector/mark_compact.cc +++ b/runtime/gc/collector/mark_compact.cc @@ -300,22 +300,20 @@ mirror::Object* MarkCompact::MarkObjectCallback(mirror::Object* root, void* arg) } void MarkCompact::MarkHeapReferenceCallback(mirror::HeapReference<mirror::Object>* obj_ptr, - void* arg) { + void* arg) { reinterpret_cast<MarkCompact*>(arg)->MarkObject(obj_ptr->AsMirrorPtr()); } void MarkCompact::DelayReferenceReferentCallback(mirror::Class* klass, mirror::Reference* ref, - void* arg) { + void* arg) { reinterpret_cast<MarkCompact*>(arg)->DelayReferenceReferent(klass, ref); } -void MarkCompact::MarkRootCallback(Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +void MarkCompact::MarkRootCallback(Object** root, void* arg, const RootInfo& /*root_info*/) { reinterpret_cast<MarkCompact*>(arg)->MarkObject(*root); } -void MarkCompact::UpdateRootCallback(Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +void MarkCompact::UpdateRootCallback(Object** root, void* arg, const RootInfo& /*root_info*/) { mirror::Object* obj = *root; mirror::Object* new_obj = reinterpret_cast<MarkCompact*>(arg)->GetMarkedForwardAddress(obj); if (obj != new_obj) { diff --git a/runtime/gc/collector/mark_compact.h b/runtime/gc/collector/mark_compact.h index f40e8702d9..f6d473d3dd 100644 --- a/runtime/gc/collector/mark_compact.h +++ b/runtime/gc/collector/mark_compact.h @@ -24,6 +24,7 @@ #include "base/macros.h" #include "base/mutex.h" #include "garbage_collector.h" +#include "gc_root.h" #include "gc/accounting/heap_bitmap.h" #include "immune_region.h" #include "lock_word.h" @@ -113,8 +114,7 @@ class MarkCompact : public GarbageCollector { void SweepSystemWeaks() SHARED_LOCKS_REQUIRED(Locks::heap_bitmap_lock_, Locks::mutator_lock_); - static void MarkRootCallback(mirror::Object** root, void* arg, uint32_t /*tid*/, - RootType /*root_type*/) + static void MarkRootCallback(mirror::Object** root, void* arg, const RootInfo& root_info) EXCLUSIVE_LOCKS_REQUIRED(Locks::heap_bitmap_lock_, Locks::mutator_lock_); static mirror::Object* MarkObjectCallback(mirror::Object* root, void* arg) @@ -180,8 +180,7 @@ class MarkCompact : public GarbageCollector { EXCLUSIVE_LOCKS_REQUIRED(Locks::mutator_lock_, Locks::heap_bitmap_lock_); // Update the references of objects by using the forwarding addresses. void UpdateReferences() EXCLUSIVE_LOCKS_REQUIRED(Locks::mutator_lock_, Locks::heap_bitmap_lock_); - static void UpdateRootCallback(mirror::Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) + static void UpdateRootCallback(mirror::Object** root, void* arg, const RootInfo& /*root_info*/) EXCLUSIVE_LOCKS_REQUIRED(Locks::mutator_lock_) SHARED_LOCKS_REQUIRED(Locks::heap_bitmap_lock_); // Move objects and restore lock words. diff --git a/runtime/gc/collector/mark_sweep.cc b/runtime/gc/collector/mark_sweep.cc index 6ad44e6a75..80f7968ef9 100644 --- a/runtime/gc/collector/mark_sweep.cc +++ b/runtime/gc/collector/mark_sweep.cc @@ -460,42 +460,35 @@ inline void MarkSweep::MarkObject(Object* obj) { } } -void MarkSweep::MarkRootParallelCallback(Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +void MarkSweep::MarkRootParallelCallback(Object** root, void* arg, const RootInfo& /*root_info*/) { reinterpret_cast<MarkSweep*>(arg)->MarkObjectNonNullParallel(*root); } -void MarkSweep::VerifyRootMarked(Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +void MarkSweep::VerifyRootMarked(Object** root, void* arg, const RootInfo& /*root_info*/) { CHECK(reinterpret_cast<MarkSweep*>(arg)->IsMarked(*root)); } -void MarkSweep::MarkRootCallback(Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +void MarkSweep::MarkRootCallback(Object** root, void* arg, const RootInfo& /*root_info*/) { reinterpret_cast<MarkSweep*>(arg)->MarkObjectNonNull(*root); } -void MarkSweep::VerifyRootCallback(const Object* root, void* arg, size_t vreg, - const StackVisitor* visitor, RootType root_type) { - reinterpret_cast<MarkSweep*>(arg)->VerifyRoot(root, vreg, visitor, root_type); +void MarkSweep::VerifyRootCallback(Object** root, void* arg, const RootInfo& root_info) { + reinterpret_cast<MarkSweep*>(arg)->VerifyRoot(*root, root_info); } -void MarkSweep::VerifyRoot(const Object* root, size_t vreg, const StackVisitor* visitor, - RootType root_type) { +void MarkSweep::VerifyRoot(const Object* root, const RootInfo& root_info) { // See if the root is on any space bitmap. if (heap_->GetLiveBitmap()->GetContinuousSpaceBitmap(root) == nullptr) { space::LargeObjectSpace* large_object_space = GetHeap()->GetLargeObjectsSpace(); if (large_object_space != nullptr && !large_object_space->Contains(root)) { - LOG(ERROR) << "Found invalid root: " << root << " with type " << root_type; - if (visitor != NULL) { - LOG(ERROR) << visitor->DescribeLocation() << " in VReg: " << vreg; - } + LOG(ERROR) << "Found invalid root: " << root << " "; + root_info.Describe(LOG(ERROR)); } } } void MarkSweep::VerifyRoots() { - Runtime::Current()->GetThreadList()->VerifyRoots(VerifyRootCallback, this); + Runtime::Current()->GetThreadList()->VisitRoots(VerifyRootCallback, this); } void MarkSweep::MarkRoots(Thread* self) { diff --git a/runtime/gc/collector/mark_sweep.h b/runtime/gc/collector/mark_sweep.h index 9ac110d687..b787327c80 100644 --- a/runtime/gc/collector/mark_sweep.h +++ b/runtime/gc/collector/mark_sweep.h @@ -24,6 +24,7 @@ #include "base/macros.h" #include "base/mutex.h" #include "garbage_collector.h" +#include "gc_root.h" #include "gc/accounting/heap_bitmap.h" #include "immune_region.h" #include "object_callbacks.h" @@ -182,13 +183,11 @@ class MarkSweep : public GarbageCollector { SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) EXCLUSIVE_LOCKS_REQUIRED(Locks::heap_bitmap_lock_); - static void MarkRootCallback(mirror::Object** root, void* arg, uint32_t thread_id, - RootType root_type) + static void MarkRootCallback(mirror::Object** root, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) EXCLUSIVE_LOCKS_REQUIRED(Locks::heap_bitmap_lock_); - static void VerifyRootMarked(mirror::Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) + static void VerifyRootMarked(mirror::Object** root, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) EXCLUSIVE_LOCKS_REQUIRED(Locks::heap_bitmap_lock_); @@ -196,8 +195,7 @@ class MarkSweep : public GarbageCollector { EXCLUSIVE_LOCKS_REQUIRED(Locks::heap_bitmap_lock_) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); - static void MarkRootParallelCallback(mirror::Object** root, void* arg, uint32_t thread_id, - RootType root_type) + static void MarkRootParallelCallback(mirror::Object** root, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); // Marks an object. @@ -247,11 +245,9 @@ class MarkSweep : public GarbageCollector { // whether or not we care about pauses. size_t GetThreadCount(bool paused) const; - static void VerifyRootCallback(const mirror::Object* root, void* arg, size_t vreg, - const StackVisitor *visitor, RootType root_type); + static void VerifyRootCallback(mirror::Object** root, void* arg, const RootInfo& root_info); - void VerifyRoot(const mirror::Object* root, size_t vreg, const StackVisitor* visitor, - RootType root_type) NO_THREAD_SAFETY_ANALYSIS; + void VerifyRoot(const mirror::Object* root, const RootInfo& root_info) NO_THREAD_SAFETY_ANALYSIS; // Push a single reference on a mark stack. void PushOnMarkStack(mirror::Object* obj); diff --git a/runtime/gc/collector/semi_space.cc b/runtime/gc/collector/semi_space.cc index 82d6992922..fcc601f734 100644 --- a/runtime/gc/collector/semi_space.cc +++ b/runtime/gc/collector/semi_space.cc @@ -600,8 +600,7 @@ void SemiSpace::DelayReferenceReferentCallback(mirror::Class* klass, mirror::Ref reinterpret_cast<SemiSpace*>(arg)->DelayReferenceReferent(klass, ref); } -void SemiSpace::MarkRootCallback(Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +void SemiSpace::MarkRootCallback(Object** root, void* arg, const RootInfo& /*root_info*/) { auto ref = StackReference<mirror::Object>::FromMirrorPtr(*root); reinterpret_cast<SemiSpace*>(arg)->MarkObject(&ref); if (*root != ref.AsMirrorPtr()) { diff --git a/runtime/gc/collector/semi_space.h b/runtime/gc/collector/semi_space.h index 1c4f1e418a..f8fced8cc7 100644 --- a/runtime/gc/collector/semi_space.h +++ b/runtime/gc/collector/semi_space.h @@ -23,6 +23,7 @@ #include "base/macros.h" #include "base/mutex.h" #include "garbage_collector.h" +#include "gc_root.h" #include "gc/accounting/heap_bitmap.h" #include "immune_region.h" #include "mirror/object_reference.h" @@ -132,8 +133,7 @@ class SemiSpace : public GarbageCollector { void SweepSystemWeaks() SHARED_LOCKS_REQUIRED(Locks::heap_bitmap_lock_, Locks::mutator_lock_); - static void MarkRootCallback(mirror::Object** root, void* arg, uint32_t /*tid*/, - RootType /*root_type*/) + static void MarkRootCallback(mirror::Object** root, void* arg, const RootInfo& root_info) EXCLUSIVE_LOCKS_REQUIRED(Locks::heap_bitmap_lock_, Locks::mutator_lock_); static mirror::Object* MarkObjectCallback(mirror::Object* root, void* arg) diff --git a/runtime/gc/heap.cc b/runtime/gc/heap.cc index 618f1cc220..553a5d3bfc 100644 --- a/runtime/gc/heap.cc +++ b/runtime/gc/heap.cc @@ -2236,8 +2236,8 @@ void Heap::FinishGC(Thread* self, collector::GcType gc_type) { gc_complete_cond_->Broadcast(self); } -static void RootMatchesObjectVisitor(mirror::Object** root, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) { +static void RootMatchesObjectVisitor(mirror::Object** root, void* arg, + const RootInfo& /*root_info*/) { mirror::Object* obj = reinterpret_cast<mirror::Object*>(arg); if (*root == obj) { LOG(INFO) << "Object " << obj << " is a root"; @@ -2279,12 +2279,12 @@ class VerifyReferenceVisitor { return heap_->IsLiveObjectLocked(obj, true, false, true); } - static void VerifyRootCallback(mirror::Object** root, void* arg, uint32_t thread_id, - RootType root_type) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { + static void VerifyRootCallback(mirror::Object** root, void* arg, const RootInfo& root_info) + SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { VerifyReferenceVisitor* visitor = reinterpret_cast<VerifyReferenceVisitor*>(arg); if (!visitor->VerifyReference(nullptr, *root, MemberOffset(0))) { LOG(ERROR) << "Root " << *root << " is dead with type " << PrettyTypeOf(*root) - << " thread_id= " << thread_id << " root_type= " << root_type; + << " thread_id= " << root_info.GetThreadId() << " root_type= " << root_info.GetType(); } } diff --git a/runtime/gc/space/space_test.h b/runtime/gc/space/space_test.h index 9f39b80c9a..09d10dd94b 100644 --- a/runtime/gc/space/space_test.h +++ b/runtime/gc/space/space_test.h @@ -127,6 +127,9 @@ static inline size_t test_rand(size_t* seed) { } void SpaceTest::InitTestBody(CreateSpaceFn create_space) { + // This will lead to error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + { // Init < max == growth std::unique_ptr<Space> space(create_space("test", 16 * MB, 32 * MB, 32 * MB, nullptr)); diff --git a/runtime/gc_root.h b/runtime/gc_root.h index aee5586f3d..7e0be64441 100644 --- a/runtime/gc_root.h +++ b/runtime/gc_root.h @@ -19,22 +19,75 @@ #include "base/macros.h" #include "base/mutex.h" // For Locks::mutator_lock_. -#include "object_callbacks.h" namespace art { +namespace mirror { +class Object; +} // namespace mirror + +enum RootType { + kRootUnknown = 0, + kRootJNIGlobal, + kRootJNILocal, + kRootJavaFrame, + kRootNativeStack, + kRootStickyClass, + kRootThreadBlock, + kRootMonitorUsed, + kRootThreadObject, + kRootInternedString, + kRootDebugger, + kRootVMInternal, + kRootJNIMonitor, +}; +std::ostream& operator<<(std::ostream& os, const RootType& root_type); + +class RootInfo { + public: + // Thread id 0 is for non thread roots. + explicit RootInfo(RootType type, uint32_t thread_id = 0) + : type_(type), thread_id_(thread_id) { + } + virtual ~RootInfo() { + } + RootType GetType() const { + return type_; + } + uint32_t GetThreadId() const { + return thread_id_; + } + virtual void Describe(std::ostream& os) const { + os << "Type=" << type_ << " thread_id=" << thread_id_; + } + + private: + const RootType type_; + const uint32_t thread_id_; +}; + +// Returns the new address of the object, returns root if it has not moved. tid and root_type are +// only used by hprof. +typedef void (RootCallback)(mirror::Object** root, void* arg, const RootInfo& root_info); + template<class MirrorType> class PACKED(4) GcRoot { public: template<ReadBarrierOption kReadBarrierOption = kWithReadBarrier> ALWAYS_INLINE MirrorType* Read() const SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); - void VisitRoot(RootCallback* callback, void* arg, uint32_t thread_id, RootType root_type) const { + void VisitRoot(RootCallback* callback, void* arg, const RootInfo& info) const { DCHECK(!IsNull()); - callback(reinterpret_cast<mirror::Object**>(&root_), arg, thread_id, root_type); + callback(reinterpret_cast<mirror::Object**>(&root_), arg, info); DCHECK(!IsNull()); } + void VisitRootIfNonNull(RootCallback* callback, void* arg, const RootInfo& info) const { + if (!IsNull()) { + VisitRoot(callback, arg, info); + } + } + // This is only used by IrtIterator. ALWAYS_INLINE MirrorType** AddressWithoutBarrier() { return &root_; diff --git a/runtime/hprof/hprof.cc b/runtime/hprof/hprof.cc index 1716d5e0e7..040757bdb1 100644 --- a/runtime/hprof/hprof.cc +++ b/runtime/hprof/hprof.cc @@ -44,6 +44,7 @@ #include "common_throws.h" #include "debugger.h" #include "dex_file-inl.h" +#include "gc_root.h" #include "gc/accounting/heap_bitmap.h" #include "gc/heap.h" #include "gc/space/space.h" @@ -456,13 +457,13 @@ class Hprof { EndianOutput* output; }; - static void RootVisitor(mirror::Object** obj, void* arg, uint32_t thread_id, RootType root_type) + static void RootVisitor(mirror::Object** obj, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { DCHECK(arg != nullptr); DCHECK(obj != nullptr); DCHECK(*obj != nullptr); Env* env = reinterpret_cast<Env*>(arg); - env->hprof->VisitRoot(*obj, thread_id, root_type, env->output); + env->hprof->VisitRoot(*obj, root_info, env->output); } static void VisitObjectCallback(mirror::Object* obj, void* arg) @@ -574,7 +575,7 @@ class Hprof { } } - void VisitRoot(const mirror::Object* obj, uint32_t thread_id, RootType type, EndianOutput* output) + void VisitRoot(const mirror::Object* obj, const RootInfo& root_info, EndianOutput* output) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); void MarkRootObject(const mirror::Object* obj, jobject jni_obj, HprofHeapTag heap_tag, uint32_t thread_serial, EndianOutput* output); @@ -1124,8 +1125,7 @@ void Hprof::DumpHeapInstanceObject(mirror::Object* obj, mirror::Class* klass, __ UpdateU4(size_patch_offset, output->Length() - (size_patch_offset + 4)); } -void Hprof::VisitRoot(const mirror::Object* obj, uint32_t thread_id, RootType type, - EndianOutput* output) { +void Hprof::VisitRoot(const mirror::Object* obj, const RootInfo& info, EndianOutput* output) { static const HprofHeapTag xlate[] = { HPROF_ROOT_UNKNOWN, HPROF_ROOT_JNI_GLOBAL, @@ -1143,11 +1143,11 @@ void Hprof::VisitRoot(const mirror::Object* obj, uint32_t thread_id, RootType ty HPROF_ROOT_VM_INTERNAL, HPROF_ROOT_JNI_MONITOR, }; - CHECK_LT(type, sizeof(xlate) / sizeof(HprofHeapTag)); + CHECK_LT(info.GetType(), sizeof(xlate) / sizeof(HprofHeapTag)); if (obj == nullptr) { return; } - MarkRootObject(obj, 0, xlate[type], thread_id, output); + MarkRootObject(obj, 0, xlate[info.GetType()], info.GetThreadId(), output); } // If "direct_to_ddms" is true, the other arguments are ignored, and data is diff --git a/runtime/indirect_reference_table.cc b/runtime/indirect_reference_table.cc index 0d84a1ef98..aa2a6b58f1 100644 --- a/runtime/indirect_reference_table.cc +++ b/runtime/indirect_reference_table.cc @@ -242,15 +242,15 @@ void IndirectReferenceTable::Trim() { madvise(release_start, release_end - release_start, MADV_DONTNEED); } -void IndirectReferenceTable::VisitRoots(RootCallback* callback, void* arg, uint32_t tid, - RootType root_type) { +void IndirectReferenceTable::VisitRoots(RootCallback* callback, void* arg, + const RootInfo& root_info) { for (auto ref : *this) { if (*ref == nullptr) { // Need to skip null entries to make it possible to do the // non-null check after the call back. continue; } - callback(ref, arg, tid, root_type); + callback(ref, arg, root_info); DCHECK(*ref != nullptr); } } diff --git a/runtime/indirect_reference_table.h b/runtime/indirect_reference_table.h index fbd5714688..7f7870a412 100644 --- a/runtime/indirect_reference_table.h +++ b/runtime/indirect_reference_table.h @@ -31,6 +31,8 @@ namespace art { +class RootInfo; + namespace mirror { class Object; } // namespace mirror @@ -316,7 +318,7 @@ class IndirectReferenceTable { return IrtIterator(table_, Capacity(), Capacity()); } - void VisitRoots(RootCallback* callback, void* arg, uint32_t tid, RootType root_type) + void VisitRoots(RootCallback* callback, void* arg, const RootInfo& root_info) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); uint32_t GetSegmentState() const { diff --git a/runtime/indirect_reference_table_test.cc b/runtime/indirect_reference_table_test.cc index 99ee597bb8..1156cf5996 100644 --- a/runtime/indirect_reference_table_test.cc +++ b/runtime/indirect_reference_table_test.cc @@ -43,6 +43,9 @@ static void CheckDump(IndirectReferenceTable* irt, size_t num_objects, size_t nu } TEST_F(IndirectReferenceTableTest, BasicTest) { + // This will lead to error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + ScopedObjectAccess soa(Thread::Current()); static const size_t kTableInitial = 10; static const size_t kTableMax = 20; diff --git a/runtime/instrumentation.cc b/runtime/instrumentation.cc index 6bc813faf9..1548cfd2ab 100644 --- a/runtime/instrumentation.cc +++ b/runtime/instrumentation.cc @@ -1053,7 +1053,7 @@ void Instrumentation::VisitRoots(RootCallback* callback, void* arg) { return; } for (auto pair : deoptimized_methods_) { - pair.second.VisitRoot(callback, arg, 0, kRootVMInternal); + pair.second.VisitRoot(callback, arg, RootInfo(kRootVMInternal)); } } diff --git a/runtime/intern_table.cc b/runtime/intern_table.cc index 7ecb58e7e9..f92f209306 100644 --- a/runtime/intern_table.cc +++ b/runtime/intern_table.cc @@ -60,7 +60,7 @@ void InternTable::VisitRoots(RootCallback* callback, void* arg, VisitRootFlags f } else if ((flags & kVisitRootFlagNewRoots) != 0) { for (auto& root : new_strong_intern_roots_) { mirror::String* old_ref = root.Read<kWithoutReadBarrier>(); - root.VisitRoot(callback, arg, 0, kRootInternedString); + root.VisitRoot(callback, arg, RootInfo(kRootInternedString)); mirror::String* new_ref = root.Read<kWithoutReadBarrier>(); if (new_ref != old_ref) { // The GC moved a root in the log. Need to search the strong interns and update the @@ -329,10 +329,10 @@ void InternTable::Table::Insert(mirror::String* s) { void InternTable::Table::VisitRoots(RootCallback* callback, void* arg) { for (auto& intern : pre_zygote_table_) { - intern.VisitRoot(callback, arg, 0, kRootInternedString); + intern.VisitRoot(callback, arg, RootInfo(kRootInternedString)); } for (auto& intern : post_zygote_table_) { - intern.VisitRoot(callback, arg, 0, kRootInternedString); + intern.VisitRoot(callback, arg, RootInfo(kRootInternedString)); } } diff --git a/runtime/java_vm_ext.cc b/runtime/java_vm_ext.cc index 7f677ab5d3..4643d145cc 100644 --- a/runtime/java_vm_ext.cc +++ b/runtime/java_vm_ext.cc @@ -764,10 +764,8 @@ void JavaVMExt::TrimGlobals() { void JavaVMExt::VisitRoots(RootCallback* callback, void* arg) { Thread* self = Thread::Current(); - { - ReaderMutexLock mu(self, globals_lock_); - globals_.VisitRoots(callback, arg, 0, kRootJNIGlobal); - } + ReaderMutexLock mu(self, globals_lock_); + globals_.VisitRoots(callback, arg, RootInfo(kRootJNIGlobal)); // The weak_globals table is visited by the GC itself (because it mutates the table). } diff --git a/runtime/jni_internal_test.cc b/runtime/jni_internal_test.cc index 8e329687c4..906aa4c1be 100644 --- a/runtime/jni_internal_test.cc +++ b/runtime/jni_internal_test.cc @@ -634,6 +634,9 @@ TEST_F(JniInternalTest, GetVersion) { } TEST_F(JniInternalTest, FindClass) { + // This tests leads to warnings in the log. + ScopedLogSeverity sls(LogSeverity::ERROR); + FindClassTest(false); FindClassTest(true); } @@ -890,40 +893,44 @@ TEST_F(JniInternalTest, RegisterAndUnregisterNatives) { // Sanity check that no exceptions are pending. ASSERT_FALSE(env_->ExceptionCheck()); - // Check that registering method without name causes a NoSuchMethodError. + // The following can print errors to the log we'd like to ignore. { - JNINativeMethod methods[] = { { nullptr, "()V", native_function } }; - EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); - } - ExpectException(jlnsme); + ScopedLogSeverity sls(LogSeverity::FATAL); + // Check that registering method without name causes a NoSuchMethodError. + { + JNINativeMethod methods[] = { { nullptr, "()V", native_function } }; + EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); + } + ExpectException(jlnsme); - // Check that registering method without signature causes a NoSuchMethodError. - { - JNINativeMethod methods[] = { { "notify", nullptr, native_function } }; - EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); - } - ExpectException(jlnsme); + // Check that registering method without signature causes a NoSuchMethodError. + { + JNINativeMethod methods[] = { { "notify", nullptr, native_function } }; + EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); + } + ExpectException(jlnsme); - // Check that registering method without function causes a NoSuchMethodError. - { - JNINativeMethod methods[] = { { "notify", "()V", nullptr } }; - EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); - } - ExpectException(jlnsme); + // Check that registering method without function causes a NoSuchMethodError. + { + JNINativeMethod methods[] = { { "notify", "()V", nullptr } }; + EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); + } + ExpectException(jlnsme); - // Check that registering to a non-existent java.lang.Object.foo() causes a NoSuchMethodError. - { - JNINativeMethod methods[] = { { "foo", "()V", native_function } }; - EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); - } - ExpectException(jlnsme); + // Check that registering to a non-existent java.lang.Object.foo() causes a NoSuchMethodError. + { + JNINativeMethod methods[] = { { "foo", "()V", native_function } }; + EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); + } + ExpectException(jlnsme); - // Check that registering non-native methods causes a NoSuchMethodError. - { - JNINativeMethod methods[] = { { "equals", "(Ljava/lang/Object;)Z", native_function } }; - EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); + // Check that registering non-native methods causes a NoSuchMethodError. + { + JNINativeMethod methods[] = { { "equals", "(Ljava/lang/Object;)Z", native_function } }; + EXPECT_EQ(env_->RegisterNatives(jlobject, methods, 1), JNI_ERR); + } + ExpectException(jlnsme); } - ExpectException(jlnsme); // Check that registering native methods is successful. { @@ -1707,6 +1714,9 @@ TEST_F(JniInternalTest, DeleteLocalRef_nullptr) { } TEST_F(JniInternalTest, DeleteLocalRef) { + // This tests leads to warnings and errors in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + jstring s = env_->NewStringUTF(""); ASSERT_NE(s, nullptr); env_->DeleteLocalRef(s); @@ -1743,6 +1753,9 @@ TEST_F(JniInternalTest, PushLocalFrame_10395422) { ASSERT_EQ(JNI_OK, env_->PushLocalFrame(0)); env_->PopLocalFrame(nullptr); + // The following two tests will print errors to the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + // Negative capacities are not allowed. ASSERT_EQ(JNI_ERR, env_->PushLocalFrame(-1)); @@ -1751,6 +1764,9 @@ TEST_F(JniInternalTest, PushLocalFrame_10395422) { } TEST_F(JniInternalTest, PushLocalFrame_PopLocalFrame) { + // This tests leads to errors in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + jobject original = env_->NewStringUTF(""); ASSERT_NE(original, nullptr); @@ -1815,6 +1831,9 @@ TEST_F(JniInternalTest, DeleteGlobalRef_nullptr) { } TEST_F(JniInternalTest, DeleteGlobalRef) { + // This tests leads to warnings and errors in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + jstring s = env_->NewStringUTF(""); ASSERT_NE(s, nullptr); @@ -1865,6 +1884,9 @@ TEST_F(JniInternalTest, DeleteWeakGlobalRef_nullptr) { } TEST_F(JniInternalTest, DeleteWeakGlobalRef) { + // This tests leads to warnings and errors in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + jstring s = env_->NewStringUTF(""); ASSERT_NE(s, nullptr); @@ -1989,6 +2011,9 @@ TEST_F(JniInternalTest, NewDirectBuffer_GetDirectBufferAddress_GetDirectBufferCa } TEST_F(JniInternalTest, MonitorEnterExit) { + // This will print some error messages. Suppress. + ScopedLogSeverity sls(LogSeverity::FATAL); + // Create an object to torture. jclass object_class = env_->FindClass("java/lang/Object"); ASSERT_NE(object_class, nullptr); diff --git a/runtime/mirror/array-inl.h b/runtime/mirror/array-inl.h index 4dddd38b80..048d8ba08f 100644 --- a/runtime/mirror/array-inl.h +++ b/runtime/mirror/array-inl.h @@ -200,9 +200,7 @@ inline Array* Array::Alloc(Thread* self, Class* array_class, int32_t component_c template<class T> inline void PrimitiveArray<T>::VisitRoots(RootCallback* callback, void* arg) { - if (!array_class_.IsNull()) { - array_class_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + array_class_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } template<typename T> diff --git a/runtime/mirror/art_field.cc b/runtime/mirror/art_field.cc index 7e20076112..5a4ebd1f6e 100644 --- a/runtime/mirror/art_field.cc +++ b/runtime/mirror/art_field.cc @@ -56,9 +56,7 @@ void ArtField::SetOffset(MemberOffset num_bytes) { } void ArtField::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_reflect_ArtField_.IsNull()) { - java_lang_reflect_ArtField_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_reflect_ArtField_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } // TODO: we could speed up the search if fields are ordered by offsets. diff --git a/runtime/mirror/art_method.cc b/runtime/mirror/art_method.cc index ff3822a173..288f6a60bb 100644 --- a/runtime/mirror/art_method.cc +++ b/runtime/mirror/art_method.cc @@ -60,9 +60,7 @@ ArtMethod* ArtMethod::FromReflectedMethod(const ScopedObjectAccessAlreadyRunnabl void ArtMethod::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_reflect_ArtMethod_.IsNull()) { - java_lang_reflect_ArtMethod_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_reflect_ArtMethod_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } mirror::String* ArtMethod::GetNameAsString(Thread* self) { diff --git a/runtime/mirror/class.cc b/runtime/mirror/class.cc index bd3bfbf9fe..ae684b162c 100644 --- a/runtime/mirror/class.cc +++ b/runtime/mirror/class.cc @@ -52,9 +52,7 @@ void Class::ResetClass() { } void Class::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_Class_.IsNull()) { - java_lang_Class_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_Class_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } void Class::SetStatus(Status new_status, Thread* self) { diff --git a/runtime/mirror/reference.cc b/runtime/mirror/reference.cc index c36bd980f9..35130e8b88 100644 --- a/runtime/mirror/reference.cc +++ b/runtime/mirror/reference.cc @@ -33,9 +33,7 @@ void Reference::ResetClass() { } void Reference::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_ref_Reference_.IsNull()) { - java_lang_ref_Reference_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_ref_Reference_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } } // namespace mirror diff --git a/runtime/mirror/stack_trace_element.cc b/runtime/mirror/stack_trace_element.cc index 1eb20f71a6..c2a67e809a 100644 --- a/runtime/mirror/stack_trace_element.cc +++ b/runtime/mirror/stack_trace_element.cc @@ -68,9 +68,7 @@ void StackTraceElement::Init(Handle<String> declaring_class, Handle<String> meth } void StackTraceElement::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_StackTraceElement_.IsNull()) { - java_lang_StackTraceElement_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_StackTraceElement_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } diff --git a/runtime/mirror/string.cc b/runtime/mirror/string.cc index 01599ae907..e199d0e2ef 100644 --- a/runtime/mirror/string.cc +++ b/runtime/mirror/string.cc @@ -224,9 +224,7 @@ int32_t String::CompareTo(String* rhs) { } void String::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_String_.IsNull()) { - java_lang_String_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_String_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } } // namespace mirror diff --git a/runtime/mirror/throwable.cc b/runtime/mirror/throwable.cc index 93ed4d4daf..61d85e2fe2 100644 --- a/runtime/mirror/throwable.cc +++ b/runtime/mirror/throwable.cc @@ -138,9 +138,7 @@ void Throwable::ResetClass() { } void Throwable::VisitRoots(RootCallback* callback, void* arg) { - if (!java_lang_Throwable_.IsNull()) { - java_lang_Throwable_.VisitRoot(callback, arg, 0, kRootStickyClass); - } + java_lang_Throwable_.VisitRootIfNonNull(callback, arg, RootInfo(kRootStickyClass)); } } // namespace mirror diff --git a/runtime/monitor_test.cc b/runtime/monitor_test.cc index adc7848ae0..6d1e721bb6 100644 --- a/runtime/monitor_test.cc +++ b/runtime/monitor_test.cc @@ -356,6 +356,8 @@ static void CommonWaitSetup(MonitorTest* test, ClassLinker* class_linker, uint64 TEST_F(MonitorTest, CheckExceptionsWait1) { // Make the CreateTask wait 10ms, the UseTask wait 10ms. // => The use task will get the lock first and get to self == owner check. + // This will lead to OOM and monitor error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); CommonWaitSetup(this, class_linker_, 10, 50, false, false, 2, 50, true, "Monitor test thread pool 1"); } @@ -364,6 +366,8 @@ TEST_F(MonitorTest, CheckExceptionsWait1) { TEST_F(MonitorTest, CheckExceptionsWait2) { // Make the CreateTask wait 0ms, the UseTask wait 10ms. // => The create task will get the lock first and get to ms >= 0 + // This will lead to OOM and monitor error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); CommonWaitSetup(this, class_linker_, 0, -1, true, false, 10, 50, true, "Monitor test thread pool 2"); } @@ -373,6 +377,8 @@ TEST_F(MonitorTest, CheckExceptionsWait3) { // Make the CreateTask wait 0ms, then Wait for a long time. Make the InterruptTask wait 10ms, // after which it will interrupt the create task and then wait another 10ms. // => The create task will get to the interrupted-exception throw. + // This will lead to OOM and monitor error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); CommonWaitSetup(this, class_linker_, 0, 500, true, true, 10, 50, true, "Monitor test thread pool 3"); } diff --git a/runtime/native/dalvik_system_VMRuntime.cc b/runtime/native/dalvik_system_VMRuntime.cc index 471aa9c034..599d97fb51 100644 --- a/runtime/native/dalvik_system_VMRuntime.cc +++ b/runtime/native/dalvik_system_VMRuntime.cc @@ -249,7 +249,7 @@ static void VMRuntime_runHeapTasks(JNIEnv* env, jobject) { typedef std::map<std::string, mirror::String*> StringTable; static void PreloadDexCachesStringsCallback(mirror::Object** root, void* arg, - uint32_t /*thread_id*/, RootType /*root_type*/) + const RootInfo& /*root_info*/) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { StringTable& table = *reinterpret_cast<StringTable*>(arg); mirror::String* string = const_cast<mirror::Object*>(*root)->AsString(); diff --git a/runtime/oat_file.cc b/runtime/oat_file.cc index 358519b7af..9061bb3d55 100644 --- a/runtime/oat_file.cc +++ b/runtime/oat_file.cc @@ -456,7 +456,7 @@ size_t OatFile::OatDexFile::FileSize() const { std::unique_ptr<const DexFile> OatFile::OatDexFile::OpenDexFile(std::string* error_msg) const { return DexFile::Open(dex_file_pointer_, FileSize(), dex_file_location_, - dex_file_location_checksum_, error_msg); + dex_file_location_checksum_, GetOatFile(), error_msg); } uint32_t OatFile::OatDexFile::GetOatClassOffset(uint16_t class_def_index) const { diff --git a/runtime/object_callbacks.h b/runtime/object_callbacks.h index 592deed1a7..cf81cc5093 100644 --- a/runtime/object_callbacks.h +++ b/runtime/object_callbacks.h @@ -35,34 +35,10 @@ namespace mirror { } // namespace mirror class StackVisitor; -enum RootType { - kRootUnknown = 0, - kRootJNIGlobal, - kRootJNILocal, - kRootJavaFrame, - kRootNativeStack, - kRootStickyClass, - kRootThreadBlock, - kRootMonitorUsed, - kRootThreadObject, - kRootInternedString, - kRootDebugger, - kRootVMInternal, - kRootJNIMonitor, -}; -std::ostream& operator<<(std::ostream& os, const RootType& root_type); - -// Returns the new address of the object, returns root if it has not moved. tid and root_type are -// only used by hprof. -typedef void (RootCallback)(mirror::Object** root, void* arg, uint32_t thread_id, - RootType root_type); // A callback for visiting an object in the heap. typedef void (ObjectCallback)(mirror::Object* obj, void* arg); // A callback used for marking an object, returns the new address of the object if the object moved. typedef mirror::Object* (MarkObjectCallback)(mirror::Object* obj, void* arg) WARN_UNUSED; -// A callback for verifying roots. -typedef void (VerifyRootCallback)(const mirror::Object* root, void* arg, size_t vreg, - const StackVisitor* visitor, RootType root_type); typedef void (MarkHeapReferenceCallback)(mirror::HeapReference<mirror::Object>* ref, void* arg); typedef void (DelayReferenceReferentCallback)(mirror::Class* klass, mirror::Reference* ref, void* arg); diff --git a/runtime/quick/inline_method_analyser.h b/runtime/quick/inline_method_analyser.h index 72b696b2d5..34630250cf 100644 --- a/runtime/quick/inline_method_analyser.h +++ b/runtime/quick/inline_method_analyser.h @@ -103,6 +103,9 @@ enum IntrinsicFlags { kIntrinsicFlagIsObject = 4, // kIntrinsicUnsafePut kIntrinsicFlagIsOrdered = 8, + + // kIntrinsicDoubleCvt, kIntrinsicFloatCvt. + kIntrinsicFlagToFloatingPoint = kIntrinsicFlagMin, }; struct InlineIGetIPutData { diff --git a/runtime/reference_table.cc b/runtime/reference_table.cc index c917d844ae..e454b20d76 100644 --- a/runtime/reference_table.cc +++ b/runtime/reference_table.cc @@ -232,10 +232,9 @@ void ReferenceTable::Dump(std::ostream& os, Table& entries) { DumpSummaryLine(os, prev, GetElementCount(prev), identical, equiv); } -void ReferenceTable::VisitRoots(RootCallback* visitor, void* arg, uint32_t tid, - RootType root_type) { +void ReferenceTable::VisitRoots(RootCallback* visitor, void* arg, const RootInfo& root_info) { for (GcRoot<mirror::Object>& root : entries_) { - root.VisitRoot(visitor, arg, tid, root_type); + root.VisitRoot(visitor, arg, root_info); } } diff --git a/runtime/reference_table.h b/runtime/reference_table.h index 6cffa85d7f..22cf1cd804 100644 --- a/runtime/reference_table.h +++ b/runtime/reference_table.h @@ -49,7 +49,7 @@ class ReferenceTable { void Dump(std::ostream& os) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); - void VisitRoots(RootCallback* visitor, void* arg, uint32_t tid, RootType root_type); + void VisitRoots(RootCallback* visitor, void* arg, const RootInfo& root_info); private: typedef std::vector<GcRoot<mirror::Object>, diff --git a/runtime/runtime.cc b/runtime/runtime.cc index fabbbfb9ed..9dddf2f18f 100644 --- a/runtime/runtime.cc +++ b/runtime/runtime.cc @@ -40,6 +40,8 @@ #include "arch/instruction_set_features.h" #include "arch/mips/quick_method_frame_info_mips.h" #include "arch/mips/registers_mips.h" +#include "arch/mips64/quick_method_frame_info_mips64.h" +#include "arch/mips64/registers_mips64.h" #include "arch/x86/quick_method_frame_info_x86.h" #include "arch/x86/registers_x86.h" #include "arch/x86_64/quick_method_frame_info_x86_64.h" @@ -1219,33 +1221,15 @@ void Runtime::VisitConcurrentRoots(RootCallback* callback, void* arg, VisitRootF void Runtime::VisitNonThreadRoots(RootCallback* callback, void* arg) { java_vm_->VisitRoots(callback, arg); - if (!sentinel_.IsNull()) { - sentinel_.VisitRoot(callback, arg, 0, kRootVMInternal); - DCHECK(!sentinel_.IsNull()); - } - if (!pre_allocated_OutOfMemoryError_.IsNull()) { - pre_allocated_OutOfMemoryError_.VisitRoot(callback, arg, 0, kRootVMInternal); - DCHECK(!pre_allocated_OutOfMemoryError_.IsNull()); - } - resolution_method_.VisitRoot(callback, arg, 0, kRootVMInternal); - DCHECK(!resolution_method_.IsNull()); - if (!pre_allocated_NoClassDefFoundError_.IsNull()) { - pre_allocated_NoClassDefFoundError_.VisitRoot(callback, arg, 0, kRootVMInternal); - DCHECK(!pre_allocated_NoClassDefFoundError_.IsNull()); - } - if (HasImtConflictMethod()) { - imt_conflict_method_.VisitRoot(callback, arg, 0, kRootVMInternal); - } - if (!imt_unimplemented_method_.IsNull()) { - imt_unimplemented_method_.VisitRoot(callback, arg, 0, kRootVMInternal); - } - if (HasDefaultImt()) { - default_imt_.VisitRoot(callback, arg, 0, kRootVMInternal); - } + sentinel_.VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); + pre_allocated_OutOfMemoryError_.VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); + resolution_method_.VisitRoot(callback, arg, RootInfo(kRootVMInternal)); + pre_allocated_NoClassDefFoundError_.VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); + imt_conflict_method_.VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); + imt_unimplemented_method_.VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); + default_imt_.VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); for (int i = 0; i < Runtime::kLastCalleeSaveType; i++) { - if (!callee_save_methods_[i].IsNull()) { - callee_save_methods_[i].VisitRoot(callback, arg, 0, kRootVMInternal); - } + callee_save_methods_[i].VisitRootIfNonNull(callback, arg, RootInfo(kRootVMInternal)); } verifier::MethodVerifier::VisitStaticRoots(callback, arg); { @@ -1356,6 +1340,11 @@ void Runtime::SetInstructionSet(InstructionSet instruction_set) { CalleeSaveType type = static_cast<CalleeSaveType>(i); callee_save_method_frame_infos_[i] = mips::MipsCalleeSaveMethodFrameInfo(type); } + } else if (instruction_set_ == kMips64) { + for (int i = 0; i != kLastCalleeSaveType; ++i) { + CalleeSaveType type = static_cast<CalleeSaveType>(i); + callee_save_method_frame_infos_[i] = mips64::Mips64CalleeSaveMethodFrameInfo(type); + } } else if (instruction_set_ == kX86) { for (int i = 0; i != kLastCalleeSaveType; ++i) { CalleeSaveType type = static_cast<CalleeSaveType>(i); diff --git a/runtime/runtime_linux.cc b/runtime/runtime_linux.cc index a0adcd1082..35d944f1e6 100644 --- a/runtime/runtime_linux.cc +++ b/runtime/runtime_linux.cc @@ -25,6 +25,7 @@ #include "base/dumpable.h" #include "base/logging.h" +#include "base/macros.h" #include "base/mutex.h" #include "base/stringprintf.h" #include "thread-inl.h" @@ -34,6 +35,7 @@ namespace art { static constexpr bool kDumpHeapObjectOnSigsevg = false; +static constexpr bool kUseSigRTTimeout = true; struct Backtrace { public: @@ -284,8 +286,15 @@ struct UContext { mcontext_t& context; }; +// Return the signal number we recognize as timeout. -1 means not active/supported. static int GetTimeoutSignal() { - return SIGRTMIN + 2; +#if defined(__APPLE__) + // Mac does not support realtime signals. + UNUSED(kUseSigRTTimeout); + return -1; +#else + return kUseSigRTTimeout ? (SIGRTMIN + 2) : -1; +#endif } static bool IsTimeoutSignal(int signal_number) { @@ -392,7 +401,9 @@ void Runtime::InitPlatformSignalHandlers() { #endif rc += sigaction(SIGTRAP, &action, NULL); // Special dump-all timeout. - rc += sigaction(GetTimeoutSignal(), &action, NULL); + if (GetTimeoutSignal() != -1) { + rc += sigaction(GetTimeoutSignal(), &action, NULL); + } CHECK_EQ(rc, 0); } diff --git a/runtime/stack.cc b/runtime/stack.cc index aaa5b898b3..3165898e8c 100644 --- a/runtime/stack.cc +++ b/runtime/stack.cc @@ -614,4 +614,11 @@ void StackVisitor::WalkStack(bool include_transitions) { } } +void JavaFrameRootInfo::Describe(std::ostream& os) const { + const StackVisitor* visitor = stack_visitor_; + CHECK(visitor != nullptr); + os << "Type=" << GetType() << " thread_id=" << GetThreadId() << " location=" << + visitor->DescribeLocation() << " vreg=" << vreg_; +} + } // namespace art diff --git a/runtime/stack.h b/runtime/stack.h index 15007af85a..233e1c36a8 100644 --- a/runtime/stack.h +++ b/runtime/stack.h @@ -22,6 +22,7 @@ #include "arch/instruction_set.h" #include "dex_file.h" +#include "gc_root.h" #include "mirror/object_reference.h" #include "throw_location.h" #include "utils.h" @@ -314,6 +315,19 @@ class ShadowFrame { DISALLOW_IMPLICIT_CONSTRUCTORS(ShadowFrame); }; +class JavaFrameRootInfo : public RootInfo { + public: + JavaFrameRootInfo(uint32_t thread_id, const StackVisitor* stack_visitor, size_t vreg) + : RootInfo(kRootJavaFrame, thread_id), stack_visitor_(stack_visitor), vreg_(vreg) { + } + virtual void Describe(std::ostream& os) const OVERRIDE + SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); + + private: + const StackVisitor* const stack_visitor_; + const size_t vreg_; +}; + // The managed stack is used to record fragments of managed code stacks. Managed code stacks // may either be shadow frames or lists of frames using fixed frame sizes. Transition records are // necessary for transitions between code using different frame layouts and transitions into native diff --git a/runtime/thread.cc b/runtime/thread.cc index 6a1aeb56ba..78a8bf81d7 100644 --- a/runtime/thread.cc +++ b/runtime/thread.cc @@ -1151,8 +1151,7 @@ void Thread::AssertNoPendingExceptionForNewException(const char* msg) const { } } -static void MonitorExitVisitor(mirror::Object** object, void* arg, uint32_t /*thread_id*/, - RootType /*root_type*/) +static void MonitorExitVisitor(mirror::Object** object, void* arg, const RootInfo& /*root_info*/) NO_THREAD_SAFETY_ANALYSIS { Thread* self = reinterpret_cast<Thread*>(arg); mirror::Object* entered_monitor = *object; @@ -1171,7 +1170,7 @@ void Thread::Destroy() { if (tlsPtr_.jni_env != nullptr) { // On thread detach, all monitors entered with JNI MonitorEnter are automatically exited. - tlsPtr_.jni_env->monitors.VisitRoots(MonitorExitVisitor, self, 0, kRootVMInternal); + tlsPtr_.jni_env->monitors.VisitRoots(MonitorExitVisitor, self, RootInfo(kRootVMInternal)); // Release locally held global references which releasing may require the mutator lock. if (tlsPtr_.jpeer != nullptr) { // If pthread_create fails we don't have a jni env here. @@ -1333,7 +1332,7 @@ void Thread::HandleScopeVisitRoots(RootCallback* visitor, void* arg, uint32_t th mirror::Object* object = cur->GetReference(j); if (object != nullptr) { mirror::Object* old_obj = object; - visitor(&object, arg, thread_id, kRootNativeStack); + visitor(&object, arg, RootInfo(kRootNativeStack, thread_id)); if (old_obj != object) { cur->SetReference(j, object); } @@ -2219,8 +2218,8 @@ class RootCallbackVisitor { RootCallbackVisitor(RootCallback* callback, void* arg, uint32_t tid) : callback_(callback), arg_(arg), tid_(tid) {} - void operator()(mirror::Object** obj, size_t, const StackVisitor*) const { - callback_(obj, arg_, tid_, kRootJavaFrame); + void operator()(mirror::Object** obj, size_t vreg, const StackVisitor* stack_visitor) const { + callback_(obj, arg_, JavaFrameRootInfo(tid_, stack_visitor, vreg)); } private: @@ -2232,23 +2231,24 @@ class RootCallbackVisitor { void Thread::VisitRoots(RootCallback* visitor, void* arg) { uint32_t thread_id = GetThreadId(); if (tlsPtr_.opeer != nullptr) { - visitor(&tlsPtr_.opeer, arg, thread_id, kRootThreadObject); + visitor(&tlsPtr_.opeer, arg, RootInfo(kRootThreadObject, thread_id)); } if (tlsPtr_.exception != nullptr && tlsPtr_.exception != GetDeoptimizationException()) { - visitor(reinterpret_cast<mirror::Object**>(&tlsPtr_.exception), arg, thread_id, kRootNativeStack); + visitor(reinterpret_cast<mirror::Object**>(&tlsPtr_.exception), arg, + RootInfo(kRootNativeStack, thread_id)); } tlsPtr_.throw_location.VisitRoots(visitor, arg); if (tlsPtr_.monitor_enter_object != nullptr) { - visitor(&tlsPtr_.monitor_enter_object, arg, thread_id, kRootNativeStack); + visitor(&tlsPtr_.monitor_enter_object, arg, RootInfo(kRootNativeStack, thread_id)); } - tlsPtr_.jni_env->locals.VisitRoots(visitor, arg, thread_id, kRootJNILocal); - tlsPtr_.jni_env->monitors.VisitRoots(visitor, arg, thread_id, kRootJNIMonitor); + tlsPtr_.jni_env->locals.VisitRoots(visitor, arg, RootInfo(kRootJNILocal, thread_id)); + tlsPtr_.jni_env->monitors.VisitRoots(visitor, arg, RootInfo(kRootJNIMonitor, thread_id)); HandleScopeVisitRoots(visitor, arg, thread_id); if (tlsPtr_.debug_invoke_req != nullptr) { - tlsPtr_.debug_invoke_req->VisitRoots(visitor, arg, thread_id, kRootDebugger); + tlsPtr_.debug_invoke_req->VisitRoots(visitor, arg, RootInfo(kRootDebugger, thread_id)); } if (tlsPtr_.single_step_control != nullptr) { - tlsPtr_.single_step_control->VisitRoots(visitor, arg, thread_id, kRootDebugger); + tlsPtr_.single_step_control->VisitRoots(visitor, arg, RootInfo(kRootDebugger, thread_id)); } if (tlsPtr_.deoptimization_shadow_frame != nullptr) { RootCallbackVisitor visitorToCallback(visitor, arg, thread_id); @@ -2259,8 +2259,8 @@ void Thread::VisitRoots(RootCallback* visitor, void* arg) { } } if (tlsPtr_.shadow_frame_under_construction != nullptr) { - RootCallbackVisitor visitorToCallback(visitor, arg, thread_id); - ReferenceMapVisitor<RootCallbackVisitor> mapper(this, nullptr, visitorToCallback); + RootCallbackVisitor visitor_to_callback(visitor, arg, thread_id); + ReferenceMapVisitor<RootCallbackVisitor> mapper(this, nullptr, visitor_to_callback); for (ShadowFrame* shadow_frame = tlsPtr_.shadow_frame_under_construction; shadow_frame != nullptr; shadow_frame = shadow_frame->GetLink()) { @@ -2269,21 +2269,22 @@ void Thread::VisitRoots(RootCallback* visitor, void* arg) { } // Visit roots on this thread's stack Context* context = GetLongJumpContext(); - RootCallbackVisitor visitorToCallback(visitor, arg, thread_id); - ReferenceMapVisitor<RootCallbackVisitor> mapper(this, context, visitorToCallback); + RootCallbackVisitor visitor_to_callback(visitor, arg, thread_id); + ReferenceMapVisitor<RootCallbackVisitor> mapper(this, context, visitor_to_callback); mapper.WalkStack(); ReleaseLongJumpContext(context); for (instrumentation::InstrumentationStackFrame& frame : *GetInstrumentationStack()) { if (frame.this_object_ != nullptr) { - visitor(&frame.this_object_, arg, thread_id, kRootJavaFrame); + visitor(&frame.this_object_, arg, RootInfo(kRootVMInternal, thread_id)); } DCHECK(frame.method_ != nullptr); - visitor(reinterpret_cast<mirror::Object**>(&frame.method_), arg, thread_id, kRootJavaFrame); + visitor(reinterpret_cast<mirror::Object**>(&frame.method_), arg, + RootInfo(kRootVMInternal, thread_id)); } } -static void VerifyRoot(mirror::Object** root, void* /*arg*/, uint32_t /*thread_id*/, - RootType /*root_type*/) SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { +static void VerifyRoot(mirror::Object** root, void* /*arg*/, const RootInfo& /*root_info*/) + SHARED_LOCKS_REQUIRED(Locks::mutator_lock_) { VerifyObject(*root); } diff --git a/runtime/thread_list.cc b/runtime/thread_list.cc index 0f6488342e..6ec40d46d7 100644 --- a/runtime/thread_list.cc +++ b/runtime/thread_list.cc @@ -1045,28 +1045,6 @@ void ThreadList::VisitRoots(RootCallback* callback, void* arg) const { } } -class VerifyRootWrapperArg { - public: - VerifyRootWrapperArg(VerifyRootCallback* callback, void* arg) : callback_(callback), arg_(arg) { - } - VerifyRootCallback* const callback_; - void* const arg_; -}; - -static void VerifyRootWrapperCallback(mirror::Object** root, void* arg, uint32_t /*thread_id*/, - RootType root_type) { - VerifyRootWrapperArg* wrapperArg = reinterpret_cast<VerifyRootWrapperArg*>(arg); - wrapperArg->callback_(*root, wrapperArg->arg_, 0, NULL, root_type); -} - -void ThreadList::VerifyRoots(VerifyRootCallback* callback, void* arg) const { - VerifyRootWrapperArg wrapper(callback, arg); - MutexLock mu(Thread::Current(), *Locks::thread_list_lock_); - for (const auto& thread : list_) { - thread->VisitRoots(VerifyRootWrapperCallback, &wrapper); - } -} - uint32_t ThreadList::AllocThreadId(Thread* self) { MutexLock mu(self, *Locks::allocated_thread_ids_lock_); for (size_t i = 0; i < allocated_ids_.size(); ++i) { diff --git a/runtime/thread_list.h b/runtime/thread_list.h index 43c065ae0a..6751bf5a86 100644 --- a/runtime/thread_list.h +++ b/runtime/thread_list.h @@ -19,6 +19,7 @@ #include "base/histogram.h" #include "base/mutex.h" +#include "gc_root.h" #include "jni.h" #include "object_callbacks.h" @@ -125,9 +126,6 @@ class ThreadList { void VisitRoots(RootCallback* callback, void* arg) const SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); - void VerifyRoots(VerifyRootCallback* callback, void* arg) const - SHARED_LOCKS_REQUIRED(Locks::mutator_lock_); - // Return a copy of the thread list. std::list<Thread*> GetList() EXCLUSIVE_LOCKS_REQUIRED(Locks::thread_list_lock_) { return list_; diff --git a/runtime/throw_location.cc b/runtime/throw_location.cc index 04abe64453..4d2aec088e 100644 --- a/runtime/throw_location.cc +++ b/runtime/throw_location.cc @@ -34,11 +34,11 @@ std::string ThrowLocation::Dump() const { void ThrowLocation::VisitRoots(RootCallback* visitor, void* arg) { if (this_object_ != nullptr) { - visitor(&this_object_, arg, 0, kRootVMInternal); + visitor(&this_object_, arg, RootInfo(kRootVMInternal)); DCHECK(this_object_ != nullptr); } if (method_ != nullptr) { - visitor(reinterpret_cast<mirror::Object**>(&method_), arg, 0, kRootVMInternal); + visitor(reinterpret_cast<mirror::Object**>(&method_), arg, RootInfo(kRootVMInternal)); DCHECK(method_ != nullptr); } } diff --git a/runtime/throw_location.h b/runtime/throw_location.h index b36eb67f9c..bec0da490a 100644 --- a/runtime/throw_location.h +++ b/runtime/throw_location.h @@ -20,6 +20,7 @@ #include "object_callbacks.h" #include "base/macros.h" #include "base/mutex.h" +#include "gc_root.h" #include <stdint.h> #include <string> diff --git a/runtime/transaction.cc b/runtime/transaction.cc index 478066f018..118c1a293a 100644 --- a/runtime/transaction.cc +++ b/runtime/transaction.cc @@ -206,7 +206,7 @@ void Transaction::VisitObjectLogs(RootCallback* callback, void* arg) { it.second.VisitRoots(callback, arg); mirror::Object* old_root = it.first; mirror::Object* new_root = old_root; - callback(&new_root, arg, 0, kRootUnknown); + callback(&new_root, arg, RootInfo(kRootUnknown)); if (new_root != old_root) { moving_roots.push_back(std::make_pair(old_root, new_root)); } @@ -233,7 +233,7 @@ void Transaction::VisitArrayLogs(RootCallback* callback, void* arg) { mirror::Array* old_root = it.first; CHECK(!old_root->IsObjectArray()); mirror::Array* new_root = old_root; - callback(reinterpret_cast<mirror::Object**>(&new_root), arg, 0, kRootUnknown); + callback(reinterpret_cast<mirror::Object**>(&new_root), arg, RootInfo(kRootUnknown)); if (new_root != old_root) { moving_roots.push_back(std::make_pair(old_root, new_root)); } @@ -396,7 +396,7 @@ void Transaction::ObjectLog::VisitRoots(RootCallback* callback, void* arg) { mirror::Object* obj = reinterpret_cast<mirror::Object*>(static_cast<uintptr_t>(field_value.value)); if (obj != nullptr) { - callback(&obj, arg, 0, kRootUnknown); + callback(&obj, arg, RootInfo(kRootUnknown)); field_value.value = reinterpret_cast<uintptr_t>(obj); } } @@ -441,7 +441,7 @@ void Transaction::InternStringLog::Undo(InternTable* intern_table) { } void Transaction::InternStringLog::VisitRoots(RootCallback* callback, void* arg) { - callback(reinterpret_cast<mirror::Object**>(&str_), arg, 0, kRootInternedString); + callback(reinterpret_cast<mirror::Object**>(&str_), arg, RootInfo(kRootInternedString)); } void Transaction::ArrayLog::LogValue(size_t index, uint64_t value) { diff --git a/runtime/transaction.h b/runtime/transaction.h index 566f231de6..8c82847683 100644 --- a/runtime/transaction.h +++ b/runtime/transaction.h @@ -20,6 +20,7 @@ #include "base/macros.h" #include "base/mutex.h" #include "base/value_object.h" +#include "gc_root.h" #include "object_callbacks.h" #include "offsets.h" #include "primitive.h" diff --git a/runtime/utils.cc b/runtime/utils.cc index d7d4ec2073..908cfbd27f 100644 --- a/runtime/utils.cc +++ b/runtime/utils.cc @@ -1208,7 +1208,7 @@ void DumpNativeStack(std::ostream& os, pid_t tid, const char* prefix, if (kUseAddr2line) { // Try to run it to see whether we have it. Push an argument so that it doesn't assume a.out // and print to stderr. - use_addr2line = RunCommand("addr2line -h", nullptr, nullptr); + use_addr2line = (gAborting > 0) && RunCommand("addr2line -h", nullptr, nullptr); } else { use_addr2line = false; } diff --git a/runtime/utils_test.cc b/runtime/utils_test.cc index a98bc909f2..a3dd13c661 100644 --- a/runtime/utils_test.cc +++ b/runtime/utils_test.cc @@ -392,6 +392,9 @@ TEST_F(UtilsTest, ExecSuccess) { } TEST_F(UtilsTest, ExecError) { + // This will lead to error messages in the log. + ScopedLogSeverity sls(LogSeverity::FATAL); + std::vector<std::string> command; command.push_back("bogus"); std::string error_msg; diff --git a/runtime/verifier/reg_type.cc b/runtime/verifier/reg_type.cc index 41541b5c86..3510665193 100644 --- a/runtime/verifier/reg_type.cc +++ b/runtime/verifier/reg_type.cc @@ -779,9 +779,7 @@ void RegType::CheckInvariants() const { } void RegType::VisitRoots(RootCallback* callback, void* arg) const { - if (!klass_.IsNull()) { - callback(reinterpret_cast<mirror::Object**>(&klass_), arg, 0, kRootUnknown); - } + klass_.VisitRootIfNonNull(callback, arg, RootInfo(kRootUnknown)); } void UninitializedThisReferenceType::CheckInvariants() const { diff --git a/runtime/vmap_table.h b/runtime/vmap_table.h index df5cd80e97..db9e1ea5cb 100644 --- a/runtime/vmap_table.h +++ b/runtime/vmap_table.h @@ -65,7 +65,7 @@ class VmapTable { uint16_t adjusted_vreg = vreg + kEntryAdjustment; size_t end = DecodeUnsignedLeb128(&table); bool high_reg = (kind == kLongHiVReg) || (kind == kDoubleHiVReg); - bool target64 = (kRuntimeISA == kArm64) || (kRuntimeISA == kX86_64); + bool target64 = (kRuntimeISA == kArm64) || (kRuntimeISA == kX86_64) || (kRuntimeISA == kMips64); if (target64 && high_reg) { // Wide promoted registers are associated with the sreg of the low portion. adjusted_vreg--; diff --git a/test/082-inline-execute/src/Main.java b/test/082-inline-execute/src/Main.java index 56972ff216..862fe066ce 100644 --- a/test/082-inline-execute/src/Main.java +++ b/test/082-inline-execute/src/Main.java @@ -119,6 +119,9 @@ public class Main { } } + // Break up the charAt tests. The optimizing compiler doesn't optimize methods with try-catch yet, + // so we need to separate out the tests that are expected to throw exception + public static void test_String_charAt() { String testStr = "Now is the time"; @@ -127,6 +130,12 @@ public class Main { Assert.assertEquals(' ', testStr.charAt(10)); Assert.assertEquals('e', testStr.charAt(testStr.length()-1)); + test_String_charAtExc(); + test_String_charAtExc2(); + } + + private static void test_String_charAtExc() { + String testStr = "Now is the time"; try { testStr.charAt(-1); Assert.fail(); @@ -146,6 +155,19 @@ public class Main { } } + private static void test_String_charAtExc2() { + try { + test_String_charAtExc3(); + Assert.fail(); + } catch (StringIndexOutOfBoundsException expected) { + } + } + + private static void test_String_charAtExc3() { + String testStr = "Now is the time"; + Assert.assertEquals('N', testStr.charAt(-1)); + } + static int start; private static int[] negIndex = { -100000 }; public static void test_String_indexOf() { diff --git a/test/114-ParallelGC/src/Main.java b/test/114-ParallelGC/src/Main.java index 8e2519dd0a..48f9bd363f 100644 --- a/test/114-ParallelGC/src/Main.java +++ b/test/114-ParallelGC/src/Main.java @@ -24,7 +24,10 @@ import java.util.concurrent.TimeoutException; public class Main implements Runnable { - public final static long TIMEOUT_VALUE = 5; // Timeout in minutes. + // Timeout in minutes. Make it larger than the run-test timeout to get a native thread dump by + // ART on timeout when running on the host. + public final static long TIMEOUT_VALUE = 12; + public final static long MAX_SIZE = 1000; // Maximum size of array-list to allocate. public static void main(String[] args) throws Exception { diff --git a/test/131-structural-change/build b/test/131-structural-change/build new file mode 100755 index 0000000000..7ddc81d9b8 --- /dev/null +++ b/test/131-structural-change/build @@ -0,0 +1,31 @@ +#!/bin/bash +# +# Copyright (C) 2015 The Android Open Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Stop if something fails. +set -e + +mkdir classes +${JAVAC} -d classes `find src -name '*.java'` + +mkdir classes-ex +${JAVAC} -d classes-ex `find src-ex -name '*.java'` + +if [ ${NEED_DEX} = "true" ]; then + ${DX} -JXmx256m --debug --dex --dump-to=classes.lst --output=classes.dex --dump-width=1000 classes + zip $TEST_NAME.jar classes.dex + ${DX} -JXmx256m --debug --dex --dump-to=classes-ex.lst --output=classes.dex --dump-width=1000 classes-ex + zip ${TEST_NAME}-ex.jar classes.dex +fi diff --git a/test/131-structural-change/expected.txt b/test/131-structural-change/expected.txt new file mode 100644 index 0000000000..cc7713d252 --- /dev/null +++ b/test/131-structural-change/expected.txt @@ -0,0 +1,2 @@ +Should really reach here. +Done. diff --git a/test/131-structural-change/info.txt b/test/131-structural-change/info.txt new file mode 100644 index 0000000000..6d5817bcea --- /dev/null +++ b/test/131-structural-change/info.txt @@ -0,0 +1 @@ +Check whether a structural change in a (non-native) multi-dex scenario is detected. diff --git a/test/131-structural-change/run b/test/131-structural-change/run new file mode 100755 index 0000000000..63fdb8c749 --- /dev/null +++ b/test/131-structural-change/run @@ -0,0 +1,18 @@ +#!/bin/bash +# +# Copyright (C) 2015 The Android Open Source Project +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. + +# Use secondary switch to add secondary dex file to class path. +exec ${RUN} "${@}" --secondary diff --git a/test/131-structural-change/src-ex/A.java b/test/131-structural-change/src-ex/A.java new file mode 100644 index 0000000000..800347b716 --- /dev/null +++ b/test/131-structural-change/src-ex/A.java @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +public class A { + public void bar() { + } +} diff --git a/test/131-structural-change/src-ex/B.java b/test/131-structural-change/src-ex/B.java new file mode 100644 index 0000000000..61369db32d --- /dev/null +++ b/test/131-structural-change/src-ex/B.java @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +public class B extends A { + public void test() { + System.out.println("Should not reach this!"); + } +} diff --git a/test/131-structural-change/src/A.java b/test/131-structural-change/src/A.java new file mode 100644 index 0000000000..b07de581d8 --- /dev/null +++ b/test/131-structural-change/src/A.java @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +public class A { + public void foo() { + } + + public void bar() { + } + + public void baz() { + } +} diff --git a/test/131-structural-change/src/Main.java b/test/131-structural-change/src/Main.java new file mode 100644 index 0000000000..8dfa2808a2 --- /dev/null +++ b/test/131-structural-change/src/Main.java @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2015 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +import java.io.File; +import java.lang.reflect.Constructor; +import java.lang.reflect.Method; + +/** + * Structural hazard test. + */ +public class Main { + public static void main(String[] args) { + new Main().run(); + } + + private void run() { + try { + Class<?> bClass = getClass().getClassLoader().loadClass("A"); + System.out.println("Should really reach here."); + } catch (Exception e) { + e.printStackTrace(System.out); + } + + boolean haveOatFile = hasOat(); + boolean gotError = false; + try { + Class<?> bClass = getClass().getClassLoader().loadClass("B"); + } catch (IncompatibleClassChangeError icce) { + gotError = true; + } catch (Exception e) { + e.printStackTrace(System.out); + } + if (haveOatFile ^ gotError) { + System.out.println("Did not get expected error."); + } + System.out.println("Done."); + } + + static { + System.loadLibrary("arttest"); + } + + private native static boolean hasOat(); +} diff --git a/test/Android.run-test.mk b/test/Android.run-test.mk index dc4ec66ce7..04c590e876 100644 --- a/test/Android.run-test.mk +++ b/test/Android.run-test.mk @@ -282,6 +282,7 @@ TEST_ART_BROKEN_NDEBUG_TESTS := \ 117-nopatchoat \ 118-noimage-dex2oat \ 119-noimage-patchoat \ + 131-structural-change \ ifneq (,$(filter ndebug,$(RUN_TYPES))) ART_TEST_KNOWN_BROKEN += $(call all-run-test-names,$(TARGET_TYPES),ndebug,$(PREBUILD_TYPES), \ diff --git a/test/etc/run-test-jar b/test/etc/run-test-jar index 2710df8dc4..92b1e8233f 100755 --- a/test/etc/run-test-jar +++ b/test/etc/run-test-jar @@ -10,7 +10,7 @@ msg() { ANDROID_ROOT="/system" ARCHITECTURES_32="(arm|x86|mips|none)" -ARCHITECTURES_64="(arm64|x86_64|none)" +ARCHITECTURES_64="(arm64|x86_64|mips64|none)" ARCHITECTURES_PATTERN="${ARCHITECTURES_32}" BOOT_IMAGE="" COMPILE_FLAGS="" @@ -38,7 +38,7 @@ RELOCATE="y" SECONDARY_DEX="" TIME_OUT="y" # Value in minutes. -TIME_OUT_VALUE=5 +TIME_OUT_VALUE=10 USE_GDB="n" USE_JVM="n" VERIFY="y" diff --git a/test/run-test b/test/run-test index d2b1ec9b05..2802b75be7 100755 --- a/test/run-test +++ b/test/run-test @@ -298,7 +298,7 @@ fi # Try to map the suffix64 flag and what we find in ${ANDROID_PRODUCT_OUT}/data/art-test to an architecture name. function guess_arch_name() { grep32bit=`ls ${ANDROID_PRODUCT_OUT}/data/art-test | grep -E '^(arm|x86|mips)$'` - grep64bit=`ls ${ANDROID_PRODUCT_OUT}/data/art-test | grep -E '^(arm64|x86_64)$'` + grep64bit=`ls ${ANDROID_PRODUCT_OUT}/data/art-test | grep -E '^(arm64|x86_64|mips64)$'` if [ "x${suffix64}" = "x64" ]; then target_arch_name=${grep64bit} else diff --git a/tools/checker.py b/tools/checker.py index 406a311638..24784cec6d 100755 --- a/tools/checker.py +++ b/tools/checker.py @@ -77,10 +77,11 @@ import re import shutil import sys import tempfile -from subprocess import check_call class Logger(object): - SilentMode = False + + class Level(object): + NoOutput, Error, Info = range(3) class Color(object): Default, Blue, Gray, Purple, Red = range(5) @@ -100,13 +101,15 @@ class Logger(object): else: return '\033[0m' + Verbosity = Level.Info + @staticmethod - def log(text, color=Color.Default, newLine=True, out=sys.stdout): - if not Logger.SilentMode: + def log(text, level=Level.Info, color=Color.Default, newLine=True, out=sys.stdout): + if level <= Logger.Verbosity: text = Logger.Color.terminalCode(color, out) + text + \ Logger.Color.terminalCode(Logger.Color.Default, out) if newLine: - print(text, file=out) + print(text, flush=True, file=out) else: print(text, end="", flush=True, file=out) @@ -120,9 +123,9 @@ class Logger(object): if location: location += " " - Logger.log(location, color=Logger.Color.Gray, newLine=False, out=sys.stderr) - Logger.log("error: ", color=Logger.Color.Red, newLine=False, out=sys.stderr) - Logger.log(msg, out=sys.stderr) + Logger.log(location, Logger.Level.Error, color=Logger.Color.Gray, newLine=False, out=sys.stderr) + Logger.log("error: ", Logger.Level.Error, color=Logger.Color.Red, newLine=False, out=sys.stderr) + Logger.log(msg, Logger.Level.Error, out=sys.stderr) sys.exit(1) @staticmethod @@ -685,52 +688,23 @@ class OutputFile(FileSplitMixin): def ParseArguments(): parser = argparse.ArgumentParser() - parser.add_argument("test_file", help="the source of the test with checking annotations") + parser.add_argument("tested_file", + help="text file the checks should be verified against") + parser.add_argument("source_path", nargs="?", + help="path to file/folder with checking annotations") parser.add_argument("--check-prefix", dest="check_prefix", default="CHECK", metavar="PREFIX", - help="prefix of checks in the test file (default: CHECK)") + help="prefix of checks in the test files (default: CHECK)") parser.add_argument("--list-groups", dest="list_groups", action="store_true", - help="print a list of all groups found in the test output") + help="print a list of all groups found in the tested file") parser.add_argument("--dump-group", dest="dump_group", metavar="GROUP", help="print the contents of an output group") + parser.add_argument("-q", "--quiet", action="store_true", + help="print only errors") + parser.add_argument("--no-clean", dest="no_clean", action="store_true", + help="don't clean up generated files") return parser.parse_args() -class cd: - """Helper class which temporarily changes the working directory.""" - - def __init__(self, newPath): - self.newPath = newPath - - def __enter__(self): - self.savedPath = os.getcwd() - os.chdir(self.newPath) - - def __exit__(self, etype, value, traceback): - os.chdir(self.savedPath) - - -def CompileTest(inputFile, tempFolder): - classFolder = tempFolder + "/classes" - dexFile = tempFolder + "/test.dex" - oatFile = tempFolder + "/test.oat" - outputFile = tempFolder + "/art.cfg" - os.makedirs(classFolder) - - # Build a DEX from the source file. We pass "--no-optimize" to dx to avoid - # interference with its optimizations. - check_call(["javac", "-d", classFolder, inputFile]) - check_call(["dx", "--dex", "--no-optimize", "--output=" + dexFile, classFolder]) - - # Run dex2oat and export the HGraph. The output is stored into ${PWD}/art.cfg. - with cd(tempFolder): - check_call(["dex2oat", "-j1", "--dump-passes", "--compiler-backend=Optimizing", - "--android-root=" + os.environ["ANDROID_HOST_OUT"], - "--boot-image=" + os.environ["ANDROID_HOST_OUT"] + "/framework/core-optimizing.art", - "--runtime-arg", "-Xnorelocate", "--dex-file=" + dexFile, "--oat-file=" + oatFile]) - - return outputFile - - def ListGroups(outputFilename): outputFile = OutputFile(open(outputFilename, "r")) for group in outputFile.groups: @@ -751,26 +725,47 @@ def DumpGroup(outputFilename, groupName): Logger.fail("Group \"" + groupName + "\" not found in the output") -def RunChecks(checkPrefix, checkFilename, outputFilename): - checkBaseName = os.path.basename(checkFilename) - outputBaseName = os.path.splitext(checkBaseName)[0] + ".cfg" +def FindCheckFiles(path): + if not path: + Logger.fail("No source path provided") + elif os.path.isfile(path): + return [ path ] + elif os.path.isdir(path): + foundFiles = [] + for root, dirs, files in os.walk(path): + for file in files: + if os.path.splitext(file)[1] == ".java": + foundFiles.append(os.path.join(root, file)) + return foundFiles + else: + Logger.fail("Source path \"" + path + "\" not found") + - checkFile = CheckFile(checkPrefix, open(checkFilename, "r"), checkBaseName) +def RunChecks(checkPrefix, checkPath, outputFilename): + outputBaseName = os.path.basename(outputFilename) outputFile = OutputFile(open(outputFilename, "r"), outputBaseName) - checkFile.match(outputFile) + + for checkFilename in FindCheckFiles(checkPath): + checkBaseName = os.path.basename(checkFilename) + checkFile = CheckFile(checkPrefix, open(checkFilename, "r"), checkBaseName) + checkFile.match(outputFile) if __name__ == "__main__": args = ParseArguments() - tempFolder = tempfile.mkdtemp() + if args.quiet: + Logger.Verbosity = Logger.Level.Error + tempFolder = tempfile.mkdtemp() try: - outputFile = CompileTest(args.test_file, tempFolder) if args.list_groups: - ListGroups(outputFile) + ListGroups(args.tested_file) elif args.dump_group: - DumpGroup(outputFile, args.dump_group) + DumpGroup(args.tested_file, args.dump_group) else: - RunChecks(args.check_prefix, args.test_file, outputFile) + RunChecks(args.check_prefix, args.source_path, args.tested_file) finally: - shutil.rmtree(tempFolder) + if args.no_clean: + print("Files left in %s" % tempFolder) + else: + shutil.rmtree(tempFolder) diff --git a/tools/checker_test.py b/tools/checker_test.py index 3c659c24c0..1466b935c1 100755 --- a/tools/checker_test.py +++ b/tools/checker_test.py @@ -457,5 +457,5 @@ class TestCheckFile_Parse(unittest.TestCase): ("def", CheckVariant.DAG) ])) ]) if __name__ == '__main__': - checker.Logger.SilentMode = True + checker.Logger.Verbosity = checker.Logger.Level.NoOutput unittest.main() diff --git a/tools/symbolize.sh b/tools/symbolize.sh index b66191f9b0..0168e7db2f 100755 --- a/tools/symbolize.sh +++ b/tools/symbolize.sh @@ -52,7 +52,7 @@ function all() { DIRS=$(adbls /data/dalvik-cache/) for DIR in $DIRS ; do case $DIR in - arm|arm64|mips|x86|x86_64) + arm|arm64|mips|mips64|x86|x86_64) FILES=$(adbls /data/dalvik-cache/$DIR/*.oat /data/dalvik-cache/$DIR/*.dex) for FILE in $FILES ; do # Cannot use basename as the file doesn't exist. |