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-rw-r--r--compiler/optimizing/code_generator_arm64.cc2
-rw-r--r--runtime/arch/arm64/callee_save_frame_arm64.h2
-rw-r--r--runtime/arch/arm64/entrypoints_init_arm64.cc1
-rw-r--r--runtime/arch/arm64/quick_entrypoints_arm64.S194
4 files changed, 98 insertions, 101 deletions
diff --git a/compiler/optimizing/code_generator_arm64.cc b/compiler/optimizing/code_generator_arm64.cc
index d56f7aaca1..5bca93fde1 100644
--- a/compiler/optimizing/code_generator_arm64.cc
+++ b/compiler/optimizing/code_generator_arm64.cc
@@ -1205,6 +1205,7 @@ void CodeGeneratorARM64::SetupBlockedRegisters() const {
// mr : Runtime reserved.
// ip1 : VIXL core temp.
// ip0 : VIXL core temp.
+ // x18 : Platform register.
//
// Blocked fp registers:
// d31 : VIXL fp temp.
@@ -1213,6 +1214,7 @@ void CodeGeneratorARM64::SetupBlockedRegisters() const {
while (!reserved_core_registers.IsEmpty()) {
blocked_core_registers_[reserved_core_registers.PopLowestIndex().GetCode()] = true;
}
+ blocked_core_registers_[X18] = true;
CPURegList reserved_fp_registers = vixl_reserved_fp_registers;
while (!reserved_fp_registers.IsEmpty()) {
diff --git a/runtime/arch/arm64/callee_save_frame_arm64.h b/runtime/arch/arm64/callee_save_frame_arm64.h
index bc36bfabec..a5aea2a573 100644
--- a/runtime/arch/arm64/callee_save_frame_arm64.h
+++ b/runtime/arch/arm64/callee_save_frame_arm64.h
@@ -54,7 +54,7 @@ static constexpr uint32_t kArm64CalleeSaveEverythingSpills =
(1 << art::arm64::X9) | (1 << art::arm64::X10) | (1 << art::arm64::X11) |
(1 << art::arm64::X12) | (1 << art::arm64::X13) | (1 << art::arm64::X14) |
(1 << art::arm64::X15) | (1 << art::arm64::X16) | (1 << art::arm64::X17) |
- (1 << art::arm64::X18) | (1 << art::arm64::X19);
+ (1 << art::arm64::X19);
static constexpr uint32_t kArm64CalleeSaveFpAlwaysSpills = 0;
static constexpr uint32_t kArm64CalleeSaveFpRefSpills = 0;
diff --git a/runtime/arch/arm64/entrypoints_init_arm64.cc b/runtime/arch/arm64/entrypoints_init_arm64.cc
index 4c43b7ed3d..5a77d20344 100644
--- a/runtime/arch/arm64/entrypoints_init_arm64.cc
+++ b/runtime/arch/arm64/entrypoints_init_arm64.cc
@@ -103,7 +103,6 @@ void UpdateReadBarrierEntrypoints(QuickEntryPoints* qpoints, bool is_active) {
qpoints->pReadBarrierMarkReg14 = is_active ? art_quick_read_barrier_mark_reg14 : nullptr;
qpoints->pReadBarrierMarkReg15 = is_active ? art_quick_read_barrier_mark_reg15 : nullptr;
qpoints->pReadBarrierMarkReg17 = is_active ? art_quick_read_barrier_mark_reg17 : nullptr;
- qpoints->pReadBarrierMarkReg18 = is_active ? art_quick_read_barrier_mark_reg18 : nullptr;
qpoints->pReadBarrierMarkReg19 = is_active ? art_quick_read_barrier_mark_reg19 : nullptr;
qpoints->pReadBarrierMarkReg20 = is_active ? art_quick_read_barrier_mark_reg20 : nullptr;
qpoints->pReadBarrierMarkReg21 = is_active ? art_quick_read_barrier_mark_reg21 : nullptr;
diff --git a/runtime/arch/arm64/quick_entrypoints_arm64.S b/runtime/arch/arm64/quick_entrypoints_arm64.S
index 96ceecfe9b..9f3377ed1e 100644
--- a/runtime/arch/arm64/quick_entrypoints_arm64.S
+++ b/runtime/arch/arm64/quick_entrypoints_arm64.S
@@ -289,36 +289,33 @@
#endif
// Save FP registers.
- // For better performance, store d0 and d31 separately, so that all STPs are 16-byte aligned.
- str d0, [sp, #8]
- stp d1, d2, [sp, #16]
- stp d3, d4, [sp, #32]
- stp d5, d6, [sp, #48]
- stp d7, d8, [sp, #64]
- stp d9, d10, [sp, #80]
- stp d11, d12, [sp, #96]
- stp d13, d14, [sp, #112]
- stp d15, d16, [sp, #128]
- stp d17, d18, [sp, #144]
- stp d19, d20, [sp, #160]
- stp d21, d22, [sp, #176]
- stp d23, d24, [sp, #192]
- stp d25, d26, [sp, #208]
- stp d27, d28, [sp, #224]
- stp d29, d30, [sp, #240]
- str d31, [sp, #256]
+ stp d0, d1, [sp, #16]
+ stp d2, d3, [sp, #32]
+ stp d4, d5, [sp, #48]
+ stp d6, d7, [sp, #64]
+ stp d8, d9, [sp, #80]
+ stp d10, d11, [sp, #96]
+ stp d12, d13, [sp, #112]
+ stp d14, d15, [sp, #128]
+ stp d16, d17, [sp, #144]
+ stp d18, d19, [sp, #160]
+ stp d20, d21, [sp, #176]
+ stp d22, d23, [sp, #192]
+ stp d24, d25, [sp, #208]
+ stp d26, d27, [sp, #224]
+ stp d28, d29, [sp, #240]
+ stp d30, d31, [sp, #256]
// Save core registers.
- SAVE_REG x0, 264
- SAVE_TWO_REGS x1, x2, 272
- SAVE_TWO_REGS x3, x4, 288
- SAVE_TWO_REGS x5, x6, 304
- SAVE_TWO_REGS x7, x8, 320
- SAVE_TWO_REGS x9, x10, 336
- SAVE_TWO_REGS x11, x12, 352
- SAVE_TWO_REGS x13, x14, 368
- SAVE_TWO_REGS x15, x16, 384
- SAVE_TWO_REGS x17, x18, 400
+ SAVE_TWO_REGS x0, x1, 272
+ SAVE_TWO_REGS x2, x3, 288
+ SAVE_TWO_REGS x4, x5, 304
+ SAVE_TWO_REGS x6, x7, 320
+ SAVE_TWO_REGS x8, x9, 336
+ SAVE_TWO_REGS x10, x11, 352
+ SAVE_TWO_REGS x12, x13, 368
+ SAVE_TWO_REGS x14, x15, 384
+ SAVE_TWO_REGS x16, x17, 400 // Do not save the platform register.
SAVE_TWO_REGS x19, x20, 416
SAVE_TWO_REGS x21, x22, 432
SAVE_TWO_REGS x23, x24, 448
@@ -351,35 +348,33 @@
.macro RESTORE_SAVE_EVERYTHING_FRAME_KEEP_X0
// Restore FP registers.
- // For better performance, load d0 and d31 separately, so that all LDPs are 16-byte aligned.
- ldr d0, [sp, #8]
- ldp d1, d2, [sp, #16]
- ldp d3, d4, [sp, #32]
- ldp d5, d6, [sp, #48]
- ldp d7, d8, [sp, #64]
- ldp d9, d10, [sp, #80]
- ldp d11, d12, [sp, #96]
- ldp d13, d14, [sp, #112]
- ldp d15, d16, [sp, #128]
- ldp d17, d18, [sp, #144]
- ldp d19, d20, [sp, #160]
- ldp d21, d22, [sp, #176]
- ldp d23, d24, [sp, #192]
- ldp d25, d26, [sp, #208]
- ldp d27, d28, [sp, #224]
- ldp d29, d30, [sp, #240]
- ldr d31, [sp, #256]
+ ldp d0, d1, [sp, #16]
+ ldp d2, d3, [sp, #32]
+ ldp d4, d5, [sp, #48]
+ ldp d6, d7, [sp, #64]
+ ldp d8, d9, [sp, #80]
+ ldp d10, d11, [sp, #96]
+ ldp d12, d13, [sp, #112]
+ ldp d14, d15, [sp, #128]
+ ldp d16, d17, [sp, #144]
+ ldp d18, d19, [sp, #160]
+ ldp d20, d21, [sp, #176]
+ ldp d22, d23, [sp, #192]
+ ldp d24, d25, [sp, #208]
+ ldp d26, d27, [sp, #224]
+ ldp d28, d29, [sp, #240]
+ ldp d30, d31, [sp, #256]
// Restore core registers, except x0.
- RESTORE_TWO_REGS x1, x2, 272
- RESTORE_TWO_REGS x3, x4, 288
- RESTORE_TWO_REGS x5, x6, 304
- RESTORE_TWO_REGS x7, x8, 320
- RESTORE_TWO_REGS x9, x10, 336
- RESTORE_TWO_REGS x11, x12, 352
- RESTORE_TWO_REGS x13, x14, 368
- RESTORE_TWO_REGS x15, x16, 384
- RESTORE_TWO_REGS x17, x18, 400
+ RESTORE_REG x1, 280
+ RESTORE_TWO_REGS x2, x3, 288
+ RESTORE_TWO_REGS x4, x5, 304
+ RESTORE_TWO_REGS x6, x7, 320
+ RESTORE_TWO_REGS x8, x9, 336
+ RESTORE_TWO_REGS x10, x11, 352
+ RESTORE_TWO_REGS x12, x13, 368
+ RESTORE_TWO_REGS x14, x15, 384
+ RESTORE_TWO_REGS x16, x17, 400 // Do not restore the platform register.
RESTORE_TWO_REGS x19, x20, 416
RESTORE_TWO_REGS x21, x22, 432
RESTORE_TWO_REGS x23, x24, 448
@@ -391,7 +386,7 @@
.endm
.macro RESTORE_SAVE_EVERYTHING_FRAME
- RESTORE_REG x0, 264
+ RESTORE_REG x0, 272
RESTORE_SAVE_EVERYTHING_FRAME_KEEP_X0
.endm
@@ -1116,7 +1111,8 @@ ENTRY art_quick_do_long_jump
ldp x12, x13, [x0, #96]
ldp x14, x15, [x0, #112]
// Do not load IP0 (x16) and IP1 (x17), these shall be clobbered below.
- ldp x18, x19, [x0, #144] // X18 and xSELF.
+ // Don't load the platform register (x18) either.
+ ldr x19, [x0, #152] // xSELF.
ldp x20, x21, [x0, #160] // For Baker RB, wMR (w20) is reloaded below.
ldp x22, x23, [x0, #176]
ldp x24, x25, [x0, #192]
@@ -2293,8 +2289,8 @@ ENTRY art_quick_instrumentation_exit
mov xLR, #0 // Clobber LR for later checks.
SETUP_SAVE_EVERYTHING_FRAME
- add x3, sp, #8 // Pass floating-point result pointer, in kSaveEverything frame.
- add x2, sp, #264 // Pass integer result pointer, in kSaveEverything frame.
+ add x3, sp, #16 // Pass floating-point result pointer, in kSaveEverything frame.
+ add x2, sp, #272 // Pass integer result pointer, in kSaveEverything frame.
mov x1, sp // Pass SP.
mov x0, xSELF // Pass Thread.
bl artInstrumentationMethodExitFromCode // (Thread*, SP, gpr_res*, fpr_res*)
@@ -2496,7 +2492,8 @@ ENTRY \name
.Lslow_rb_\name:
/*
* Allocate 44 stack slots * 8 = 352 bytes:
- * - 20 slots for core registers X0-15, X17-X19, LR
+ * - 19 slots for core registers X0-15, X17, X19, LR
+ * - 1 slot padding
* - 24 slots for floating-point registers D0-D7 and D16-D31
*/
// We must not clobber IP1 since code emitted for HLoadClass and HLoadString
@@ -2510,8 +2507,8 @@ ENTRY \name
SAVE_TWO_REGS x10, x11, 80
SAVE_TWO_REGS x12, x13, 96
SAVE_TWO_REGS x14, x15, 112
- SAVE_TWO_REGS x17, x18, 128 // Skip x16, i.e. IP0.
- SAVE_TWO_REGS x19, xLR, 144 // Save also return address.
+ SAVE_TWO_REGS x17, x19, 128 // Skip x16, i.e. IP0, and x18, the platform register.
+ SAVE_REG xLR, 144 // Save also return address.
// Save all potentially live caller-save floating-point registers.
stp d0, d1, [sp, #160]
stp d2, d3, [sp, #176]
@@ -2544,8 +2541,8 @@ ENTRY \name
POP_REGS_NE x10, x11, 80, \xreg
POP_REGS_NE x12, x13, 96, \xreg
POP_REGS_NE x14, x15, 112, \xreg
- POP_REGS_NE x17, x18, 128, \xreg
- POP_REGS_NE x19, xLR, 144, \xreg // Restore also return address.
+ POP_REGS_NE x17, x19, 128, \xreg
+ POP_REG_NE xLR, 144, \xreg // Restore also return address.
// Restore floating-point registers.
ldp d0, d1, [sp, #160]
ldp d2, d3, [sp, #176]
@@ -2588,7 +2585,7 @@ READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg14, w14, x14
READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg15, w15, x15
// READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg16, w16, x16 ip0 is blocked
READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg17, w17, x17
-READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg18, w18, x18
+// READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg18, w18, x18 x18 is blocked
READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg19, w19, x19
READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg20, w20, x20
READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg21, w21, x21
@@ -2629,7 +2626,7 @@ READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg29, w29, x29
SELECT_X_OR_W_FOR_MACRO \macro_for_register, x15, w15, \xreg
\macro_for_reserved_register // IP0 is reserved
\macro_for_reserved_register // IP1 is reserved
- SELECT_X_OR_W_FOR_MACRO \macro_for_register, x18, w18, \xreg
+ \macro_for_reserved_register // x18 is reserved
SELECT_X_OR_W_FOR_MACRO \macro_for_register, x19, w19, \xreg
SELECT_X_OR_W_FOR_MACRO \macro_for_register, x20, w20, \xreg
SELECT_X_OR_W_FOR_MACRO \macro_for_register, x21, w21, \xreg
@@ -2673,13 +2670,12 @@ READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg29, w29, x29
.macro READ_BARRIER_MARK_INTROSPECTION_SLOW_PATH ldr_offset
/*
- * Allocate 44 stack slots * 8 = 352 bytes:
- * - 19 slots for core registers X0-15, X18-X19, LR
- * - 1 slot padding
+ * Allocate 42 stack slots * 8 = 336 bytes:
+ * - 18 slots for core registers X0-15, X19, LR
* - 24 slots for floating-point registers D0-D7 and D16-D31
*/
// Save all potentially live caller-save core registers.
- SAVE_TWO_REGS_INCREASE_FRAME x0, x1, 352
+ SAVE_TWO_REGS_INCREASE_FRAME x0, x1, 336
SAVE_TWO_REGS x2, x3, 16
SAVE_TWO_REGS x4, x5, 32
SAVE_TWO_REGS x6, x7, 48
@@ -2687,21 +2683,21 @@ READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg29, w29, x29
SAVE_TWO_REGS x10, x11, 80
SAVE_TWO_REGS x12, x13, 96
SAVE_TWO_REGS x14, x15, 112
- SAVE_TWO_REGS x18, x19, 128 // Skip x16, x17, i.e. IP0, IP1.
- SAVE_REG xLR, 144 // Save return address, skip padding at 152.
+ // Skip x16, x17, i.e. IP0, IP1, and x18, the platform register.
+ SAVE_TWO_REGS x19, xLR, 128 // Save return address.
// Save all potentially live caller-save floating-point registers.
- stp d0, d1, [sp, #160]
- stp d2, d3, [sp, #176]
- stp d4, d5, [sp, #192]
- stp d6, d7, [sp, #208]
- stp d16, d17, [sp, #224]
- stp d18, d19, [sp, #240]
- stp d20, d21, [sp, #256]
- stp d22, d23, [sp, #272]
- stp d24, d25, [sp, #288]
- stp d26, d27, [sp, #304]
- stp d28, d29, [sp, #320]
- stp d30, d31, [sp, #336]
+ stp d0, d1, [sp, #144]
+ stp d2, d3, [sp, #160]
+ stp d4, d5, [sp, #176]
+ stp d6, d7, [sp, #192]
+ stp d16, d17, [sp, #208]
+ stp d18, d19, [sp, #224]
+ stp d20, d21, [sp, #240]
+ stp d22, d23, [sp, #256]
+ stp d24, d25, [sp, #272]
+ stp d26, d27, [sp, #288]
+ stp d28, d29, [sp, #304]
+ stp d30, d31, [sp, #320]
mov x0, xIP0
bl artReadBarrierMark // artReadBarrierMark(obj)
@@ -2716,26 +2712,26 @@ READ_BARRIER_MARK_REG art_quick_read_barrier_mark_reg29, w29, x29
RESTORE_TWO_REGS x10, x11, 80
RESTORE_TWO_REGS x12, x13, 96
RESTORE_TWO_REGS x14, x15, 112
- RESTORE_TWO_REGS x18, x19, 128 // Skip x16, x17, i.e. IP0, IP1.
- RESTORE_REG xLR, 144 // Restore return address.
+ // Skip x16, x17, i.e. IP0, IP1, and x18, the platform register.
+ RESTORE_TWO_REGS x19, xLR, 128 // Restore return address.
// Restore caller-save floating-point registers.
- ldp d0, d1, [sp, #160]
- ldp d2, d3, [sp, #176]
- ldp d4, d5, [sp, #192]
- ldp d6, d7, [sp, #208]
- ldp d16, d17, [sp, #224]
- ldp d18, d19, [sp, #240]
- ldp d20, d21, [sp, #256]
- ldp d22, d23, [sp, #272]
- ldp d24, d25, [sp, #288]
- ldp d26, d27, [sp, #304]
- ldp d28, d29, [sp, #320]
- ldp d30, d31, [sp, #336]
+ ldp d0, d1, [sp, #144]
+ ldp d2, d3, [sp, #160]
+ ldp d4, d5, [sp, #176]
+ ldp d6, d7, [sp, #192]
+ ldp d16, d17, [sp, #208]
+ ldp d18, d19, [sp, #224]
+ ldp d20, d21, [sp, #240]
+ ldp d22, d23, [sp, #256]
+ ldp d24, d25, [sp, #272]
+ ldp d26, d27, [sp, #288]
+ ldp d28, d29, [sp, #304]
+ ldp d30, d31, [sp, #320]
ldr x0, [lr, #\ldr_offset] // Load the instruction.
adr xIP1, .Lmark_introspection_return_switch
bfi xIP1, x0, #3, #5 // Calculate switch case address.
- RESTORE_TWO_REGS_DECREASE_FRAME x0, x1, 352
+ RESTORE_TWO_REGS_DECREASE_FRAME x0, x1, 336
br xIP1
.endm
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