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-rw-r--r--runtime/interpreter/mterp/arm/entry.S3
-rw-r--r--runtime/interpreter/mterp/arm/header.S1
-rw-r--r--runtime/interpreter/mterp/arm64/entry.S3
-rw-r--r--runtime/interpreter/mterp/arm64/header.S1
-rw-r--r--runtime/interpreter/mterp/cfi_asm_support.h31
-rw-r--r--runtime/interpreter/mterp/mips/entry.S1
-rw-r--r--runtime/interpreter/mterp/mips/header.S1
-rw-r--r--runtime/interpreter/mterp/mips64/entry.S1
-rw-r--r--runtime/interpreter/mterp/mips64/header.S1
-rw-r--r--runtime/interpreter/mterp/out/mterp_arm.S4
-rw-r--r--runtime/interpreter/mterp/out/mterp_arm64.S4
-rw-r--r--runtime/interpreter/mterp/out/mterp_mips.S2
-rw-r--r--runtime/interpreter/mterp/out/mterp_mips64.S2
-rw-r--r--runtime/interpreter/mterp/out/mterp_x86.S4
-rw-r--r--runtime/interpreter/mterp/out/mterp_x86_64.S4
-rw-r--r--runtime/interpreter/mterp/x86/entry.S3
-rw-r--r--runtime/interpreter/mterp/x86/header.S1
-rw-r--r--runtime/interpreter/mterp/x86_64/entry.S3
-rw-r--r--runtime/interpreter/mterp/x86_64/header.S1
19 files changed, 63 insertions, 8 deletions
diff --git a/runtime/interpreter/mterp/arm/entry.S b/runtime/interpreter/mterp/arm/entry.S
index de617a90d7..df4bcc66f3 100644
--- a/runtime/interpreter/mterp/arm/entry.S
+++ b/runtime/interpreter/mterp/arm/entry.S
@@ -23,7 +23,7 @@
/*
* On entry:
* r0 Thread* self/
- * r1 code_item
+ * r1 insns_
* r2 ShadowFrame
* r3 JValue* result_register
*
@@ -56,6 +56,7 @@ ENTRY ExecuteMterpImpl
VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame
ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc.
add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/arm/header.S b/runtime/interpreter/mterp/arm/header.S
index 51c2ba4c03..64ab9efa19 100644
--- a/runtime/interpreter/mterp/arm/header.S
+++ b/runtime/interpreter/mterp/arm/header.S
@@ -85,6 +85,7 @@ unspecified registers or condition codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
#define MTERP_PROFILE_BRANCHES 1
#define MTERP_LOGGING 0
diff --git a/runtime/interpreter/mterp/arm64/entry.S b/runtime/interpreter/mterp/arm64/entry.S
index f3d40ff6f7..8d61210be8 100644
--- a/runtime/interpreter/mterp/arm64/entry.S
+++ b/runtime/interpreter/mterp/arm64/entry.S
@@ -20,7 +20,7 @@
* Interpreter entry point.
* On entry:
* x0 Thread* self/
- * x1 code_item
+ * x1 insns_
* x2 ShadowFrame
* x3 JValue* result_register
*
@@ -46,6 +46,7 @@ ENTRY ExecuteMterpImpl
add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame
ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc.
add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode
+ .cfi_register DPC_PSEUDO_REG, xPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/arm64/header.S b/runtime/interpreter/mterp/arm64/header.S
index 47f12d2f5d..9261b770d6 100644
--- a/runtime/interpreter/mterp/arm64/header.S
+++ b/runtime/interpreter/mterp/arm64/header.S
@@ -87,6 +87,7 @@ codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
#define MTERP_PROFILE_BRANCHES 1
#define MTERP_LOGGING 0
diff --git a/runtime/interpreter/mterp/cfi_asm_support.h b/runtime/interpreter/mterp/cfi_asm_support.h
new file mode 100644
index 0000000000..a97e153993
--- /dev/null
+++ b/runtime/interpreter/mterp/cfi_asm_support.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2017 The Android Open Source Project
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ART_RUNTIME_INTERPRETER_MTERP_CFI_ASM_SUPPORT_H_
+#define ART_RUNTIME_INTERPRETER_MTERP_CFI_ASM_SUPPORT_H_
+
+/*
+ * To keep track of the Dalvik PC, give assign it a magic register number that
+ * won't be confused with a pysical register. Then, standard .cfi directives
+ * will track the location of it so that it may be extracted during a stack
+ * unwind.
+ *
+ * The Dalvik PC will be in either a physical registor, or the frame.
+ * Encoded from the ASCII string " DEX" -> 0x20 0x44 0x45 0x58
+ */
+#define DPC_PSEUDO_REG 0x20444558
+
+#endif // ART_RUNTIME_INTERPRETER_MTERP_CFI_ASM_SUPPORT_H_
diff --git a/runtime/interpreter/mterp/mips/entry.S b/runtime/interpreter/mterp/mips/entry.S
index 03de985cd0..3908cb506e 100644
--- a/runtime/interpreter/mterp/mips/entry.S
+++ b/runtime/interpreter/mterp/mips/entry.S
@@ -53,6 +53,7 @@ ExecuteMterpImpl:
EAS2(rREFS, rFP, a0) # point to reference array in shadow frame
lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc
EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC()
diff --git a/runtime/interpreter/mterp/mips/header.S b/runtime/interpreter/mterp/mips/header.S
index e4552ddf3d..1ccaa6443f 100644
--- a/runtime/interpreter/mterp/mips/header.S
+++ b/runtime/interpreter/mterp/mips/header.S
@@ -32,6 +32,7 @@
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.S"
#if (__mips==32) && (__mips_isa_rev>=2)
#define MIPS32REVGE2 /* mips32r2 and greater */
diff --git a/runtime/interpreter/mterp/mips64/entry.S b/runtime/interpreter/mterp/mips64/entry.S
index 436b88dbd0..841a817569 100644
--- a/runtime/interpreter/mterp/mips64/entry.S
+++ b/runtime/interpreter/mterp/mips64/entry.S
@@ -73,6 +73,7 @@ ExecuteMterpImpl:
dlsa rREFS, v0, rFP, 2
lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2)
dlsa rPC, v0, a1, 1
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/mips64/header.S b/runtime/interpreter/mterp/mips64/header.S
index d1acefd338..2b550cb533 100644
--- a/runtime/interpreter/mterp/mips64/header.S
+++ b/runtime/interpreter/mterp/mips64/header.S
@@ -102,6 +102,7 @@ The following registers have fixed assignments:
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
/*
* Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So,
diff --git a/runtime/interpreter/mterp/out/mterp_arm.S b/runtime/interpreter/mterp/out/mterp_arm.S
index 69d7edbe8a..f3c1124ec4 100644
--- a/runtime/interpreter/mterp/out/mterp_arm.S
+++ b/runtime/interpreter/mterp/out/mterp_arm.S
@@ -92,6 +92,7 @@ unspecified registers or condition codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
#define MTERP_PROFILE_BRANCHES 1
#define MTERP_LOGGING 0
@@ -341,7 +342,7 @@ unspecified registers or condition codes.
/*
* On entry:
* r0 Thread* self/
- * r1 code_item
+ * r1 insns_
* r2 ShadowFrame
* r3 JValue* result_register
*
@@ -374,6 +375,7 @@ ENTRY ExecuteMterpImpl
VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame
ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc.
add rPC, r1, r0, lsl #1 @ Create direct pointer to 1st dex opcode
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S
index 82edab465e..347d54f705 100644
--- a/runtime/interpreter/mterp/out/mterp_arm64.S
+++ b/runtime/interpreter/mterp/out/mterp_arm64.S
@@ -94,6 +94,7 @@ codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
#define MTERP_PROFILE_BRANCHES 1
#define MTERP_LOGGING 0
@@ -378,7 +379,7 @@ codes.
* Interpreter entry point.
* On entry:
* x0 Thread* self/
- * x1 code_item
+ * x1 insns_
* x2 ShadowFrame
* x3 JValue* result_register
*
@@ -404,6 +405,7 @@ ENTRY ExecuteMterpImpl
add xREFS, xFP, w0, lsl #2 // point to reference array in shadow frame
ldr w0, [x2, #SHADOWFRAME_DEX_PC_OFFSET] // Get starting dex_pc.
add xPC, x1, w0, lsl #1 // Create direct pointer to 1st dex opcode
+ .cfi_register DPC_PSEUDO_REG, xPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/out/mterp_mips.S b/runtime/interpreter/mterp/out/mterp_mips.S
index 8cc1b19128..9535e254e7 100644
--- a/runtime/interpreter/mterp/out/mterp_mips.S
+++ b/runtime/interpreter/mterp/out/mterp_mips.S
@@ -39,6 +39,7 @@
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.S"
#if (__mips==32) && (__mips_isa_rev>=2)
#define MIPS32REVGE2 /* mips32r2 and greater */
@@ -786,6 +787,7 @@ ExecuteMterpImpl:
EAS2(rREFS, rFP, a0) # point to reference array in shadow frame
lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc
EAS1(rPC, a1, a0) # Create direct pointer to 1st dex opcode
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC()
diff --git a/runtime/interpreter/mterp/out/mterp_mips64.S b/runtime/interpreter/mterp/out/mterp_mips64.S
index 139ee25904..559c72bb0c 100644
--- a/runtime/interpreter/mterp/out/mterp_mips64.S
+++ b/runtime/interpreter/mterp/out/mterp_mips64.S
@@ -109,6 +109,7 @@ The following registers have fixed assignments:
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
/*
* Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So,
@@ -407,6 +408,7 @@ ExecuteMterpImpl:
dlsa rREFS, v0, rFP, 2
lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2)
dlsa rPC, v0, a1, 1
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/out/mterp_x86.S b/runtime/interpreter/mterp/out/mterp_x86.S
index cbab61ebf6..0613c9d12e 100644
--- a/runtime/interpreter/mterp/out/mterp_x86.S
+++ b/runtime/interpreter/mterp/out/mterp_x86.S
@@ -95,6 +95,7 @@ unspecified registers or condition codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
/*
* Handle mac compiler specific
@@ -342,7 +343,7 @@ unspecified registers or condition codes.
/*
* On entry:
* 0 Thread* self
- * 1 code_item
+ * 1 insns_
* 2 ShadowFrame
* 3 JValue* result_register
*
@@ -379,6 +380,7 @@ SYMBOL(ExecuteMterpImpl):
leal (rFP, %eax, 4), rREFS
movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax
lea (%ecx, %eax, 2), rPC
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Set up for backwards branches & osr profiling */
diff --git a/runtime/interpreter/mterp/out/mterp_x86_64.S b/runtime/interpreter/mterp/out/mterp_x86_64.S
index 83c3e4fb91..aa91db3b61 100644
--- a/runtime/interpreter/mterp/out/mterp_x86_64.S
+++ b/runtime/interpreter/mterp/out/mterp_x86_64.S
@@ -91,6 +91,7 @@ unspecified registers or condition codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
/*
* Handle mac compiler specific
@@ -328,7 +329,7 @@ unspecified registers or condition codes.
/*
* On entry:
* 0 Thread* self
- * 1 code_item
+ * 1 insns_
* 2 ShadowFrame
* 3 JValue* result_register
*
@@ -362,6 +363,7 @@ SYMBOL(ExecuteMterpImpl):
leaq (rFP, %rax, 4), rREFS
movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax
leaq (IN_ARG1, %rax, 2), rPC
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/x86/entry.S b/runtime/interpreter/mterp/x86/entry.S
index 055e834fed..10ca8366de 100644
--- a/runtime/interpreter/mterp/x86/entry.S
+++ b/runtime/interpreter/mterp/x86/entry.S
@@ -24,7 +24,7 @@
/*
* On entry:
* 0 Thread* self
- * 1 code_item
+ * 1 insns_
* 2 ShadowFrame
* 3 JValue* result_register
*
@@ -61,6 +61,7 @@ SYMBOL(ExecuteMterpImpl):
leal (rFP, %eax, 4), rREFS
movl SHADOWFRAME_DEX_PC_OFFSET(%edx), %eax
lea (%ecx, %eax, 2), rPC
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Set up for backwards branches & osr profiling */
diff --git a/runtime/interpreter/mterp/x86/header.S b/runtime/interpreter/mterp/x86/header.S
index 370012f324..0e585e86f0 100644
--- a/runtime/interpreter/mterp/x86/header.S
+++ b/runtime/interpreter/mterp/x86/header.S
@@ -88,6 +88,7 @@ unspecified registers or condition codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
/*
* Handle mac compiler specific
diff --git a/runtime/interpreter/mterp/x86_64/entry.S b/runtime/interpreter/mterp/x86_64/entry.S
index 83b845b702..d85ef7fe24 100644
--- a/runtime/interpreter/mterp/x86_64/entry.S
+++ b/runtime/interpreter/mterp/x86_64/entry.S
@@ -24,7 +24,7 @@
/*
* On entry:
* 0 Thread* self
- * 1 code_item
+ * 1 insns_
* 2 ShadowFrame
* 3 JValue* result_register
*
@@ -58,6 +58,7 @@ SYMBOL(ExecuteMterpImpl):
leaq (rFP, %rax, 4), rREFS
movl SHADOWFRAME_DEX_PC_OFFSET(IN_ARG2), %eax
leaq (IN_ARG1, %rax, 2), rPC
+ .cfi_register DPC_PSEUDO_REG, rPC
EXPORT_PC
/* Starting ibase */
diff --git a/runtime/interpreter/mterp/x86_64/header.S b/runtime/interpreter/mterp/x86_64/header.S
index 9d21f3f1a1..a3ef8953ca 100644
--- a/runtime/interpreter/mterp/x86_64/header.S
+++ b/runtime/interpreter/mterp/x86_64/header.S
@@ -84,6 +84,7 @@ unspecified registers or condition codes.
* to expand the macros into assembler assignment statements.
*/
#include "asm_support.h"
+#include "interpreter/mterp/cfi_asm_support.h"
/*
* Handle mac compiler specific
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-02 00:40:40 +0000