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-rw-r--r--runtime/interpreter/mterp/x86/arithmetic.S46
-rw-r--r--runtime/interpreter/mterp/x86/main.S28
-rw-r--r--runtime/interpreter/mterp/x86_64/arithmetic.S50
-rw-r--r--runtime/interpreter/mterp/x86_64/main.S30
4 files changed, 78 insertions, 76 deletions
diff --git a/runtime/interpreter/mterp/x86/arithmetic.S b/runtime/interpreter/mterp/x86/arithmetic.S
index 43ca4c8f5d..3b5f0beb89 100644
--- a/runtime/interpreter/mterp/x86/arithmetic.S
+++ b/runtime/interpreter/mterp/x86/arithmetic.S
@@ -142,7 +142,7 @@
%def binop(result="%eax", instr=""):
/*
* Generic 32-bit binary operation. Provide an "instr" line that
- * specifies an instruction that performs "result = eax op (rFP,%ecx,4)".
+ * specifies an instruction that performs "result = eax op VREG_ADDRESS(%ecx)".
* This could be an x86 instruction or a function call. (If the result
* comes back in a register other than eax, you can override "result".)
*
@@ -153,7 +153,7 @@
movzbl 2(rPC), %eax # eax <- BB
movzbl 3(rPC), %ecx # ecx <- CC
GET_VREG %eax, %eax # eax <- vBB
- $instr # ex: addl (rFP,%ecx,4),%eax
+ $instr # ex: addl VREG_ADDRESS(%ecx),%eax
SET_VREG $result, rINST
ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
@@ -187,7 +187,7 @@
sarl $$4, rINST # rINST <- B
GET_VREG %eax, rINST # eax <- vB
andb $$0xf, %cl # ecx <- A
- $instr # for ex: addl %eax,(rFP,%ecx,4)
+ $instr # for ex: addl %eax,VREG_ADDRESS(%ecx)
CLEAR_REF %ecx
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
@@ -240,8 +240,8 @@
movl rIBASE, LOCAL0(%esp) # save rIBASE
GET_VREG rIBASE, %eax # rIBASE <- v[BB+0]
GET_VREG_HIGH %eax, %eax # eax <- v[BB+1]
- $instr1 # ex: addl (rFP,%ecx,4),rIBASE
- $instr2 # ex: adcl 4(rFP,%ecx,4),%eax
+ $instr1 # ex: addl VREG_ADDRESS(%ecx),rIBASE
+ $instr2 # ex: adcl VREG_HIGH_ADDRESS(%ecx),%eax
SET_VREG rIBASE, rINST # v[AA+0] <- rIBASE
movl LOCAL0(%esp), rIBASE # restore rIBASE
SET_VREG_HIGH %eax, rINST # v[AA+1] <- eax
@@ -355,10 +355,10 @@
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
%def op_add_int():
-% binop(instr="addl (rFP,%ecx,4), %eax")
+% binop(instr="addl VREG_ADDRESS(%ecx), %eax")
%def op_add_int_2addr():
-% binop2addr(instr="addl %eax, (rFP,%ecx,4)")
+% binop2addr(instr="addl %eax, VREG_ADDRESS(%ecx)")
%def op_add_int_lit16():
% binopLit16(instr="addl %ecx, %eax")
@@ -367,16 +367,16 @@
% binopLit8(instr="addl %ecx, %eax")
%def op_add_long():
-% binopWide(instr1="addl (rFP,%ecx,4), rIBASE", instr2="adcl 4(rFP,%ecx,4), %eax")
+% binopWide(instr1="addl VREG_ADDRESS(%ecx), rIBASE", instr2="adcl VREG_HIGH_ADDRESS(%ecx), %eax")
%def op_add_long_2addr():
% binopWide2addr(instr1="addl %eax, (rFP,rINST,4)", instr2="adcl %ecx, 4(rFP,rINST,4)")
%def op_and_int():
-% binop(instr="andl (rFP,%ecx,4), %eax")
+% binop(instr="andl VREG_ADDRESS(%ecx), %eax")
%def op_and_int_2addr():
-% binop2addr(instr="andl %eax, (rFP,%ecx,4)")
+% binop2addr(instr="andl %eax, VREG_ADDRESS(%ecx)")
%def op_and_int_lit16():
% binopLit16(instr="andl %ecx, %eax")
@@ -385,7 +385,7 @@
% binopLit8(instr="andl %ecx, %eax")
%def op_and_long():
-% binopWide(instr1="andl (rFP,%ecx,4), rIBASE", instr2="andl 4(rFP,%ecx,4), %eax")
+% binopWide(instr1="andl VREG_ADDRESS(%ecx), rIBASE", instr2="andl VREG_HIGH_ADDRESS(%ecx), %eax")
%def op_and_long_2addr():
% binopWide2addr(instr1="andl %eax, (rFP,rINST,4)", instr2="andl %ecx, 4(rFP,rINST,4)")
@@ -517,7 +517,7 @@
movzbl 3(rPC), %ecx # ecx <- CC
GET_VREG %eax, %eax # eax <- vBB
mov rIBASE, LOCAL0(%esp)
- imull (rFP,%ecx,4), %eax # trashes rIBASE/edx
+ imull VREG_ADDRESS(%ecx), %eax # trashes rIBASE/edx
mov LOCAL0(%esp), rIBASE
SET_VREG %eax, rINST
ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
@@ -529,7 +529,7 @@
GET_VREG %eax, rINST # eax <- vB
andb $$0xf, %cl # ecx <- A
movl rIBASE, rINST
- imull (rFP,%ecx,4), %eax # trashes rIBASE/edx
+ imull VREG_ADDRESS(%ecx), %eax # trashes rIBASE/edx
movl rINST, rIBASE
SET_VREG %eax, %ecx
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
@@ -578,7 +578,7 @@
mov rFP, LOCAL1(%esp) # save FP
mov rIBASE, LOCAL2(%esp) # save rIBASE
leal (rFP,%eax,4), %esi # esi <- &v[B]
- leal (rFP,%ecx,4), rFP # rFP <- &v[C]
+ leal VREG_ADDRESS(%ecx), rFP # rFP <- &v[C]
movl 4(%esi), %ecx # ecx <- Bmsw
imull (rFP), %ecx # ecx <- (Bmsw*Clsw)
movl 4(rFP), %eax # eax <- Cmsw
@@ -666,10 +666,10 @@
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
%def op_or_int():
-% binop(instr="orl (rFP,%ecx,4), %eax")
+% binop(instr="orl VREG_ADDRESS(%ecx), %eax")
%def op_or_int_2addr():
-% binop2addr(instr="orl %eax, (rFP,%ecx,4)")
+% binop2addr(instr="orl %eax, VREG_ADDRESS(%ecx)")
%def op_or_int_lit16():
% binopLit16(instr="orl %ecx, %eax")
@@ -678,7 +678,7 @@
% binopLit8(instr="orl %ecx, %eax")
%def op_or_long():
-% binopWide(instr1="orl (rFP,%ecx,4), rIBASE", instr2="orl 4(rFP,%ecx,4), %eax")
+% binopWide(instr1="orl VREG_ADDRESS(%ecx), rIBASE", instr2="orl VREG_HIGH_ADDRESS(%ecx), %eax")
%def op_or_long_2addr():
% binopWide2addr(instr1="orl %eax, (rFP,rINST,4)", instr2="orl %ecx, 4(rFP,rINST,4)")
@@ -845,13 +845,13 @@
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
%def op_sub_int():
-% binop(instr="subl (rFP,%ecx,4), %eax")
+% binop(instr="subl VREG_ADDRESS(%ecx), %eax")
%def op_sub_int_2addr():
-% binop2addr(instr="subl %eax, (rFP,%ecx,4)")
+% binop2addr(instr="subl %eax, VREG_ADDRESS(%ecx)")
%def op_sub_long():
-% binopWide(instr1="subl (rFP,%ecx,4), rIBASE", instr2="sbbl 4(rFP,%ecx,4), %eax")
+% binopWide(instr1="subl VREG_ADDRESS(%ecx), rIBASE", instr2="sbbl VREG_HIGH_ADDRESS(%ecx), %eax")
%def op_sub_long_2addr():
% binopWide2addr(instr1="subl %eax, (rFP,rINST,4)", instr2="sbbl %ecx, 4(rFP,rINST,4)")
@@ -925,10 +925,10 @@
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
%def op_xor_int():
-% binop(instr="xorl (rFP,%ecx,4), %eax")
+% binop(instr="xorl VREG_ADDRESS(%ecx), %eax")
%def op_xor_int_2addr():
-% binop2addr(instr="xorl %eax, (rFP,%ecx,4)")
+% binop2addr(instr="xorl %eax, VREG_ADDRESS(%ecx)")
%def op_xor_int_lit16():
% binopLit16(instr="xorl %ecx, %eax")
@@ -937,7 +937,7 @@
% binopLit8(instr="xorl %ecx, %eax")
%def op_xor_long():
-% binopWide(instr1="xorl (rFP,%ecx,4), rIBASE", instr2="xorl 4(rFP,%ecx,4), %eax")
+% binopWide(instr1="xorl VREG_ADDRESS(%ecx), rIBASE", instr2="xorl VREG_HIGH_ADDRESS(%ecx), %eax")
%def op_xor_long_2addr():
% binopWide2addr(instr1="xorl %eax, (rFP,rINST,4)", instr2="xorl %ecx, 4(rFP,rINST,4)")
diff --git a/runtime/interpreter/mterp/x86/main.S b/runtime/interpreter/mterp/x86/main.S
index a7451426ff..04b653e24b 100644
--- a/runtime/interpreter/mterp/x86/main.S
+++ b/runtime/interpreter/mterp/x86/main.S
@@ -273,47 +273,47 @@ unspecified registers or condition codes.
#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4)
.macro GET_VREG _reg _vreg
- movl (rFP,\_vreg,4), \_reg
+ movl VREG_ADDRESS(\_vreg), \_reg
.endm
/* Read wide value to xmm. */
.macro GET_WIDE_FP_VREG _reg _vreg
- movq (rFP,\_vreg,4), \_reg
+ movq VREG_ADDRESS(\_vreg), \_reg
.endm
.macro SET_VREG _reg _vreg
- movl \_reg, (rFP,\_vreg,4)
- movl MACRO_LITERAL(0), (rREFS,\_vreg,4)
+ movl \_reg, VREG_ADDRESS(\_vreg)
+ movl MACRO_LITERAL(0), VREG_REF_ADDRESS(\_vreg)
.endm
/* Write wide value from xmm. xmm is clobbered. */
.macro SET_WIDE_FP_VREG _reg _vreg
- movq \_reg, (rFP,\_vreg,4)
+ movq \_reg, VREG_ADDRESS(\_vreg)
pxor \_reg, \_reg
- movq \_reg, (rREFS,\_vreg,4)
+ movq \_reg, VREG_REF_ADDRESS(\_vreg)
.endm
.macro SET_VREG_OBJECT _reg _vreg
- movl \_reg, (rFP,\_vreg,4)
- movl \_reg, (rREFS,\_vreg,4)
+ movl \_reg, VREG_ADDRESS(\_vreg)
+ movl \_reg, VREG_REF_ADDRESS(\_vreg)
.endm
.macro GET_VREG_HIGH _reg _vreg
- movl 4(rFP,\_vreg,4), \_reg
+ movl VREG_HIGH_ADDRESS(\_vreg), \_reg
.endm
.macro SET_VREG_HIGH _reg _vreg
- movl \_reg, 4(rFP,\_vreg,4)
- movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
+ movl \_reg, VREG_HIGH_ADDRESS(\_vreg)
+ movl MACRO_LITERAL(0), VREG_REF_HIGH_ADDRESS(\_vreg)
.endm
.macro CLEAR_REF _vreg
- movl MACRO_LITERAL(0), (rREFS,\_vreg,4)
+ movl MACRO_LITERAL(0), VREG_REF_ADDRESS(\_vreg)
.endm
.macro CLEAR_WIDE_REF _vreg
- movl MACRO_LITERAL(0), (rREFS,\_vreg,4)
- movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
+ movl MACRO_LITERAL(0), VREG_REF_ADDRESS(\_vreg)
+ movl MACRO_LITERAL(0), VREG_REF_HIGH_ADDRESS(\_vreg)
.endm
/*
diff --git a/runtime/interpreter/mterp/x86_64/arithmetic.S b/runtime/interpreter/mterp/x86_64/arithmetic.S
index ffe2008993..263f82b9f6 100644
--- a/runtime/interpreter/mterp/x86_64/arithmetic.S
+++ b/runtime/interpreter/mterp/x86_64/arithmetic.S
@@ -137,7 +137,7 @@
movzbq 2(rPC), %rax # rax <- BB
movzbq 3(rPC), %rcx # rcx <- CC
GET_VREG %eax, %rax # eax <- vBB
- $instr # ex: addl (rFP,%rcx,4),%eax
+ $instr # ex: addl VREG_ADDRESS(%rcx),%eax
SET_VREG $result, rINSTq
ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
@@ -228,7 +228,7 @@
movzbq 2(rPC), %rax # eax <- BB
movzbq 3(rPC), %rcx # ecx <- CC
GET_WIDE_VREG %rax, %rax # rax <- v[BB]
- $instr # ex: addq (rFP,%rcx,4),%rax
+ $instr # ex: addq VREG_ADDRESS(%rcx),%rax
SET_WIDE_VREG %rax, rINSTq # v[AA] <- rax
ADVANCE_PC_FETCH_AND_GOTO_NEXT 2
@@ -241,7 +241,7 @@
sarl $$4, rINST # rINST <- B
andb $$0xf, %cl # ecx <- A
GET_WIDE_VREG %rax, rINSTq # rax <- vB
- $instr # for ex: addq %rax,(rFP,%rcx,4)
+ $instr # for ex: addq %rax,VREG_ADDRESS(%rcx)
CLEAR_WIDE_REF %rcx
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
@@ -317,10 +317,10 @@ $instr
ADVANCE_PC_FETCH_AND_GOTO_NEXT 1
%def op_add_int():
-% binop(instr="addl (rFP,%rcx,4), %eax")
+% binop(instr="addl VREG_ADDRESS(%rcx), %eax")
%def op_add_int_2addr():
-% binop2addr(instr="addl %eax, (rFP,%rcx,4)")
+% binop2addr(instr="addl %eax, VREG_ADDRESS(%rcx)")
%def op_add_int_lit16():
% binopLit16(instr="addl %ecx, %eax")
@@ -329,16 +329,16 @@ $instr
% binopLit8(instr="addl %ecx, %eax")
%def op_add_long():
-% binopWide(instr="addq (rFP,%rcx,4), %rax")
+% binopWide(instr="addq VREG_ADDRESS(%rcx), %rax")
%def op_add_long_2addr():
-% binopWide2addr(instr="addq %rax, (rFP,%rcx,4)")
+% binopWide2addr(instr="addq %rax, VREG_ADDRESS(%rcx)")
%def op_and_int():
-% binop(instr="andl (rFP,%rcx,4), %eax")
+% binop(instr="andl VREG_ADDRESS(%rcx), %eax")
%def op_and_int_2addr():
-% binop2addr(instr="andl %eax, (rFP,%rcx,4)")
+% binop2addr(instr="andl %eax, VREG_ADDRESS(%rcx)")
%def op_and_int_lit16():
% binopLit16(instr="andl %ecx, %eax")
@@ -347,10 +347,10 @@ $instr
% binopLit8(instr="andl %ecx, %eax")
%def op_and_long():
-% binopWide(instr="andq (rFP,%rcx,4), %rax")
+% binopWide(instr="andq VREG_ADDRESS(%rcx), %rax")
%def op_and_long_2addr():
-% binopWide2addr(instr="andq %rax, (rFP,%rcx,4)")
+% binopWide2addr(instr="andq %rax, VREG_ADDRESS(%rcx)")
%def op_cmp_long():
/*
@@ -413,7 +413,7 @@ $instr
% op_move()
%def op_mul_int():
-% binop(instr="imull (rFP,%rcx,4), %eax")
+% binop(instr="imull VREG_ADDRESS(%rcx), %eax")
%def op_mul_int_2addr():
/* mul vA, vB */
@@ -432,7 +432,7 @@ $instr
% binopLit8(instr="imull %ecx, %eax")
%def op_mul_long():
-% binopWide(instr="imulq (rFP,%rcx,4), %rax")
+% binopWide(instr="imulq VREG_ADDRESS(%rcx), %rax")
%def op_mul_long_2addr():
/* mul vA, vB */
@@ -457,10 +457,10 @@ $instr
% unop(instr=" notq %rax", wide="1")
%def op_or_int():
-% binop(instr="orl (rFP,%rcx,4), %eax")
+% binop(instr="orl VREG_ADDRESS(%rcx), %eax")
%def op_or_int_2addr():
-% binop2addr(instr="orl %eax, (rFP,%rcx,4)")
+% binop2addr(instr="orl %eax, VREG_ADDRESS(%rcx)")
%def op_or_int_lit16():
% binopLit16(instr="orl %ecx, %eax")
@@ -469,10 +469,10 @@ $instr
% binopLit8(instr="orl %ecx, %eax")
%def op_or_long():
-% binopWide(instr="orq (rFP,%rcx,4), %rax")
+% binopWide(instr="orq VREG_ADDRESS(%rcx), %rax")
%def op_or_long_2addr():
-% binopWide2addr(instr="orq %rax, (rFP,%rcx,4)")
+% binopWide2addr(instr="orq %rax, VREG_ADDRESS(%rcx)")
%def op_rem_int():
% bindiv(result="%edx", second="%ecx", wide="0", suffix="l", rem="1")
@@ -530,16 +530,16 @@ $instr
% shop2addr(instr="sarq %cl, %rax", wide="1")
%def op_sub_int():
-% binop(instr="subl (rFP,%rcx,4), %eax")
+% binop(instr="subl VREG_ADDRESS(%rcx), %eax")
%def op_sub_int_2addr():
-% binop2addr(instr="subl %eax, (rFP,%rcx,4)")
+% binop2addr(instr="subl %eax, VREG_ADDRESS(%rcx)")
%def op_sub_long():
-% binopWide(instr="subq (rFP,%rcx,4), %rax")
+% binopWide(instr="subq VREG_ADDRESS(%rcx), %rax")
%def op_sub_long_2addr():
-% binopWide2addr(instr="subq %rax, (rFP,%rcx,4)")
+% binopWide2addr(instr="subq %rax, VREG_ADDRESS(%rcx)")
%def op_ushr_int():
% binop1(instr="shrl %cl, %eax")
@@ -557,10 +557,10 @@ $instr
% shop2addr(instr="shrq %cl, %rax", wide="1")
%def op_xor_int():
-% binop(instr="xorl (rFP,%rcx,4), %eax")
+% binop(instr="xorl VREG_ADDRESS(%rcx), %eax")
%def op_xor_int_2addr():
-% binop2addr(instr="xorl %eax, (rFP,%rcx,4)")
+% binop2addr(instr="xorl %eax, VREG_ADDRESS(%rcx)")
%def op_xor_int_lit16():
% binopLit16(instr="xorl %ecx, %eax")
@@ -569,7 +569,7 @@ $instr
% binopLit8(instr="xorl %ecx, %eax")
%def op_xor_long():
-% binopWide(instr="xorq (rFP,%rcx,4), %rax")
+% binopWide(instr="xorq VREG_ADDRESS(%rcx), %rax")
%def op_xor_long_2addr():
-% binopWide2addr(instr="xorq %rax, (rFP,%rcx,4)")
+% binopWide2addr(instr="xorq %rax, VREG_ADDRESS(%rcx)")
diff --git a/runtime/interpreter/mterp/x86_64/main.S b/runtime/interpreter/mterp/x86_64/main.S
index 53a993429e..e283bbee3f 100644
--- a/runtime/interpreter/mterp/x86_64/main.S
+++ b/runtime/interpreter/mterp/x86_64/main.S
@@ -256,50 +256,52 @@ unspecified registers or condition codes.
* Get/set the 32-bit value from a Dalvik register.
*/
#define VREG_ADDRESS(_vreg) (rFP,_vreg,4)
+#define VREG_HIGH_ADDRESS(_vreg) 4(rFP,_vreg,4)
#define VREG_REF_ADDRESS(_vreg) (rREFS,_vreg,4)
+#define VREG_REF_HIGH_ADDRESS(_vreg) 4(rREFS,_vreg,4)
.macro GET_VREG _reg _vreg
- movl (rFP,\_vreg,4), \_reg
+ movl VREG_ADDRESS(\_vreg), \_reg
.endm
/* Read wide value. */
.macro GET_WIDE_VREG _reg _vreg
- movq (rFP,\_vreg,4), \_reg
+ movq VREG_ADDRESS(\_vreg), \_reg
.endm
.macro SET_VREG _reg _vreg
- movl \_reg, (rFP,\_vreg,4)
- movl MACRO_LITERAL(0), (rREFS,\_vreg,4)
+ movl \_reg, VREG_ADDRESS(\_vreg)
+ movl MACRO_LITERAL(0), VREG_REF_ADDRESS(\_vreg)
.endm
/* Write wide value. reg is clobbered. */
.macro SET_WIDE_VREG _reg _vreg
- movq \_reg, (rFP,\_vreg,4)
+ movq \_reg, VREG_ADDRESS(\_vreg)
xorq \_reg, \_reg
- movq \_reg, (rREFS,\_vreg,4)
+ movq \_reg, VREG_REF_ADDRESS(\_vreg)
.endm
.macro SET_VREG_OBJECT _reg _vreg
- movl \_reg, (rFP,\_vreg,4)
- movl \_reg, (rREFS,\_vreg,4)
+ movl \_reg, VREG_ADDRESS(\_vreg)
+ movl \_reg, VREG_REF_ADDRESS(\_vreg)
.endm
.macro GET_VREG_HIGH _reg _vreg
- movl 4(rFP,\_vreg,4), \_reg
+ movl VREG_HIGH_ADDRESS(\_vreg), \_reg
.endm
.macro SET_VREG_HIGH _reg _vreg
- movl \_reg, 4(rFP,\_vreg,4)
- movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
+ movl \_reg, VREG_HIGH_ADDRESS(\_vreg)
+ movl MACRO_LITERAL(0), VREG_REF_HIGH_ADDRESS(\_vreg)
.endm
.macro CLEAR_REF _vreg
- movl MACRO_LITERAL(0), (rREFS,\_vreg,4)
+ movl MACRO_LITERAL(0), VREG_REF_ADDRESS(\_vreg)
.endm
.macro CLEAR_WIDE_REF _vreg
- movl MACRO_LITERAL(0), (rREFS,\_vreg,4)
- movl MACRO_LITERAL(0), 4(rREFS,\_vreg,4)
+ movl MACRO_LITERAL(0), VREG_REF_ADDRESS(\_vreg)
+ movl MACRO_LITERAL(0), VREG_REF_HIGH_ADDRESS(\_vreg)
.endm
/*
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-12-30 07:26:02 +0000