diff options
| -rw-r--r-- | runtime/interpreter/mterp/arm64/fcmp.S | 7 | ||||
| -rw-r--r-- | runtime/interpreter/mterp/arm64/op_cmp_long.S | 4 | ||||
| -rw-r--r-- | runtime/interpreter/mterp/arm64/op_cmpg_double.S | 2 | ||||
| -rw-r--r-- | runtime/interpreter/mterp/arm64/op_cmpg_float.S | 2 | ||||
| -rw-r--r-- | runtime/interpreter/mterp/arm64/op_cmpl_double.S | 2 | ||||
| -rw-r--r-- | runtime/interpreter/mterp/arm64/op_cmpl_float.S | 2 | ||||
| -rw-r--r-- | runtime/interpreter/mterp/out/mterp_arm64.S | 24 |
7 files changed, 19 insertions, 24 deletions
diff --git a/runtime/interpreter/mterp/arm64/fcmp.S b/runtime/interpreter/mterp/arm64/fcmp.S index a45e789f68..cad63189af 100644 --- a/runtime/interpreter/mterp/arm64/fcmp.S +++ b/runtime/interpreter/mterp/arm64/fcmp.S @@ -1,4 +1,4 @@ -%default {"wide":"", "r1":"s1", "r2":"s2", "default_val":"-1","cond":"le"} +%default {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"} /* * Compare two floating-point values. Puts 0, 1, or -1 into the * destination register based on the results of the comparison. @@ -10,10 +10,9 @@ lsr w3, w0, #8 // w3<- CC GET_VREG$wide $r1, w2 GET_VREG$wide $r2, w3 - mov w0, #$default_val fcmp $r1, $r2 - csneg w0, w0, w0, $cond - csel w0, wzr, w0, eq + cset w0, ne + cneg w0, w0, $cond FETCH_ADVANCE_INST 2 // advance rPC, load rINST GET_INST_OPCODE ip // extract opcode from rINST SET_VREG w0, w4 // vAA<- w0 diff --git a/runtime/interpreter/mterp/arm64/op_cmp_long.S b/runtime/interpreter/mterp/arm64/op_cmp_long.S index 982e5b161d..c4ad984084 100644 --- a/runtime/interpreter/mterp/arm64/op_cmp_long.S +++ b/runtime/interpreter/mterp/arm64/op_cmp_long.S @@ -5,8 +5,8 @@ GET_VREG_WIDE x1, w2 GET_VREG_WIDE x2, w3 cmp x1, x2 - csinc w0, wzr, wzr, eq - csneg w0, w0, w0, ge + cset w0, ne + cneg w0, w0, lt FETCH_ADVANCE_INST 2 // advance rPC, load wINST SET_VREG w0, w4 GET_INST_OPCODE ip // extract opcode from wINST diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_double.S b/runtime/interpreter/mterp/arm64/op_cmpg_double.S index 14f9ff8a05..30cb7ebbe2 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpg_double.S +++ b/runtime/interpreter/mterp/arm64/op_cmpg_double.S @@ -1 +1 @@ -%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "default_val":"1", "cond":"pl"} +%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"cc"} diff --git a/runtime/interpreter/mterp/arm64/op_cmpg_float.S b/runtime/interpreter/mterp/arm64/op_cmpg_float.S index 3a20cbae1e..ba23f43462 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpg_float.S +++ b/runtime/interpreter/mterp/arm64/op_cmpg_float.S @@ -1 +1 @@ -%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "default_val":"1", "cond":"pl"} +%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"cc"} diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_double.S b/runtime/interpreter/mterp/arm64/op_cmpl_double.S index 06d59179e1..c73968588e 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpl_double.S +++ b/runtime/interpreter/mterp/arm64/op_cmpl_double.S @@ -1 +1 @@ -%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "default_val":"-1", "cond":"le"} +%include "arm64/fcmp.S" {"wide":"_WIDE", "r1":"d1", "r2":"d2", "cond":"lt"} diff --git a/runtime/interpreter/mterp/arm64/op_cmpl_float.S b/runtime/interpreter/mterp/arm64/op_cmpl_float.S index d87d086259..32a931935b 100644 --- a/runtime/interpreter/mterp/arm64/op_cmpl_float.S +++ b/runtime/interpreter/mterp/arm64/op_cmpl_float.S @@ -1 +1 @@ -%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "default_val":"-1", "cond":"le"} +%include "arm64/fcmp.S" {"wide":"", "r1":"s1", "r2":"s2", "cond":"lt"} diff --git a/runtime/interpreter/mterp/out/mterp_arm64.S b/runtime/interpreter/mterp/out/mterp_arm64.S index d470551173..79d3c9a6f7 100644 --- a/runtime/interpreter/mterp/out/mterp_arm64.S +++ b/runtime/interpreter/mterp/out/mterp_arm64.S @@ -1192,10 +1192,9 @@ artMterpAsmInstructionStart = .L_op_nop lsr w3, w0, #8 // w3<- CC GET_VREG s1, w2 GET_VREG s2, w3 - mov w0, #-1 fcmp s1, s2 - csneg w0, w0, w0, le - csel w0, wzr, w0, eq + cset w0, ne + cneg w0, w0, lt FETCH_ADVANCE_INST 2 // advance rPC, load rINST GET_INST_OPCODE ip // extract opcode from rINST SET_VREG w0, w4 // vAA<- w0 @@ -1218,10 +1217,9 @@ artMterpAsmInstructionStart = .L_op_nop lsr w3, w0, #8 // w3<- CC GET_VREG s1, w2 GET_VREG s2, w3 - mov w0, #1 fcmp s1, s2 - csneg w0, w0, w0, pl - csel w0, wzr, w0, eq + cset w0, ne + cneg w0, w0, cc FETCH_ADVANCE_INST 2 // advance rPC, load rINST GET_INST_OPCODE ip // extract opcode from rINST SET_VREG w0, w4 // vAA<- w0 @@ -1244,10 +1242,9 @@ artMterpAsmInstructionStart = .L_op_nop lsr w3, w0, #8 // w3<- CC GET_VREG_WIDE d1, w2 GET_VREG_WIDE d2, w3 - mov w0, #-1 fcmp d1, d2 - csneg w0, w0, w0, le - csel w0, wzr, w0, eq + cset w0, ne + cneg w0, w0, lt FETCH_ADVANCE_INST 2 // advance rPC, load rINST GET_INST_OPCODE ip // extract opcode from rINST SET_VREG w0, w4 // vAA<- w0 @@ -1270,10 +1267,9 @@ artMterpAsmInstructionStart = .L_op_nop lsr w3, w0, #8 // w3<- CC GET_VREG_WIDE d1, w2 GET_VREG_WIDE d2, w3 - mov w0, #1 fcmp d1, d2 - csneg w0, w0, w0, pl - csel w0, wzr, w0, eq + cset w0, ne + cneg w0, w0, cc FETCH_ADVANCE_INST 2 // advance rPC, load rINST GET_INST_OPCODE ip // extract opcode from rINST SET_VREG w0, w4 // vAA<- w0 @@ -1291,8 +1287,8 @@ artMterpAsmInstructionStart = .L_op_nop GET_VREG_WIDE x1, w2 GET_VREG_WIDE x2, w3 cmp x1, x2 - csinc w0, wzr, wzr, eq - csneg w0, w0, w0, ge + cset w0, ne + cneg w0, w0, lt FETCH_ADVANCE_INST 2 // advance rPC, load wINST SET_VREG w0, w4 GET_INST_OPCODE ip // extract opcode from wINST |