Don't use predicated vectorization by default.

This patch sets the traditional vectorization mode to be
the default one; previously, if the target supported
predicated vectorization (e.g. arm64 SVE), predicated
vectorization was be tried for ALL loops.

Motivation: this is a prerequisite for the further patches
to enable mixed mode vectorization - when most of the loops
are vectorized in traditional mode and some others - in
predicated.

A new env variable - ART_FORCE_TRY_PREDICATED_SIMD - is
introduced to force-use the predicated mode; this could be
set to true for testing purposes.

Checker tests are adjusted accordingly - to also check the
ART_FORCE_TRY_PREDICATED_SIMD variable.

Test: test-art-target, test-art-host.
Test: test-art-target with ART_FORCE_TRY_PREDICATED_SIMD=true.

Original author: Artem Serov <Artem.Serov@linaro.org>

Test: ./art/test/testrunner/testrunner.py --host --optimizing --jit
Test: ./art/test/testrunner/testrunner.py --target --optimizing --jit
      (with ART_FORCE_TRY_PREDICATED_SIMD=true and without)

Test: 661-checker-simd-cf-loops.
Test: target tests on arm64 with SVE
Change-Id: I57852f3777da6f86d615429d1a3c703cb87fbac8

1 files changed, 21 insertions, 21 deletions

diff --git a/test/661-checker-simd-cf-loops/src/Main.java b/test/661-checker-simd-cf-loops/src/Main.java
index 95c09490bb..aee6c6a4f4 100644
--- a/test/661-checker-simd-cf-loops/src/Main.java
+++ b/test/661-checker-simd-cf-loops/src/Main.java
@@ -45,7 +45,7 @@ public class Main {
   public static final float MAGIC_FLOAT_ADD_CONST = 99.0f;
 
   /// CHECK-START-ARM64: int Main.$compile$noinline$FullDiamond(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: <<C0:i\d+>>      IntConstant 0                                         loop:none
   ///     CHECK-DAG: <<C4:i\d+>>      IntConstant 4                                         loop:none
@@ -92,7 +92,7 @@ public class Main {
   //
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleBoolean(boolean[], boolean[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -109,7 +109,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleByte(byte[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -124,7 +124,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleUByte(byte[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -138,7 +138,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleShort(short[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -153,7 +153,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleChar(char[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -168,7 +168,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleInt(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -183,7 +183,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleLong(long[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -200,7 +200,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleFloat(float[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -217,7 +217,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleDouble(double[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -238,7 +238,7 @@ public class Main {
   //
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$ByteConv(byte[], byte[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -253,7 +253,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$UByteAndWrongConst(byte[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -269,7 +269,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$ByteNoHiBits(byte[], byte[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -290,7 +290,7 @@ public class Main {
   //
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$SimpleBelow(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -311,7 +311,7 @@ public class Main {
   //
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$Select(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -329,7 +329,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$Phi(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -350,7 +350,7 @@ public class Main {
   // TODO: when Phis are supported, test dotprod and sad idioms.
 
   /// CHECK-START-ARM64: int Main.$compile$noinline$Reduction(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -369,7 +369,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: int Main.$compile$noinline$ReductionBackEdge(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-DAG: VecLoad
   //
@@ -395,7 +395,7 @@ public class Main {
   public static final int STENCIL_ARRAY_SIZE = 130;
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$stencilAlike(int[], int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -416,7 +416,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$NotDiamondCf(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //
@@ -435,7 +435,7 @@ public class Main {
   }
 
   /// CHECK-START-ARM64: void Main.$compile$noinline$BrokenInduction(int[]) loop_optimization (after)
-  /// CHECK-IF:     hasIsaFeature("sve")
+  /// CHECK-IF:     hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
   //
   ///     CHECK-NOT: VecLoad
   //