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author Artem Serov <artem.serov@arm.com> 2022-09-28 16:06:15 +0100
committer Santiago Aboy Solanes <solanes@google.com> 2024-03-22 08:54:34 +0000
commitc4b188db0eb42d9639e5f66d0d063105024f8960 (patch)
tree8e1bbd22b0e20f1fe739eb8cf6133bedf3088ac2 /test/623-checker-loop-regressions/src/Main.java
parentf4ca2830f238ec7673392389d999bfe98283a459 (diff)
Don't use predicated vectorization by default.
This patch sets the traditional vectorization mode to be the default one; previously, if the target supported predicated vectorization (e.g. arm64 SVE), predicated vectorization was be tried for ALL loops. Motivation: this is a prerequisite for the further patches to enable mixed mode vectorization - when most of the loops are vectorized in traditional mode and some others - in predicated. A new env variable - ART_FORCE_TRY_PREDICATED_SIMD - is introduced to force-use the predicated mode; this could be set to true for testing purposes. Checker tests are adjusted accordingly - to also check the ART_FORCE_TRY_PREDICATED_SIMD variable. Test: test-art-target, test-art-host. Test: test-art-target with ART_FORCE_TRY_PREDICATED_SIMD=true. Original author: Artem Serov <Artem.Serov@linaro.org> Test: ./art/test/testrunner/testrunner.py --host --optimizing --jit Test: ./art/test/testrunner/testrunner.py --target --optimizing --jit (with ART_FORCE_TRY_PREDICATED_SIMD=true and without) Test: 661-checker-simd-cf-loops. Test: target tests on arm64 with SVE Change-Id: I57852f3777da6f86d615429d1a3c703cb87fbac8
Diffstat (limited to 'test/623-checker-loop-regressions/src/Main.java')
-rw-r--r--test/623-checker-loop-regressions/src/Main.java20
1 files changed, 10 insertions, 10 deletions
diff --git a/test/623-checker-loop-regressions/src/Main.java b/test/623-checker-loop-regressions/src/Main.java
index 2b280bb7d6..134e90c6c5 100644
--- a/test/623-checker-loop-regressions/src/Main.java
+++ b/test/623-checker-loop-regressions/src/Main.java
@@ -290,7 +290,7 @@ public class Main {
/// CHECK-NOT: VecLoad
//
/// CHECK-START-ARM64: void Main.string2Bytes(char[], java.lang.String) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// TODO: Support CharAt for SVE.
/// CHECK-NOT: VecLoad
@@ -314,7 +314,7 @@ public class Main {
/// CHECK-NOT: VecLoad
/// CHECK-START-ARM64: void Main.$noinline$stringToShorts(short[], java.lang.String) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// TODO: Support CharAt for SVE.
/// CHECK-NOT: VecLoad
@@ -368,7 +368,7 @@ public class Main {
//
/// CHECK-START-ARM64: void Main.oneBoth(short[], char[]) loop_optimization (after)
/// CHECK-DAG: <<One:i\d+>> IntConstant 1 loop:none
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<One>>,{{j\d+}}] loop:none
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop:B\d+>> outer_loop:none
@@ -423,7 +423,7 @@ public class Main {
//
/// CHECK-START-ARM64: void Main.typeConv(byte[], byte[]) loop_optimization (after)
/// CHECK-DAG: <<One:i\d+>> IntConstant 1 loop:none
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<One>>,{{j\d+}}] loop:none
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile loop:<<Loop1:B\d+>> outer_loop:none
@@ -765,7 +765,7 @@ public class Main {
/// CHECK-DAG: VecStore
//
/// CHECK-START-ARM64: int Main.testSADAndSet(int[], int[], int[]) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// VecSADAccumulate is not supported for SVE.
/// CHECK-NOT: VecSADAccumulate
@@ -793,7 +793,7 @@ public class Main {
/// CHECK-DAG: VecSADAccumulate
//
/// CHECK-START-ARM64: int Main.testSADAndSAD(int[], int[]) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// VecSADAccumulate is not supported for SVE.
/// CHECK-NOT: VecSADAccumulate
@@ -860,7 +860,7 @@ public class Main {
/// CHECK-DAG: VecSADAccumulate
//
/// CHECK-START-ARM64: int Main.testSADAndSADExtraAbs0(int[], int[]) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// VecSADAccumulate is not supported for SVE.
/// CHECK-NOT: VecSADAccumulate
@@ -894,7 +894,7 @@ public class Main {
/// CHECK-DAG: VecSADAccumulate
//
/// CHECK-START-ARM64: int Main.testSADAndSADExtraAbs1(int[], int[]) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// VecSADAccumulate is not supported for SVE.
/// CHECK-NOT: VecSADAccumulate
@@ -923,7 +923,7 @@ public class Main {
// Idioms common sub-expression bug: SAD and DotProd combined.
//
/// CHECK-START-ARM64: int Main.testSADAndDotProdCombined0(byte[], byte[]) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// VecSADAccumulate is not supported for SVE.
/// CHECK-NOT: VecSADAccumulate
@@ -951,7 +951,7 @@ public class Main {
// Idioms common sub-expression bug: SAD and DotProd combined (reversed order).
/// CHECK-START-ARM64: int Main.testSADAndDotProdCombined1(byte[], byte[]) loop_optimization (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// VecSADAccumulate is not supported for SVE.
/// CHECK-NOT: VecSADAccumulate