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author Artem Serov <artem.serov@arm.com> 2022-09-28 16:06:15 +0100
committer Santiago Aboy Solanes <solanes@google.com> 2024-03-22 08:54:34 +0000
commitc4b188db0eb42d9639e5f66d0d063105024f8960 (patch)
tree8e1bbd22b0e20f1fe739eb8cf6133bedf3088ac2 /test/527-checker-array-access-simd/src
parentf4ca2830f238ec7673392389d999bfe98283a459 (diff)
Don't use predicated vectorization by default.
This patch sets the traditional vectorization mode to be the default one; previously, if the target supported predicated vectorization (e.g. arm64 SVE), predicated vectorization was be tried for ALL loops. Motivation: this is a prerequisite for the further patches to enable mixed mode vectorization - when most of the loops are vectorized in traditional mode and some others - in predicated. A new env variable - ART_FORCE_TRY_PREDICATED_SIMD - is introduced to force-use the predicated mode; this could be set to true for testing purposes. Checker tests are adjusted accordingly - to also check the ART_FORCE_TRY_PREDICATED_SIMD variable. Test: test-art-target, test-art-host. Test: test-art-target with ART_FORCE_TRY_PREDICATED_SIMD=true. Original author: Artem Serov <Artem.Serov@linaro.org> Test: ./art/test/testrunner/testrunner.py --host --optimizing --jit Test: ./art/test/testrunner/testrunner.py --target --optimizing --jit (with ART_FORCE_TRY_PREDICATED_SIMD=true and without) Test: 661-checker-simd-cf-loops. Test: target tests on arm64 with SVE Change-Id: I57852f3777da6f86d615429d1a3c703cb87fbac8
Diffstat (limited to 'test/527-checker-array-access-simd/src')
-rw-r--r--test/527-checker-array-access-simd/src/Main.java28
1 files changed, 14 insertions, 14 deletions
diff --git a/test/527-checker-array-access-simd/src/Main.java b/test/527-checker-array-access-simd/src/Main.java
index a08b1f09b4..a26efaeefe 100644
--- a/test/527-checker-array-access-simd/src/Main.java
+++ b/test/527-checker-array-access-simd/src/Main.java
@@ -25,7 +25,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkIntCase(int[]) instruction_simplifier_arm64 (before)
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
// -------------- Loop
@@ -51,7 +51,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkIntCase(int[]) instruction_simplifier_arm64 (after)
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
@@ -84,7 +84,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkIntCase(int[]) GVN$after_arch (after)
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
@@ -114,7 +114,7 @@ public class Main {
/// CHECK-FI:
/// CHECK-START-ARM64: void Main.checkIntCase(int[]) disassembly (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-NOT: IntermediateAddressIndex
@@ -134,7 +134,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkByteCase(byte[]) instruction_simplifier_arm64 (before)
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
// -------------- Loop
@@ -161,7 +161,7 @@ public class Main {
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const0:i\d+>> IntConstant 0
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
@@ -194,7 +194,7 @@ public class Main {
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const0:i\d+>> IntConstant 0
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
@@ -223,7 +223,7 @@ public class Main {
/// CHECK-FI:
/// CHECK-START-ARM64: void Main.checkByteCase(byte[]) disassembly (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-NOT: IntermediateAddressIndex
@@ -247,7 +247,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkSingleAccess(int[]) instruction_simplifier_arm64 (before)
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
// -------------- Loop
@@ -270,7 +270,7 @@ public class Main {
/// CHECK-DAG: <<Array:l\d+>> ParameterValue
/// CHECK-DAG: <<Const0:i\d+>> IntConstant 0
/// CHECK-DAG: <<Const5:i\d+>> IntConstant 5
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<Repl:d\d+>> VecReplicateScalar [<<Const5>>,{{j\d+}}]
// -------------- Loop
@@ -301,7 +301,7 @@ public class Main {
/// CHECK-DAG: <<Array1:l\d+>> ParameterValue
/// CHECK-DAG: <<Array2:l\d+>> ParameterValue
// -------------- Loop
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
/// CHECK-DAG: <<LoopP:j\d+>> VecPredWhile
/// CHECK-DAG: <<Index:i\d+>> Phi
@@ -323,7 +323,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) instruction_simplifier_arm64 (after)
/// CHECK-DAG: <<Array1:l\d+>> ParameterValue
/// CHECK-DAG: <<Array2:l\d+>> ParameterValue
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
// -------------- Loop
@@ -354,7 +354,7 @@ public class Main {
/// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) GVN$after_arch (after)
/// CHECK-DAG: <<Array1:l\d+>> ParameterValue
/// CHECK-DAG: <<Array2:l\d+>> ParameterValue
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
// -------------- Loop
@@ -383,7 +383,7 @@ public class Main {
/// CHECK-FI:
/// CHECK-START-ARM64: void Main.checkInt2Float(int[], float[]) disassembly (after)
- /// CHECK-IF: hasIsaFeature("sve")
+ /// CHECK-IF: hasIsaFeature("sve") and os.environ.get('ART_FORCE_TRY_PREDICATED_SIMD') == 'true'
//
// IntermediateAddressIndex is not supported for SVE.
/// CHECK-NOT: IntermediateAddressIndex
generated by cgit v1.2.3-59-g8ed1b (git 2.39.0) at 2025-10-21 14:49:08 +0000