Quick compiler: refactored listing & const fix

This CL started off as a simple fix to Issue 4959751, which
identified a case in which compiler debugging listings could read
uninitialized data.  The fix ended up pulling a few strings - we
had two distinct dex printing routines (one was focused on SSA names
and was used by the .dot graph dumper), while the other was used with
verbose codegen listing.

Ended up combining the two routines and significantly enhancing the
value of the verbose debug output.  We now always use ssa register
names, and also show the constant values of ssa names which are known
to be const following constant propagation.

Along the way, deleted a bit of useless code that remapped all
registers in a phi set to have the same name, and also got rid of
some duplicate listing helper LIR pseudo ops.

Somee examples of the new listing:

-------- dalvik offset: 0x2 @ const/4 v0_1#0x1, #1

the format of the vreg is:
   v<orignal Dalvik vnum>_<ssa instance>[#hex value of immediate]

In this example, we don't add any new info (the listing already had #1),
but we also show this form in uses:

invoke-virtual v0_2, v1_3#0x40

Also improved is the listing output of potentially throwing instructions
which are broken into two parts: the check portion and the work portion.
Both halves now show the full disassembly.  For example:

-------- dalvik offset: 0x13 @ Check1: invoke-virtual v0_2, v1_3#0x40
....code here
....code here
-------- dalvik offset: 0x13 @ Check2: invoke-virtual v0_2, v1_3#0x40

Dalvik instructions which are optimized away prior to code generation
are displayed in sqare brackets.  For example:

-------- dalvik offset: 0x16 @ [move-result-object v0_3]--optimized away

Finally, Phi nodes show which incoming block an operand came through.
In the following example:

-------- dalvik offset: 0x5 @ Phi v1_2 = (v1_1#0x0:4, v1_2:12, v1_3#0x1:14)

Sreg v1_2 is a merge of a constant 0x0 from incoming block 4, a non-const
value from block 12 and a const 0x1 from block 14.

Change-Id: Ib6c19c19ab8a48509d43d8b0e5ed3e8e7ce9fc82

8 files changed, 7 insertions, 90 deletions

diff --git a/src/compiler/codegen/arm/call_arm.cc b/src/compiler/codegen/arm/call_arm.cc
index 950105c9d2..9696bcab6f 100644
--- a/src/compiler/codegen/arm/call_arm.cc
+++ b/src/compiler/codegen/arm/call_arm.cc
@@ -129,13 +129,8 @@ void ArmCodegen::GenPrintLabel(CompilationUnit *cu, MIR* mir)
 {
   /* Mark the beginning of a Dalvik instruction for line tracking */
   char* inst_str = cu->verbose ?
-     GetDalvikDisassembly(cu, mir->dalvikInsn, "") : NULL;
+     GetDalvikDisassembly(cu, mir) : NULL;
   MarkBoundary(cu, mir->offset, inst_str);
-  /* Don't generate the SSA annotation unless verbose mode is on */
-  if (cu->verbose && mir->ssa_rep) {
-    char* ssa_string = GetSSAString(cu, mir->ssa_rep);
-    NewLIR1(cu, kPseudoSSARep, reinterpret_cast<uintptr_t>(ssa_string));
-  }
 }
 
 static MIR* SpecialIGet(CompilationUnit* cu, BasicBlock** bb, MIR* mir,
diff --git a/src/compiler/codegen/arm/target_arm.cc b/src/compiler/codegen/arm/target_arm.cc
index 272dc46716..493b4a9aca 100644
--- a/src/compiler/codegen/arm/target_arm.cc
+++ b/src/compiler/codegen/arm/target_arm.cc
@@ -584,23 +584,6 @@ void ArmCodegen::CompilerInitializeRegAlloc(CompilationUnit* cu)
 
   // Start allocation at r2 in an attempt to avoid clobbering return values
   pool->next_core_reg = r2;
-
-  // Construct the alias map.
-  cu->phi_alias_map = static_cast<int*>
-      (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
-  for (int i = 0; i < cu->num_ssa_regs; i++) {
-    cu->phi_alias_map[i] = i;
-  }
-  for (MIR* phi = cu->phi_list; phi; phi = phi->meta.phi_next) {
-    int def_reg = phi->ssa_rep->defs[0];
-    for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
-       for (int j = 0; j < cu->num_ssa_regs; j++) {
-         if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
-           cu->phi_alias_map[j] = def_reg;
-         }
-       }
-    }
-  }
 }
 
 void ArmCodegen::FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep,
diff --git a/src/compiler/codegen/codegen_util.cc b/src/compiler/codegen/codegen_util.cc
index 11ab9c0a96..bab5cd98c5 100644
--- a/src/compiler/codegen/codegen_util.cc
+++ b/src/compiler/codegen/codegen_util.cc
@@ -177,7 +177,6 @@ void SetupResourceMasks(CompilationUnit* cu, LIR* lir)
  * Debugging macros
  */
 #define DUMP_RESOURCE_MASK(X)
-#define DUMP_SSA_REP(X)
 
 /* Pretty-print a LIR instruction */
 void DumpLIRInsn(CompilationUnit* cu, LIR* lir, unsigned char* base_addr)
@@ -199,12 +198,6 @@ void DumpLIRInsn(CompilationUnit* cu, LIR* lir, unsigned char* base_addr)
     case kPseudoBarrier:
       LOG(INFO) << "-------- BARRIER";
       break;
-    case kPseudoExtended:
-      LOG(INFO) << "-------- " << reinterpret_cast<char*>(dest);
-      break;
-    case kPseudoSSARep:
-      DUMP_SSA_REP(LOG(INFO) << "-------- kMirOpPhi: " <<  reinterpret_cast<char*>(dest));
-      break;
     case kPseudoEntryBlock:
       LOG(INFO) << "-------- entry offset: 0x" << std::hex << dest;
       break;
diff --git a/src/compiler/codegen/gen_invoke.cc b/src/compiler/codegen/gen_invoke.cc
index afaa053f95..ebc1a986ca 100644
--- a/src/compiler/codegen/gen_invoke.cc
+++ b/src/compiler/codegen/gen_invoke.cc
@@ -1337,7 +1337,8 @@ CallInfo* Codegen::NewMemCallInfo(CompilationUnit* cu, BasicBlock* bb, MIR* mir,
     info->result.location = kLocInvalid;
   } else {
     info->result = GetRawDest(cu, move_result_mir);
-    move_result_mir->dalvikInsn.opcode = Instruction::NOP;
+    move_result_mir->meta.original_opcode = move_result_mir->dalvikInsn.opcode;
+    move_result_mir->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
   }
   info->num_arg_words = mir->ssa_rep->num_uses;
   info->args = (info->num_arg_words == 0) ? NULL : static_cast<RegLocation*>
diff --git a/src/compiler/codegen/mips/target_mips.cc b/src/compiler/codegen/mips/target_mips.cc
index ed884b21d4..3bb46896a5 100644
--- a/src/compiler/codegen/mips/target_mips.cc
+++ b/src/compiler/codegen/mips/target_mips.cc
@@ -516,22 +516,6 @@ void MipsCodegen::CompilerInitializeRegAlloc(CompilationUnit* cu)
   for (int i = 0; i < num_fp_temps; i++) {
     MarkTemp(cu, fp_temps[i]);
   }
-  // Construct the alias map.
-  cu->phi_alias_map = static_cast<int*>
-      (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
-  for (int i = 0; i < cu->num_ssa_regs; i++) {
-    cu->phi_alias_map[i] = i;
-  }
-  for (MIR* phi = cu->phi_list; phi; phi = phi->meta.phi_next) {
-    int def_reg = phi->ssa_rep->defs[0];
-    for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
-       for (int j = 0; j < cu->num_ssa_regs; j++) {
-         if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
-           cu->phi_alias_map[j] = def_reg;
-         }
-       }
-    }
-  }
 }
 
 void MipsCodegen::FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep, RegLocation rl_free)
diff --git a/src/compiler/codegen/mir_to_gbc.cc b/src/compiler/codegen/mir_to_gbc.cc
index 2c27bb0dc5..6758bb9f69 100644
--- a/src/compiler/codegen/mir_to_gbc.cc
+++ b/src/compiler/codegen/mir_to_gbc.cc
@@ -1824,6 +1824,7 @@ static bool BlockBitcodeConversion(CompilationUnit* cu, BasicBlock* bb)
       SSARepresentation* ssa_rep = work_half->ssa_rep;
       work_half->ssa_rep = mir->ssa_rep;
       mir->ssa_rep = ssa_rep;
+      work_half->meta.original_opcode = work_half->dalvikInsn.opcode;
       work_half->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
       if (bb->successor_block_list.block_list_type == kCatch) {
         llvm::Function* intr = cu->intrinsic_helper->GetIntrinsicFunction(
diff --git a/src/compiler/codegen/mir_to_lir.cc b/src/compiler/codegen/mir_to_lir.cc
index fc3df6ec91..6ec7edbf1f 100644
--- a/src/compiler/codegen/mir_to_lir.cc
+++ b/src/compiler/codegen/mir_to_lir.cc
@@ -611,29 +611,11 @@ static bool CompileDalvikInstruction(CompilationUnit* cu, MIR* mir, BasicBlock*
   return res;
 }
 
-// Process extended MIR instructions (such as PHI).
+// Process extended MIR instructions
 static void HandleExtendedMethodMIR(CompilationUnit* cu, BasicBlock* bb, MIR* mir)
 {
   Codegen* cg = cu->cg.get();
-  int op_offset = mir->dalvikInsn.opcode - kMirOpFirst;
-  char* msg = NULL;
-  if (cu->verbose) {
-    msg = static_cast<char*>(NewMem(cu, strlen(extended_mir_op_names[op_offset]) + 1,
-                                    false, kAllocDebugInfo));
-    strcpy(msg, extended_mir_op_names[op_offset]);
-  }
-  LIR* op = NewLIR1(cu, kPseudoExtended, reinterpret_cast<uintptr_t>(msg));
-
   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {
-    case kMirOpPhi: {
-      char* ssa_string = NULL;
-      if (cu->verbose) {
-        ssa_string = GetSSAString(cu, mir->ssa_rep);
-      }
-      op->flags.is_nop = true;
-      NewLIR1(cu, kPseudoSSARep, reinterpret_cast<uintptr_t>(ssa_string));
-      break;
-    }
     case kMirOpCopy: {
       RegLocation rl_src = GetSrc(cu, mir, 0);
       RegLocation rl_dest = GetDest(cu, mir);
@@ -719,7 +701,7 @@ static bool MethodBlockCodeGen(CompilationUnit* cu, BasicBlock* bb)
 
     // Mark the beginning of a Dalvik instruction for line tracking.
     char* inst_str = cu->verbose ?
-       GetDalvikDisassembly(cu, mir->dalvikInsn, "") : NULL;
+       GetDalvikDisassembly(cu, mir) : NULL;
     boundary_lir = MarkBoundary(cu, mir->offset, inst_str);
     // Remember the first LIR for this block.
     if (head_lir == NULL) {
@@ -728,12 +710,6 @@ static bool MethodBlockCodeGen(CompilationUnit* cu, BasicBlock* bb)
       head_lir->def_mask = ENCODE_ALL;
     }
 
-    // Don't generate the SSA annotation unless verbose mode is on.
-    if (cu->verbose && mir->ssa_rep) {
-      char* ssa_string = GetSSAString(cu, mir->ssa_rep);
-      NewLIR1(cu, kPseudoSSARep, reinterpret_cast<uintptr_t>(ssa_string));
-    }
-
     if (opcode == kMirOpCheck) {
       // Combine check and work halves of throwing instruction.
       MIR* work_half = mir->meta.throw_insn;
@@ -742,7 +718,7 @@ static bool MethodBlockCodeGen(CompilationUnit* cu, BasicBlock* bb)
       SSARepresentation* ssa_rep = work_half->ssa_rep;
       work_half->ssa_rep = mir->ssa_rep;
       mir->ssa_rep = ssa_rep;
-      work_half->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpNop);
+      work_half->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpCheckPart2);
     }
 
     if (opcode >= kMirOpFirst) {
diff --git a/src/compiler/codegen/x86/target_x86.cc b/src/compiler/codegen/x86/target_x86.cc
index c3c79f17b3..e396e54717 100644
--- a/src/compiler/codegen/x86/target_x86.cc
+++ b/src/compiler/codegen/x86/target_x86.cc
@@ -484,22 +484,6 @@ void X86Codegen::CompilerInitializeRegAlloc(CompilationUnit* cu) {
   for (int i = 0; i < num_fp_temps; i++) {
     MarkTemp(cu, fp_temps[i]);
   }
-  // Construct the alias map.
-  cu->phi_alias_map = static_cast<int*>
-      (NewMem(cu, cu->num_ssa_regs * sizeof(cu->phi_alias_map[0]), false, kAllocDFInfo));
-  for (int i = 0; i < cu->num_ssa_regs; i++) {
-    cu->phi_alias_map[i] = i;
-  }
-  for (MIR* phi = cu->phi_list; phi != NULL; phi = phi->meta.phi_next) {
-    int def_reg = phi->ssa_rep->defs[0];
-    for (int i = 0; i < phi->ssa_rep->num_uses; i++) {
-      for (int j = 0; j < cu->num_ssa_regs; j++) {
-        if (cu->phi_alias_map[j] == phi->ssa_rep->uses[i]) {
-          cu->phi_alias_map[j] = def_reg;
-        }
-      }
-    }
-  }
 }
 
 void X86Codegen::FreeRegLocTemps(CompilationUnit* cu, RegLocation rl_keep,