More MIPS support

Working through the unimps.

Change-Id: Ie088d2061ca9a77f42ebd75e2936159465deed10

4 files changed, 51 insertions, 42 deletions

diff --git a/src/compiler/codegen/mips/ArchFactory.cc b/src/compiler/codegen/mips/ArchFactory.cc
index aaaa50f6ac..963427ddce 100644
--- a/src/compiler/codegen/mips/ArchFactory.cc
+++ b/src/compiler/codegen/mips/ArchFactory.cc
@@ -145,7 +145,7 @@ void genExitSequence(CompilationUnit* cUnit, BasicBlock* bb)
         genDebuggerUpdate(cUnit, DEBUGGER_METHOD_EXIT);
     }
     unSpillCoreRegs(cUnit);
-    opReg(cUnit, kOpBx, rLINK);
+    opReg(cUnit, kOpBx, r_RA);
 }
 
 /*
diff --git a/src/compiler/codegen/mips/Assemble.cc b/src/compiler/codegen/mips/Assemble.cc
index 4deb8f5f31..0021318c6d 100644
--- a/src/compiler/codegen/mips/Assemble.cc
+++ b/src/compiler/codegen/mips/Assemble.cc
@@ -527,7 +527,6 @@ AssemblerStatus oatAssembleInstructions(CompilationUnit *cUnit,
                                << (int)encoder->fieldLoc[i].kind;
             }
         }
-        DCHECK_EQ(encoder->size, 4);
         // FIXME: need multi-endian handling here
         cUnit->codeBuffer.push_back((bits >> 16) & 0xffff);
         cUnit->codeBuffer.push_back(bits & 0xffff);
diff --git a/src/compiler/codegen/mips/Mips32/Gen.cc b/src/compiler/codegen/mips/Mips32/Gen.cc
index db34ce35bb..155675c700 100644
--- a/src/compiler/codegen/mips/Mips32/Gen.cc
+++ b/src/compiler/codegen/mips/Mips32/Gen.cc
@@ -274,45 +274,54 @@ void genCmpLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
 LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
                  int src2, LIR* target)
 {
-   LIR* branch;
-    if (cond == kCondEq) {
-        branch = newLIR2(cUnit, kMipsBeq, src1, src2);
-    } else if (cond == kCondNe) {
-        branch = newLIR2(cUnit, kMipsBne, src1, src2);
+    LIR* branch;
+    MipsOpCode sltOp;
+    MipsOpCode brOp;
+    bool cmpZero = false;
+    bool swapped = false;
+    switch(cond) {
+        case kCondEq:
+            brOp = kMipsBeq;
+            cmpZero = true;
+            break;
+        case kCondNe:
+            brOp = kMipsBne;
+            cmpZero = true;
+            break;
+        case kCondCc:
+            sltOp = kMipsSltu;
+            brOp = kMipsBnez;
+            break;
+        case kCondCs:
+            sltOp = kMipsSltu;
+            brOp = kMipsBeqz;
+            break;
+        case kCondGe:
+            sltOp = kMipsSlt;
+            brOp = kMipsBeqz;
+            break;
+        case kCondGt:
+            sltOp = kMipsSlt;
+            brOp = kMipsBnez;
+            swapped = true;
+            break;
+        case kCondLe:
+            sltOp = kMipsSlt;
+            brOp = kMipsBeqz;
+            swapped = true;
+            break;
+        case kCondLt:
+            sltOp = kMipsSlt;
+            brOp = kMipsBnez;
+            break;
+        default:
+            UNIMPLEMENTED(FATAL) << "No support for ConditionCode: "
+                                 << (int) cond;
+            return NULL;
+    }
+    if (cmpZero) {
+        branch = newLIR2(cUnit, brOp, src1, src2);
     } else {
-        MipsOpCode sltOp;
-        MipsOpCode brOp;
-        bool swapped = false;
-        switch(cond) {
-            case kCondEq: return newLIR2(cUnit, kMipsBeq, src1, src2);
-            case kCondNe: return newLIR2(cUnit, kMipsBne, src1, src2);
-            case kCondCc:
-                sltOp = kMipsSltu;
-                brOp = kMipsBnez;
-                break;
-            case kCondGe:
-                sltOp = kMipsSlt;
-                brOp = kMipsBeqz;
-                break;
-            case kCondGt:
-                sltOp = kMipsSlt;
-                brOp = kMipsBnez;
-                swapped = true;
-                break;
-            case kCondLe:
-                sltOp = kMipsSlt;
-                brOp = kMipsBeqz;
-                swapped = true;
-                break;
-            case kCondLt:
-                sltOp = kMipsSlt;
-                brOp = kMipsBnez;
-                break;
-            default:
-                UNIMPLEMENTED(FATAL) << "No support for ConditionCode: "
-                                     << (int) cond;
-                return NULL;
-        }
         int tReg = oatAllocTemp(cUnit);
         if (swapped) {
             newLIR3(cUnit, sltOp, tReg, src2, src1);
@@ -320,8 +329,9 @@ LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,
             newLIR3(cUnit, sltOp, tReg, src1, src2);
         }
         branch = newLIR1(cUnit, brOp, tReg);
-        branch->target = target;
+        oatFreeTemp(cUnit, tReg);
     }
+    branch->target = target;
     return branch;
 }
 
diff --git a/src/compiler/codegen/mips/MipsLIR.h b/src/compiler/codegen/mips/MipsLIR.h
index 67f3131a70..b2cfdbed59 100644
--- a/src/compiler/codegen/mips/MipsLIR.h
+++ b/src/compiler/codegen/mips/MipsLIR.h
@@ -301,7 +301,7 @@ typedef enum NativeRegisterPool {
 #define rARG3 r_ARG3
 #define rRET0 r_RESULT0
 #define rRET1 r_RESULT1
-#define rLINK r_RA
+#define rINVOKE_TGT r_V0
 
 /* Shift encodings */
 typedef enum MipsShiftEncodings {