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author buzbee <buzbee@google.com> 2012-03-03 11:48:39 -0800
committer buzbee <buzbee@google.com> 2012-03-03 16:32:24 -0800
commitc5159d55ca8e9022b748176f9f53676e8e9d4cd2 (patch)
treed407a682788fbbca4dbd0821350058a3c2901617 /src/compiler/codegen/mips/Codegen.h
parent5b455485c1deda58959fdc410050e01448c032c2 (diff)
MIPS switch table support
And 64-bit neg/add/sub (ouch! Mips has no carry bit...) Change-Id: Ifb94324a0052d6069977fb8f22679b95890445d8
Diffstat (limited to 'src/compiler/codegen/mips/Codegen.h')
-rw-r--r--src/compiler/codegen/mips/Codegen.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/compiler/codegen/mips/Codegen.h b/src/compiler/codegen/mips/Codegen.h
index c6f1d98b0f..520d638fe7 100644
--- a/src/compiler/codegen/mips/Codegen.h
+++ b/src/compiler/codegen/mips/Codegen.h
@@ -27,6 +27,12 @@
namespace art {
#if defined(_CODEGEN_C)
+bool genAddLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+ RegLocation rlSrc1, RegLocation rlSrc2);
+bool genSubLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+ RegLocation rlSrc1, RegLocation rlSrc2);
+bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+ RegLocation rlSrc);
LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
LIR* opCmpBranch(CompilationUnit* cUnit, ConditionCode cond, int src1,