Merge "Quick backend: rename target-specific #defines" into dalvik-dev

1 files changed, 90 insertions, 5 deletions

diff --git a/src/compiler/codegen/mips/ArchUtility.cc b/src/compiler/codegen/mips/ArchUtility.cc
index 9a2b923baf..3063e69518 100644
--- a/src/compiler/codegen/mips/ArchUtility.cc
+++ b/src/compiler/codegen/mips/ArchUtility.cc
@@ -22,6 +22,91 @@
 
 namespace art {
 
+RegLocation locCReturn()
+{
+  RegLocation res = MIPS_LOC_C_RETURN;
+  return res;
+}
+
+RegLocation locCReturnWide()
+{
+  RegLocation res = MIPS_LOC_C_RETURN_WIDE;
+  return res;
+}
+
+RegLocation locCReturnFloat()
+{
+  RegLocation res = MIPS_LOC_C_RETURN_FLOAT;
+  return res;
+}
+
+RegLocation locCReturnDouble()
+{
+  RegLocation res = MIPS_LOC_C_RETURN_DOUBLE;
+  return res;
+}
+
+// Return a target-dependent special register.
+int targetReg(SpecialTargetRegister reg) {
+  int res = INVALID_REG;
+  switch (reg) {
+    case kSelf: res = rMIPS_SELF; break;
+    case kSuspend: res =  rMIPS_SUSPEND; break;
+    case kLr: res =  rMIPS_LR; break;
+    case kPc: res =  rMIPS_PC; break;
+    case kSp: res =  rMIPS_SP; break;
+    case kArg0: res = rMIPS_ARG0; break;
+    case kArg1: res = rMIPS_ARG1; break;
+    case kArg2: res = rMIPS_ARG2; break;
+    case kArg3: res = rMIPS_ARG3; break;
+    case kFArg0: res = rMIPS_FARG0; break;
+    case kFArg1: res = rMIPS_FARG1; break;
+    case kFArg2: res = rMIPS_FARG2; break;
+    case kFArg3: res = rMIPS_FARG3; break;
+    case kRet0: res = rMIPS_RET0; break;
+    case kRet1: res = rMIPS_RET1; break;
+    case kInvokeTgt: res = rMIPS_INVOKE_TGT; break;
+    case kCount: res = rMIPS_COUNT; break;
+  }
+  return res;
+}
+
+// Create a double from a pair of singles.
+int s2d(int lowReg, int highReg)
+{
+  return MIPS_S2D(lowReg, highReg);
+}
+
+// Is reg a single or double?
+bool fpReg(int reg)
+{
+  return MIPS_FPREG(reg);
+}
+
+// Is reg a single?
+bool singleReg(int reg)
+{
+  return MIPS_SINGLEREG(reg);
+}
+
+// Is reg a double?
+bool doubleReg(int reg)
+{
+  return MIPS_DOUBLEREG(reg);
+}
+
+// Return mask to strip off fp reg flags and bias.
+uint32_t fpRegMask()
+{
+  return MIPS_FP_REG_MASK;
+}
+
+// True if both regs single, both core or both double.
+bool sameRegType(int reg1, int reg2)
+{
+  return (MIPS_REGTYPE(reg1) == MIPS_REGTYPE(reg2));
+}
+
 /*
  * Decode the register id.
  */
@@ -34,9 +119,9 @@ u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
 
   regId = reg & 0x1f;
   /* Each double register is equal to a pair of single-precision FP registers */
-  seed = DOUBLEREG(reg) ? 3 : 1;
+  seed = MIPS_DOUBLEREG(reg) ? 3 : 1;
   /* FP register starts at bit position 16 */
-  shift = FPREG(reg) ? kMipsFPReg0 : 0;
+  shift = MIPS_FPREG(reg) ? kMipsFPReg0 : 0;
   /* Expand the double register id into single offset */
   shift += regId;
   return (seed << shift);
@@ -109,11 +194,11 @@ std::string buildInsnString(const char *fmt, LIR *lir, unsigned char* baseAddr)
              }
              break;
            case 's':
-             sprintf(tbuf,"$f%d",operand & FP_REG_MASK);
+             sprintf(tbuf,"$f%d",operand & MIPS_FP_REG_MASK);
              break;
            case 'S':
-             DCHECK_EQ(((operand & FP_REG_MASK) & 1), 0);
-             sprintf(tbuf,"$f%d",operand & FP_REG_MASK);
+             DCHECK_EQ(((operand & MIPS_FP_REG_MASK) & 1), 0);
+             sprintf(tbuf,"$f%d",operand & MIPS_FP_REG_MASK);
              break;
            case 'h':
              sprintf(tbuf,"%04x", operand);