Revert "Revert "Refactor codegen resource masks""

This reverts commit 4b39c9f1b77ff32cf5760e6bf77c189678e2c9a6.

The problem with the original commit was failure to widen a
couple of local variables to hold the newly widenened to 64-bits
EncodingMap flag field - thus we lost some high-order resource
attributes and broke instruction scheduling for x86.

Change-Id: I04d7caf79e2cc802c39369ca04666629218ccaea

2 files changed, 59 insertions, 127 deletions

diff --git a/src/compiler/codegen/arm/ArchUtility.cc b/src/compiler/codegen/arm/ArchUtility.cc
index 820f64e643..8746b6866e 100644
--- a/src/compiler/codegen/arm/ArchUtility.cc
+++ b/src/compiler/codegen/arm/ArchUtility.cc
@@ -22,24 +22,57 @@
 
 namespace art {
 
+/*
+ * Decode the register id.
+ */
+u8 getRegMaskCommon(CompilationUnit* cUnit, int reg)
+{
+  u8 seed;
+  int shift;
+  int regId;
+
+
+  regId = reg & 0x1f;
+  /* Each double register is equal to a pair of single-precision FP registers */
+  seed = DOUBLEREG(reg) ? 3 : 1;
+  /* FP register starts at bit position 16 */
+  shift = FPREG(reg) ? kArmFPReg0 : 0;
+  /* Expand the double register id into single offset */
+  shift += regId;
+  return (seed << shift);
+}
+
+uint64_t getPCUseDefEncoding()
+{
+  return ENCODE_ARM_REG_PC;
+}
+
 void setupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
 {
   DCHECK_EQ(cUnit->instructionSet, kThumb2);
 
   // Thumb2 specific setup
-  int flags = EncodingMap[lir->opcode].flags;
+  uint64_t flags = EncodingMap[lir->opcode].flags;
   int opcode = lir->opcode;
 
+  if (flags & REG_DEF_SP) {
+    lir->defMask |= ENCODE_ARM_REG_SP;
+  }
+
+  if (flags & REG_USE_SP) {
+    lir->useMask |= ENCODE_ARM_REG_SP;
+  }
+
   if (flags & REG_DEF_LIST0) {
-    lir->defMask |= ENCODE_REG_LIST(lir->operands[0]);
+    lir->defMask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
   }
 
   if (flags & REG_DEF_LIST1) {
-    lir->defMask |= ENCODE_REG_LIST(lir->operands[1]);
+    lir->defMask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
   }
 
   if (flags & REG_DEF_FPCS_LIST0) {
-    lir->defMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
+    lir->defMask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
   }
 
   if (flags & REG_DEF_FPCS_LIST2) {
@@ -49,7 +82,7 @@ void setupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
   }
 
   if (flags & REG_USE_PC) {
-    lir->useMask |= ENCODE_REG_PC;
+    lir->useMask |= ENCODE_ARM_REG_PC;
   }
 
   /* Conservatively treat the IT block */
@@ -58,15 +91,15 @@ void setupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
   }
 
   if (flags & REG_USE_LIST0) {
-    lir->useMask |= ENCODE_REG_LIST(lir->operands[0]);
+    lir->useMask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
   }
 
   if (flags & REG_USE_LIST1) {
-    lir->useMask |= ENCODE_REG_LIST(lir->operands[1]);
+    lir->useMask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
   }
 
   if (flags & REG_USE_FPCS_LIST0) {
-    lir->useMask |= ENCODE_REG_FPCS_LIST(lir->operands[0]);
+    lir->useMask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
   }
 
   if (flags & REG_USE_FPCS_LIST2) {
@@ -79,14 +112,14 @@ void setupTargetResourceMasks(CompilationUnit* cUnit, LIR* lir)
     u8 r8Mask = oatGetRegMaskCommon(cUnit, r8);
     if ((opcode == kThumbPush) && (lir->useMask & r8Mask)) {
       lir->useMask &= ~r8Mask;
-      lir->useMask |= ENCODE_REG_LR;
+      lir->useMask |= ENCODE_ARM_REG_LR;
     } else if ((opcode == kThumbPop) && (lir->defMask & r8Mask)) {
       lir->defMask &= ~r8Mask;
-      lir->defMask |= ENCODE_REG_PC;
+      lir->defMask |= ENCODE_ARM_REG_PC;
     }
   }
   if (flags & REG_DEF_LR) {
-    lir->defMask |= ENCODE_REG_LR;
+    lir->defMask |= ENCODE_ARM_REG_LR;
   }
 }
 
@@ -354,7 +387,7 @@ void oatDumpResourceMask(LIR* lir, u8 mask, const char* prefix)
     char num[8];
     int i;
 
-    for (i = 0; i < kRegEnd; i++) {
+    for (i = 0; i < kArmRegEnd; i++) {
       if (mask & (1ULL << i)) {
         sprintf(num, "%d ", i);
         strcat(buf, num);
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index 407ad793c0..05082ed8d8 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -22,9 +22,6 @@
 
 namespace art {
 
-// Set to 1 to measure cost of suspend check
-#define NO_SUSPEND 0
-
 /*
  * Runtime register usage conventions.
  *
@@ -132,43 +129,21 @@ namespace art {
 #define LOC_C_RETURN_FLOAT  LOC_C_RETURN
 #define LOC_C_RETURN_WIDE_DOUBLE  LOC_C_RETURN_WIDE
 
-enum ResourceEncodingPos {
-  kGPReg0   = 0,
-  kRegSP    = 13,
-  kRegLR    = 14,
-  kRegPC    = 15,
-  kFPReg0   = 16,
-  kFPReg16  = 32,
-  kRegEnd   = 48,
-  kCCode    = kRegEnd,
-  kFPStatus,      // FP status word
-  // The following four bits are for memory disambiguation
-  kDalvikReg,     // 1 Dalvik Frame (can be fully disambiguated)
-  kLiteral,       // 2 Literal pool (can be fully disambiguated)
-  kHeapRef,       // 3 Somewhere on the heap (alias with any other heap)
-  kMustNotAlias,    // 4 Guaranteed to be non-alias (eg *(r6+x))
+enum ArmResourceEncodingPos {
+  kArmGPReg0   = 0,
+  kArmRegSP    = 13,
+  kArmRegLR    = 14,
+  kArmRegPC    = 15,
+  kArmFPReg0   = 16,
+  kArmFPReg16  = 32,
+  kArmRegEnd   = 48,
 };
 
-#define ENCODE_REG_LIST(N)      ((u8) N)
-#define ENCODE_REG_SP           (1ULL << kRegSP)
-#define ENCODE_REG_LR           (1ULL << kRegLR)
-#define ENCODE_REG_PC           (1ULL << kRegPC)
-#define ENCODE_CCODE            (1ULL << kCCode)
-#define ENCODE_FP_STATUS        (1ULL << kFPStatus)
-#define ENCODE_REG_FPCS_LIST(N) ((u8)N << kFPReg16)
-
-/* Abstract memory locations */
-#define ENCODE_DALVIK_REG       (1ULL << kDalvikReg)
-#define ENCODE_LITERAL          (1ULL << kLiteral)
-#define ENCODE_HEAP_REF         (1ULL << kHeapRef)
-#define ENCODE_MUST_NOT_ALIAS   (1ULL << kMustNotAlias)
-
-#define ENCODE_ALL              (~0ULL)
-#define ENCODE_MEM              (ENCODE_DALVIK_REG | ENCODE_LITERAL | \
-                 ENCODE_HEAP_REF | ENCODE_MUST_NOT_ALIAS)
-
-#define DECODE_ALIAS_INFO_REG(X)        (X & 0xffff)
-#define DECODE_ALIAS_INFO_WIDE(X)       ((X & 0x80000000) ? 1 : 0)
+#define ENCODE_ARM_REG_LIST(N)      ((u8) N)
+#define ENCODE_ARM_REG_SP           (1ULL << kArmRegSP)
+#define ENCODE_ARM_REG_LR           (1ULL << kArmRegLR)
+#define ENCODE_ARM_REG_PC           (1ULL << kArmRegPC)
+#define ENCODE_ARM_REG_FPCS_LIST(N) ((u8)N << kArmFPReg16)
 
 /*
  * Annotate special-purpose core registers:
@@ -606,82 +581,6 @@ enum ArmOpDmbOptions {
 };
 
 /* Bit flags describing the behavior of each native opcode */
-enum ArmOpFeatureFlags {
-  kIsBranch = 0,
-  kRegDef0,
-  kRegDef1,
-  kRegDefSP,
-  kRegDefLR,
-  kRegDefList0,
-  kRegDefList1,
-  kRegDefFPCSList0,
-  kRegDefFPCSList2,
-  kRegDefList2,
-  kRegUse0,
-  kRegUse1,
-  kRegUse2,
-  kRegUse3,
-  kRegUseSP,
-  kRegUsePC,
-  kRegUseList0,
-  kRegUseList1,
-  kRegUseFPCSList0,
-  kRegUseFPCSList2,
-  kNoOperand,
-  kIsUnaryOp,
-  kIsBinaryOp,
-  kIsTertiaryOp,
-  kIsQuadOp,
-  kIsIT,
-  kSetsCCodes,
-  kUsesCCodes,
-  kMemLoad,
-  kMemStore,
-  kPCRelFixup,
-};
-
-#define IS_LOAD         (1 << kMemLoad)
-#define IS_STORE        (1 << kMemStore)
-#define IS_BRANCH       (1 << kIsBranch)
-#define REG_DEF0        (1 << kRegDef0)
-#define REG_DEF1        (1 << kRegDef1)
-#define REG_DEF_SP      (1 << kRegDefSP)
-#define REG_DEF_LR      (1 << kRegDefLR)
-#define REG_DEF_LIST0   (1 << kRegDefList0)
-#define REG_DEF_LIST1   (1 << kRegDefList1)
-#define REG_DEF_FPCS_LIST0   (1 << kRegDefFPCSList0)
-#define REG_DEF_FPCS_LIST2   (1 << kRegDefFPCSList2)
-#define REG_USE0        (1 << kRegUse0)
-#define REG_USE1        (1 << kRegUse1)
-#define REG_USE2        (1 << kRegUse2)
-#define REG_USE3        (1 << kRegUse3)
-#define REG_USE_SP      (1 << kRegUseSP)
-#define REG_USE_PC      (1 << kRegUsePC)
-#define REG_USE_LIST0   (1 << kRegUseList0)
-#define REG_USE_LIST1   (1 << kRegUseList1)
-#define REG_USE_FPCS_LIST0   (1 << kRegUseFPCSList0)
-#define REG_USE_FPCS_LIST2   (1 << kRegUseFPCSList2)
-#define NO_OPERAND      (1 << kNoOperand)
-#define IS_UNARY_OP     (1 << kIsUnaryOp)
-#define IS_BINARY_OP    (1 << kIsBinaryOp)
-#define IS_TERTIARY_OP  (1 << kIsTertiaryOp)
-#define IS_QUAD_OP      (1 << kIsQuadOp)
-#define IS_QUIN_OP      0
-#define IS_IT           (1 << kIsIT)
-#define SETS_CCODES     (1 << kSetsCCodes)
-#define USES_CCODES     (1 << kUsesCCodes)
-#define NEEDS_FIXUP     (1 << kPCRelFixup)
-
-/* Common combo register usage patterns */
-#define REG_USE01       (REG_USE0 | REG_USE1)
-#define REG_USE012      (REG_USE01 | REG_USE2)
-#define REG_USE12       (REG_USE1 | REG_USE2)
-#define REG_DEF0_USE0   (REG_DEF0 | REG_USE0)
-#define REG_DEF0_USE1   (REG_DEF0 | REG_USE1)
-#define REG_DEF0_USE01  (REG_DEF0 | REG_USE01)
-#define REG_DEF0_USE12  (REG_DEF0 | REG_USE12)
-#define REG_DEF01_USE2  (REG_DEF0 | REG_DEF1 | REG_USE2)
-
 /* Instruction assembly fieldLoc kind */
 enum ArmEncodingKind {
   kFmtUnused,
@@ -710,7 +609,7 @@ struct ArmEncodingMap {
     int start; /* start for kFmtBitBlt, 4-bit slice end for FP regs */
   } fieldLoc[4];
   ArmOpcode opcode;
-  int flags;
+  uint64_t flags;
   const char* name;
   const char* fmt;
   int size;   /* Size in bytes */