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author buzbee <buzbee@google.com> 2012-06-06 16:45:18 -0700
committer buzbee <buzbee@google.com> 2012-06-06 16:45:18 -0700
commit408ad16bf7c460bf34ca55ff6351b79841a6fcd5 (patch)
tree7336813d0fc92aa3ddd9b372cb1d260dd2386b9f /src/compiler/codegen/arm/Codegen.h
parent95b2619ca83752eb041020276e57af01052d0f94 (diff)
Restructure to reduce MIR references
This CL eliminates most of the MIR references in the lower-level code generator. This allows a higher level of code sharing with the MIR->LIR and GreenlandIR->LIR lowering passes. The invoke, launchpads and new array support will need some more extensive refactoring (future CL). Change-Id: I75f249268c8ac18da1dd9180ff855d5176d6c4fe
Diffstat (limited to 'src/compiler/codegen/arm/Codegen.h')
-rw-r--r--src/compiler/codegen/arm/Codegen.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/src/compiler/codegen/arm/Codegen.h b/src/compiler/codegen/arm/Codegen.h
index 10f5e384ad..22f6157228 100644
--- a/src/compiler/codegen/arm/Codegen.h
+++ b/src/compiler/codegen/arm/Codegen.h
@@ -31,19 +31,20 @@ LIR *opRegImm(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int value);
LIR *opRegReg(CompilationUnit* cUnit, OpKind op, int rDestSrc1, int rSrc2);
LIR* opCmpImmBranch(CompilationUnit* cUnit, ConditionCode cond, int reg,
int checkValue, LIR* target);
-bool genNegLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest,
+bool genNegLong(CompilationUnit* cUnit, RegLocation rlDest,
RegLocation rlSrc);
/* Forward declaraton the portable versions due to circular dependency */
-bool genArithOpFloatPortable(CompilationUnit* cUnit, MIR* mir,
+bool genArithOpFloatPortable(CompilationUnit* cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-bool genArithOpDoublePortable(CompilationUnit* cUnit, MIR* mir,
+bool genArithOpDoublePortable(CompilationUnit* cUnit, Instruction::Code opcode,
RegLocation rlDest, RegLocation rlSrc1,
RegLocation rlSrc2);
-bool genConversionPortable(CompilationUnit* cUnit, MIR* mir);
+bool genConversionPortable(CompilationUnit* cUnit, Instruction::Code opcode,
+ RegLocation rlDest, RegLocation rlSrc);
ArmConditionCode oatArmConditionEncoding(ConditionCode code);