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author buzbee <buzbee@google.com> 2011-10-02 13:08:29 -0700
committer buzbee <buzbee@google.com> 2011-10-02 13:21:01 -0700
commitbbaf894dded77603bd457758ba2b4636122fb8b7 (patch)
treeac8d0450f23dd6cde9647febef8de514c5a4b8ae /src/compiler/codegen/arm/ArmLIR.h
parentfc22c89072e310767f8e39776195a219df851ea0 (diff)
Optimization fixes
Two primary fixes. First, the save/restore mechanism for FP callee saves was broken if there were any holes in the save mask (the Arm ld/store multiple instructions for floating point use a start + count mechanism, rather than the bit-mask mechanism used for core registers). The second fix corrects a problem introduced by the recent enhancements to loading floating point literals. The load->copy optimization mechanism for literal loads used the value of the loaded literal to identify redundant loads. However, it used only the first 32 bits of the literal - which worked fine previously because 64-bit literal loads were treated as a pair of 32-bit loads. The fix was to use the label of the literal rather than the value in the aliasInfo - which works for all sizes. Change-Id: Ic4779adf73b2c7d80059a988b0ecdef39921a81f
Diffstat (limited to 'src/compiler/codegen/arm/ArmLIR.h')
-rw-r--r--src/compiler/codegen/arm/ArmLIR.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/compiler/codegen/arm/ArmLIR.h b/src/compiler/codegen/arm/ArmLIR.h
index 3b2e986acb..99b22e7741 100644
--- a/src/compiler/codegen/arm/ArmLIR.h
+++ b/src/compiler/codegen/arm/ArmLIR.h
@@ -99,6 +99,8 @@
#define FP_REG_OFFSET 32
/* Offset to distinguish DP FP regs */
#define FP_DOUBLE 64
+/* First FP callee save */
+#define FP_CALLEE_SAVE_BASE 16
/* Reg types */
#define REGTYPE(x) (x & (FP_REG_OFFSET | FP_DOUBLE))
#define FPREG(x) ((x & FP_REG_OFFSET) == FP_REG_OFFSET)