diff options
| author | 2012-03-26 16:35:06 -0700 | |
|---|---|---|
| committer | 2012-03-26 17:11:59 -0700 | |
| commit | b25c3f6a86dc634ce44fb2849385b49465caa84d (patch) | |
| tree | f359c72d821d913f78b977d8dde0fc7023afb511 /src/compiler/codegen/GenCommon.cc | |
| parent | fc9e6fabed89d948fa8c0e9d673e430076712c60 (diff) | |
Fix cpplint's whitespace complaints.
Change-Id: I11fd2db2badf7bd98e7866ca2155d8ef1e112408
Diffstat (limited to 'src/compiler/codegen/GenCommon.cc')
| -rw-r--r-- | src/compiler/codegen/GenCommon.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/compiler/codegen/GenCommon.cc b/src/compiler/codegen/GenCommon.cc index 0ef1641858..0b0d100fc4 100644 --- a/src/compiler/codegen/GenCommon.cc +++ b/src/compiler/codegen/GenCommon.cc @@ -367,7 +367,7 @@ void genCompareAndBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir, rlSrc1 = loadValue(cUnit, rlSrc1, kCoreReg); rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg); Instruction::Code opcode = mir->dalvikInsn.opcode; - switch(opcode) { + switch (opcode) { case Instruction::IF_EQ: cond = kCondEq; break; @@ -406,7 +406,7 @@ void genCompareZeroAndBranch(CompilationUnit* cUnit, BasicBlock* bb, MIR* mir, ConditionCode cond; rlSrc = loadValue(cUnit, rlSrc, kCoreReg); Instruction::Code opcode = mir->dalvikInsn.opcode; - switch(opcode) { + switch (opcode) { case Instruction::IF_EQZ: cond = kCondEq; break; @@ -458,7 +458,7 @@ void genIntNarrowing(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, rlSrc = loadValue(cUnit, rlSrc, kCoreReg); RegLocation rlResult = oatEvalLoc(cUnit, rlDest, kCoreReg, true); OpKind op = kOpInvalid; - switch(mir->dalvikInsn.opcode) { + switch (mir->dalvikInsn.opcode) { case Instruction::INT_TO_BYTE: op = kOp2Byte; break; @@ -887,7 +887,7 @@ void handleThrowLaunchpads(CompilationUnit *cUnit) int funcOffset = 0; int v1 = lab->operands[2]; int v2 = lab->operands[3]; - switch(lab->operands[0]) { + switch (lab->operands[0]) { case kThrowNullPointer: funcOffset = OFFSETOF_MEMBER(Thread, pThrowNullPointerFromCode); break; @@ -1722,7 +1722,7 @@ bool genShiftOpLong(CompilationUnit* cUnit, MIR* mir, RegLocation rlDest, { int funcOffset; - switch( mir->dalvikInsn.opcode) { + switch (mir->dalvikInsn.opcode) { case Instruction::SHL_LONG: case Instruction::SHL_LONG_2ADDR: funcOffset = OFFSETOF_MEMBER(Thread, pShlLong); |