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| author | 2012-03-04 14:57:06 -0800 | |
|---|---|---|
| committer | 2012-03-04 15:00:36 -0800 | |
| commit | a2ebdd74eb2f36e6efa7a482bc11c7b93d97c2c3 (patch) | |
| tree | 2d63c98a1f729f1e17969bfbc4b7dc1da48f4567 /src/compiler/codegen/CompilerCodegen.h | |
| parent | 11f9d2130e938511efceb6d2a4793cee7dfdde35 (diff) | |
Complete MIPS code generation support
With this CL code generation for MIPS is complete (though untested on
actual hardware). Core and the boot classpath compile without issue.
The primary thrust here was to support expanding of short branch
sequences to long form during assembly if the displacement field overflowed.
That led to a general cleanup of creation on LIR nodes outside of the
normal flow.
Also introduced is a README to describe the state of MIPS support, as well
as memory barrier handling.
Change-Id: I251a2ef8d74bc7183406dce9493464be24a9d7f7
Diffstat (limited to 'src/compiler/codegen/CompilerCodegen.h')
| -rw-r--r-- | src/compiler/codegen/CompilerCodegen.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/compiler/codegen/CompilerCodegen.h b/src/compiler/codegen/CompilerCodegen.h index 26dad8240c..fdcb55557a 100644 --- a/src/compiler/codegen/CompilerCodegen.h +++ b/src/compiler/codegen/CompilerCodegen.h @@ -21,6 +21,9 @@ namespace art { +LIR* rawLIR(CompilationUnit* cUnit, int dalvikOffset, int opcode, int op0 = 0, + int op1 = 0, int op2 = 0, int op3 = 0, LIR* target = NULL); + /* Lower middle-level IR to low-level IR for the whole method */ void oatMethodMIR2LIR(CompilationUnit* cUnit); |