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| author | 2023-12-26 14:18:07 -0800 | |
|---|---|---|
| committer | 2023-12-28 00:09:24 +0000 | |
| commit | 41a99b66d97564355a1e9c89d233c7e5480be40e (patch) | |
| tree | 6de94cf544bcc21fd404681b31379eda61c9c1ef /libnativeloader/native_loader_api_test.c | |
| parent | f45b3e396d1a1b4a19a6253bf6ae9b8a59ebeec5 (diff) | |
riscv64: refactor vreg macros to use py bools
This patch refactors the GET/SET_VREG macros
to use python's is_width=True/False and width="64"
to improve readability across Nterp's RISC-V asm.
The older style used "0" and "1" strings to
represent booleans in asm control flow directives.
(1) setup
lunch aosp_riscv64-trunk-userdebug
export ART_TEST_SSH_USER=ubuntu
export ART_TEST_SSH_HOST=localhost
export ART_TEST_SSH_PORT=10001
export ART_TEST_ON_VM=true
. art/tools/buildbot-utils.sh
art/tools/buildbot-build.sh --target
# Create, boot and configure the VM.
art/tools/buildbot-vm.sh create
art/tools/buildbot-vm.sh boot
art/tools/buildbot-vm.sh setup-ssh # password: 'ubuntu'
art/tools/buildbot-cleanup-device.sh
art/tools/buildbot-setup-device.sh
art/tools/buildbot-sync.sh
(2) test
art/test.py --target -r --no-prebuild --ndebug --64 -j 12 --cdex-none --interpreter
Test: Run these opcodes against all interpreter
tests on a Linux RISC-V VM.
Test: Cuttlefish boot
Bug: 283082047
Change-Id: If156b423147a452fcb4f83bd3d6c59e13c36dd52
Diffstat (limited to 'libnativeloader/native_loader_api_test.c')
0 files changed, 0 insertions, 0 deletions