ARM64: Support SVE VL other than 128-bit.

Arm SVE register size is not fixed and can be a
multiple of 128 bits. To support that the patch
removes explicit assumptions on the SIMD register
size to be 128 bit from the vectorizer and code
generators and enables configurable SVE vector
length autovectorization, e.g. extends SIMD register
save/restore routines.

Test: art SIMD tests on VIXL simulator.
Test: art tests on FVP (steps in test/README.arm_fvp.md)
      with FVP arg:
      -C SVE.ScalableVectorExtension.veclen=[2,4]
      (SVE vector [128,256] bits wide)

Change-Id: Icb46e7eb17f21d3bd38b16dd50f735c29b316427

1 files changed, 3 insertions, 0 deletions

diff --git a/libartbase/arch/instruction_set.h b/libartbase/arch/instruction_set.h
index 2fd8773d0e..dbaacda946 100644
--- a/libartbase/arch/instruction_set.h
+++ b/libartbase/arch/instruction_set.h
@@ -61,6 +61,9 @@ static constexpr size_t kArmAlignment = 8;
 // ARM64 instruction alignment. This is the recommended alignment for maximum performance.
 static constexpr size_t kArm64Alignment = 16;
 
+// ARM64 default SVE vector length.
+static constexpr size_t kArm64DefaultSVEVectorLength = 256;
+
 // X86 instruction alignment. This is the recommended alignment for maximum performance.
 static constexpr size_t kX86Alignment = 16;