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author | 2015-04-27 17:52:57 +0600 | |
---|---|---|
committer | 2015-04-29 12:17:35 +0600 | |
commit | e0705f51fdc71e9670a29f8c3a47168f50724b35 (patch) | |
tree | 4a9a2d808441843bed332b0bdad3aec0a7aa4cee /disassembler/disassembler_x86.cc | |
parent | 64db01714f91bf255a79c0a88813641c240c9857 (diff) |
Fix for incorrect encode and parse of PEXTRW instruction
The instruction PEXTRW encoded by sequence 66 0F 3A 15
was incorrectly encoded in compiler table and incorrectly
parsed by disassembler.
Change-Id: Ib4d4db923cb15a76e74f13f6b5514cb0d1cbe164
Signed-off-by: nikolay serdjuk <nikolay.y.serdjuk@intel.com>
Diffstat (limited to 'disassembler/disassembler_x86.cc')
-rw-r--r-- | disassembler/disassembler_x86.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index ba0c0bdebd..2ead4a2af5 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -587,6 +587,14 @@ DISASSEMBLER_ENTRY(cmp, src_reg_file = SSE; immediate_bytes = 1; break; + case 0x15: + opcode1 = "pextrw"; + prefix[2] = 0; + has_modrm = true; + store = true; + src_reg_file = SSE; + immediate_bytes = 1; + break; case 0x16: opcode1 = "pextrd"; prefix[2] = 0; |