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| author | 2014-07-25 11:49:42 +0800 | |
|---|---|---|
| committer | 2014-07-29 00:38:14 -0700 | |
| commit | b551fdcda9eb128c80de37c4fb978968bec6d4b3 (patch) | |
| tree | 62942f412f2275e2e9188f71c370cd95ec91e17f /disassembler/disassembler_x86.cc | |
| parent | 2815f1242c6c3ea1fc2df7bb5e4bd1924f4e75f7 (diff) | |
AArch64: Clean up CalleeSaveMethod frame and the use of temp registers.
CalleeSaveMethod frame size changes :
SaveAll : 368 -> 176
RefOnly : 176 -> 96
RefsAndArgs : 304 -> 224
JNI register spill size changes :
160 -> 88
In the transition assembly, use registers following the rules:
1. x0-x7 as temp/argument registers.
2. IP0, IP1 as scratch registers.
3. After correct type of callee-save-frame has been setup, all registers
are scratch-able(probably except xSELF and xSUSPEND).
4. When restore callee-save-frame, IP0 and IP1 should be untouched.
5. From C to managed code, we assume all callee save register in AAPCS
will be restored by managed code except x19(SUSPEND).
In quick compiler:
1. Use IP0, IP1 as scratch register.
2. Use IP1 as hidden argument register(IP0 will be scratched by
trampoline.)
Change-Id: I05ed9d418b01b9e87218a7608536f57e7a286e4c
Diffstat (limited to 'disassembler/disassembler_x86.cc')
0 files changed, 0 insertions, 0 deletions