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| author | 2015-08-12 21:16:41 -0400 | |
|---|---|---|
| committer | 2015-08-14 12:58:40 -0400 | |
| commit | 8ae3ffb29489a127f2a6242c33845dac8d50e508 (patch) | |
| tree | cb5cc72e4a699a8ef6b044d530539c13b02604b7 /disassembler/disassembler_x86.cc | |
| parent | f67ab129d868b8355a8403a9627f96ac1e41a796 (diff) | |
Add 'bsr' instruction to x86 and x86_64
Add support for 'bsr' instruction. Add tests.
Change-Id: I1cd8b30d7f3f5ee7fbeef8124cc6a31bf8ce59d5
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'disassembler/disassembler_x86.cc')
| -rw-r--r-- | disassembler/disassembler_x86.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index 9bee1040ba..d4574f4f0a 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -928,6 +928,11 @@ DISASSEMBLER_ENTRY(cmp, has_modrm = true; load = true; break; + case 0xBD: + opcode1 = "bsr"; + has_modrm = true; + load = true; + break; case 0xBE: opcode1 = "movsxb"; has_modrm = true; |