diff options
| author | 2018-08-28 16:27:48 +0000 | |
|---|---|---|
| committer | 2018-08-28 16:27:48 +0000 | |
| commit | 6bfbdc7fe3751fb6af6ff65493ab9e0f74ed5ca8 (patch) | |
| tree | a2d391945f5b78e840155bbb420768d9dd402a5d /disassembler/disassembler_arm64.h | |
| parent | aa317ffafe685b96993ffb2617c530f8b950480f (diff) | |
| parent | 625ca4759941299e8a9cc876c985558c4d76bdc0 (diff) | |
Merge changes If4de1e1f,I11493096,I256c7758
* changes:
Remove 'virtual' and 'override' qualifiers on final methods.
Remove superfluous 'virtual' specifiers in ART.
Use 'final' and 'override' specifiers directly in ART.
Diffstat (limited to 'disassembler/disassembler_arm64.h')
| -rw-r--r-- | disassembler/disassembler_arm64.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h index 19e4dfb486..89beaa927b 100644 --- a/disassembler/disassembler_arm64.h +++ b/disassembler/disassembler_arm64.h @@ -29,7 +29,7 @@ namespace art { namespace arm64 { -class CustomDisassembler FINAL : public vixl::aarch64::Disassembler { +class CustomDisassembler final : public vixl::aarch64::Disassembler { public: explicit CustomDisassembler(DisassemblerOptions* options) : vixl::aarch64::Disassembler(), @@ -45,13 +45,13 @@ class CustomDisassembler FINAL : public vixl::aarch64::Disassembler { // Use register aliases in the disassembly. void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr, - const vixl::aarch64::CPURegister& reg) OVERRIDE; + const vixl::aarch64::CPURegister& reg) override; // Improve the disassembly of literal load instructions. - void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) OVERRIDE; + void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) override; // Improve the disassembly of thread offset. - void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) OVERRIDE; + void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) override; private: // Indicate if the disassembler should read data loaded from literal pools. @@ -69,15 +69,15 @@ class CustomDisassembler FINAL : public vixl::aarch64::Disassembler { DisassemblerOptions* options_; }; -class DisassemblerArm64 FINAL : public Disassembler { +class DisassemblerArm64 final : public Disassembler { public: explicit DisassemblerArm64(DisassemblerOptions* options) : Disassembler(options), disasm(options) { decoder.AppendVisitor(&disasm); } - size_t Dump(std::ostream& os, const uint8_t* begin) OVERRIDE; - void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) OVERRIDE; + size_t Dump(std::ostream& os, const uint8_t* begin) override; + void Dump(std::ostream& os, const uint8_t* begin, const uint8_t* end) override; private: vixl::aarch64::Decoder decoder; |