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| author | 2024-09-19 13:00:26 +0100 | |
|---|---|---|
| committer | 2024-09-19 13:47:52 +0000 | |
| commit | 44e2172427c83cb4974cd01c3fad61c6293fbb16 (patch) | |
| tree | 92d141cc5d0cfe35898cccee0958c9e01f8eff11 /disassembler/disassembler_arm64.h | |
| parent | 526a334716ee8a2967d83e0cac95cbc99cd7918f (diff) | |
Print the full relative address in Arm64
By printing with trailing zeroes (e.g. 0x00004074 instead of
0x4074) this brings Arm64 on par with other architectures.
Bug: 364443075
Fixes: 364443075
Test: art/test/testrunner/testrunner.py --target --64 --optimizing
Change-Id: Iade36a91316ca4310d71846ff2953ff7419877ee
Diffstat (limited to 'disassembler/disassembler_arm64.h')
| -rw-r--r-- | disassembler/disassembler_arm64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/disassembler/disassembler_arm64.h b/disassembler/disassembler_arm64.h index 7d49a03f58..d1b509127c 100644 --- a/disassembler/disassembler_arm64.h +++ b/disassembler/disassembler_arm64.h @@ -48,6 +48,10 @@ class CustomDisassembler final : public vixl::aarch64::Disassembler { void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr, const vixl::aarch64::CPURegister& reg) override; + // Overriding to print the address with trailing zeroes e.g. 0x00004074 instead of 0x4074. + void AppendCodeRelativeAddressToOutput(const vixl::aarch64::Instruction* instr, + const void* addr) override; + // Intercepts the instruction flow captured by the parent method, // to specially instrument for particular instruction types. void Visit(vixl::aarch64::Metadata* metadata, const vixl::aarch64::Instruction* instr) override; |