diff options
| author | 2014-04-03 15:09:37 -0700 | |
|---|---|---|
| committer | 2014-04-03 15:44:01 -0700 | |
| commit | cbd18b7f4da7677ca48c48c23ed9a7de3a8b0354 (patch) | |
| tree | 8a894c60430ff2061964f5a9d33d248ccce88493 /compiler | |
| parent | 0537c5ea92a4fb60a04024cc2b7247f08a3d9096 (diff) | |
Fix LoadValueWide to not call MarkLive for high reg that is equal to low reg
For x86 double FP registers, LoadValueWide should not call MarkLive for
high reg that is equal to low reg.
Change-Id: Ie6a59307c9ff93303bd489c15529432cfdeceaa4
Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/dex/quick/gen_loadstore.cc | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/compiler/dex/quick/gen_loadstore.cc b/compiler/dex/quick/gen_loadstore.cc index 897d86d09a..208eadde12 100644 --- a/compiler/dex/quick/gen_loadstore.cc +++ b/compiler/dex/quick/gen_loadstore.cc @@ -211,7 +211,12 @@ RegLocation Mir2Lir::LoadValueWide(RegLocation rl_src, RegisterClass op_kind) { LoadValueDirectWide(rl_src, rl_src.reg); rl_src.location = kLocPhysReg; MarkLive(rl_src.reg.GetLow(), rl_src.s_reg_low); - MarkLive(rl_src.reg.GetHigh(), GetSRegHi(rl_src.s_reg_low)); + if (rl_src.reg.GetLowReg() != rl_src.reg.GetHighReg()) { + MarkLive(rl_src.reg.GetHigh(), GetSRegHi(rl_src.s_reg_low)); + } else { + // This must be an x86 vector register value. + DCHECK(IsFpReg(rl_src.reg) && (cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64)); + } } return rl_src; } |