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author Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> 2017-08-18 12:14:13 +0000
committer android-build-merger <android-build-merger@google.com> 2017-08-18 12:14:13 +0000
commita19140e9336d917589a25d347e596e3f828dafbe (patch)
tree46243f3ea24de4be25c5aa24649b8a015c041b7a /compiler/utils
parent9af5b85b6a5d4f46709c05c2615046749922aadb (diff)
parent5011149cbb1dddf7161ef294b8ed265862ae6d91 (diff)
Merge "MIPS64: Implement HSelect"
am: 5011149cbb Change-Id: I2d4cb5d05f86abdb933941e4530f98062a01bd3b
Diffstat (limited to 'compiler/utils')
-rw-r--r--compiler/utils/mips64/assembler_mips64.cc16
-rw-r--r--compiler/utils/mips64/assembler_mips64.h4
-rw-r--r--compiler/utils/mips64/assembler_mips64_test.cc20
3 files changed, 40 insertions, 0 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.cc b/compiler/utils/mips64/assembler_mips64.cc
index 3aa09fbdb6..183b5e507b 100644
--- a/compiler/utils/mips64/assembler_mips64.cc
+++ b/compiler/utils/mips64/assembler_mips64.cc
@@ -1079,6 +1079,22 @@ void Mips64Assembler::SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
EmitFR(0x11, 0x11, ft, fs, fd, 0x10);
}
+void Mips64Assembler::SeleqzS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+ EmitFR(0x11, 0x10, ft, fs, fd, 0x14);
+}
+
+void Mips64Assembler::SeleqzD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+ EmitFR(0x11, 0x11, ft, fs, fd, 0x14);
+}
+
+void Mips64Assembler::SelnezS(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+ EmitFR(0x11, 0x10, ft, fs, fd, 0x17);
+}
+
+void Mips64Assembler::SelnezD(FpuRegister fd, FpuRegister fs, FpuRegister ft) {
+ EmitFR(0x11, 0x11, ft, fs, fd, 0x17);
+}
+
void Mips64Assembler::RintS(FpuRegister fd, FpuRegister fs) {
EmitFR(0x11, 0x10, static_cast<FpuRegister>(0), fs, fd, 0x1a);
}
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h
index 023bcd681d..4c8fb68d62 100644
--- a/compiler/utils/mips64/assembler_mips64.h
+++ b/compiler/utils/mips64/assembler_mips64.h
@@ -606,6 +606,10 @@ class Mips64Assembler FINAL : public Assembler, public JNIMacroAssembler<Pointer
void FloorWD(FpuRegister fd, FpuRegister fs);
void SelS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
void SelD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+ void SeleqzS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+ void SeleqzD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+ void SelnezS(FpuRegister fd, FpuRegister fs, FpuRegister ft);
+ void SelnezD(FpuRegister fd, FpuRegister fs, FpuRegister ft);
void RintS(FpuRegister fd, FpuRegister fs);
void RintD(FpuRegister fd, FpuRegister fs);
void ClassS(FpuRegister fd, FpuRegister fs);
diff --git a/compiler/utils/mips64/assembler_mips64_test.cc b/compiler/utils/mips64/assembler_mips64_test.cc
index 1541780e2f..fc0bd368ea 100644
--- a/compiler/utils/mips64/assembler_mips64_test.cc
+++ b/compiler/utils/mips64/assembler_mips64_test.cc
@@ -525,6 +525,26 @@ TEST_F(AssemblerMIPS64Test, SelD) {
DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelD, "sel.d ${reg1}, ${reg2}, ${reg3}"), "sel.d");
}
+TEST_F(AssemblerMIPS64Test, SeleqzS) {
+ DriverStr(RepeatFFF(&mips64::Mips64Assembler::SeleqzS, "seleqz.s ${reg1}, ${reg2}, ${reg3}"),
+ "seleqz.s");
+}
+
+TEST_F(AssemblerMIPS64Test, SeleqzD) {
+ DriverStr(RepeatFFF(&mips64::Mips64Assembler::SeleqzD, "seleqz.d ${reg1}, ${reg2}, ${reg3}"),
+ "seleqz.d");
+}
+
+TEST_F(AssemblerMIPS64Test, SelnezS) {
+ DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelnezS, "selnez.s ${reg1}, ${reg2}, ${reg3}"),
+ "selnez.s");
+}
+
+TEST_F(AssemblerMIPS64Test, SelnezD) {
+ DriverStr(RepeatFFF(&mips64::Mips64Assembler::SelnezD, "selnez.d ${reg1}, ${reg2}, ${reg3}"),
+ "selnez.d");
+}
+
TEST_F(AssemblerMIPS64Test, RintS) {
DriverStr(RepeatFF(&mips64::Mips64Assembler::RintS, "rint.s ${reg1}, ${reg2}"), "rint.s");
}