diff options
| author | 2014-12-01 12:28:51 +0000 | |
|---|---|---|
| committer | 2014-12-01 12:28:51 +0000 | |
| commit | 89b53873b29e9e93fa6ba49c9685b84c60c76a4c (patch) | |
| tree | f5c860c8f84d3ae77972e94eddfdefadd5d58dc1 /compiler/utils | |
| parent | 672db0289de1dec9513da14153f315fecb78649e (diff) | |
| parent | 32f5b4d2c8c9b52e9522941c159577b21752d0fa (diff) | |
Merge "Vixl: Update the VIXL interface to VIXL 1.7 and enable VIXL debug."
Diffstat (limited to 'compiler/utils')
| -rw-r--r-- | compiler/utils/arm64/assembler_arm64.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/compiler/utils/arm64/assembler_arm64.cc b/compiler/utils/arm64/assembler_arm64.cc index 390f2ea449..21014c8bba 100644 --- a/compiler/utils/arm64/assembler_arm64.cc +++ b/compiler/utils/arm64/assembler_arm64.cc @@ -329,12 +329,12 @@ void Arm64Assembler::Move(ManagedRegister m_dst, ManagedRegister m_src, size_t s if (dst.IsXRegister()) { if (size == 4) { CHECK(src.IsWRegister()); - ___ Mov(reg_x(dst.AsXRegister()), reg_w(src.AsWRegister())); + ___ Mov(reg_w(dst.AsOverlappingWRegister()), reg_w(src.AsWRegister())); } else { if (src.IsXRegister()) { ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsXRegister())); } else { - ___ Mov(reg_x(dst.AsXRegister()), reg_w(src.AsWRegister())); + ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsOverlappingXRegister())); } } } else if (dst.IsWRegister()) { @@ -484,9 +484,9 @@ void Arm64Assembler::SignExtend(ManagedRegister mreg, size_t size) { CHECK(size == 1 || size == 2) << size; CHECK(reg.IsWRegister()) << reg; if (size == 1) { - ___ sxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); + ___ Sxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); } else { - ___ sxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); + ___ Sxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); } } @@ -495,9 +495,9 @@ void Arm64Assembler::ZeroExtend(ManagedRegister mreg, size_t size) { CHECK(size == 1 || size == 2) << size; CHECK(reg.IsWRegister()) << reg; if (size == 1) { - ___ uxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); + ___ Uxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); } else { - ___ uxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); + ___ Uxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); } } |