diff options
| author | 2024-03-13 13:52:51 +0300 | |
|---|---|---|
| committer | 2024-03-21 16:39:20 +0000 | |
| commit | 2f33fea690c2becb00ffe12fa3ebc0ada52c678c (patch) | |
| tree | 1f54b3d8b0f58a68d2309510dbb00079279a855d /compiler/utils | |
| parent | 700002ee909f6575b2c8a23725493da523ae5a5f (diff) | |
riscv64: Support auto-compression for ebreak/unimp
Emit automatically corresponding compressed instruction
Add tests
Test: m test-art-host-gtest
Test: run-gtests.sh
Test: testrunner.py --target --optimizing
Bug: 328561342
Change-Id: Iea334f94f0f0b30d05442df10b5bd0efae19857a
Diffstat (limited to 'compiler/utils')
| -rw-r--r-- | compiler/utils/riscv64/assembler_riscv64.cc | 16 | ||||
| -rw-r--r-- | compiler/utils/riscv64/assembler_riscv64_test.cc | 14 |
2 files changed, 25 insertions, 5 deletions
diff --git a/compiler/utils/riscv64/assembler_riscv64.cc b/compiler/utils/riscv64/assembler_riscv64.cc index 82536999b4..db9aac6793 100644 --- a/compiler/utils/riscv64/assembler_riscv64.cc +++ b/compiler/utils/riscv64/assembler_riscv64.cc @@ -559,7 +559,14 @@ void Riscv64Assembler::Sraw(XRegister rd, XRegister rs1, XRegister rs2) { void Riscv64Assembler::Ecall() { EmitI(0x0, 0x0, 0x0, 0x0, 0x73); } -void Riscv64Assembler::Ebreak() { EmitI(0x1, 0x0, 0x0, 0x0, 0x73); } +void Riscv64Assembler::Ebreak() { + if (IsExtensionEnabled(Riscv64Extension::kZca)) { + CEbreak(); + return; + } + + EmitI(0x1, 0x0, 0x0, 0x0, 0x73); +} // Fence instruction (RV32I): opcode = 0xf, funct3 = 0 @@ -6489,8 +6496,11 @@ void Riscv64Assembler::FLoadd(FRegister rd, Literal* literal) { } void Riscv64Assembler::Unimp() { - // TODO(riscv64): use 16-bit zero C.UNIMP once we support compression - Emit32(0xC0001073); + if (IsExtensionEnabled(Riscv64Extension::kZca)) { + CUnimp(); + } else { + Emit32(0xC0001073); + } } /////////////////////////////// RV64 MACRO Instructions END /////////////////////////////// diff --git a/compiler/utils/riscv64/assembler_riscv64_test.cc b/compiler/utils/riscv64/assembler_riscv64_test.cc index 95bc6560b9..120dfc4f35 100644 --- a/compiler/utils/riscv64/assembler_riscv64_test.cc +++ b/compiler/utils/riscv64/assembler_riscv64_test.cc @@ -2616,11 +2616,16 @@ TEST_F(AssemblerRISCV64Test, Ecall) { } TEST_F(AssemblerRISCV64Test, Ebreak) { - ScopedCSuppression scs(this); __ Ebreak(); DriverStr("ebreak\n", "Ebreak"); } +TEST_F(AssemblerRISCV64Test, Ebreak_WithoutC) { + ScopedCSuppression scs(this); + __ Ebreak(); + DriverStr("ebreak\n", "Ebreak_WithoutC"); +} + TEST_F(AssemblerRISCV64Test, Fence) { auto get_fence_type_string = [](uint32_t fence_type) { CHECK_LE(fence_type, 0xfu); @@ -8789,11 +8794,16 @@ TEST_F(AssemblerRISCV64Test, FStored) { } TEST_F(AssemblerRISCV64Test, Unimp) { - ScopedCSuppression scs(this); __ Unimp(); DriverStr("unimp\n", "Unimp"); } +TEST_F(AssemblerRISCV64Test, Unimp_WithoutC) { + ScopedCSuppression scs(this); + __ Unimp(); + DriverStr("unimp\n", "Unimp_WithoutC"); +} + TEST_F(AssemblerRISCV64Test, LoadLabelAddress) { std::string expected; constexpr size_t kNumLoadsForward = 4 * KB; |