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| author | 2015-10-19 15:45:55 +0000 | |
|---|---|---|
| committer | 2015-10-19 15:45:55 +0000 | |
| commit | aeae32f846a04c9472fd3bdbbee92c0e1ace9b6c (patch) | |
| tree | 78a49ebd0052617c3bd7d0bc17ec0b9d3fd206a0 /compiler/utils/mips64/assembler_mips64.h | |
| parent | a5903e622c0c11c1513a62e128a26d3cefd16c6f (diff) | |
| parent | 9aebff2f19b605bff864308be51b604b7191163e (diff) | |
Merge "MIPS64: Add intrinsic support for bit rotation"
Diffstat (limited to 'compiler/utils/mips64/assembler_mips64.h')
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h index ac06521ec0..33f22d2c2d 100644 --- a/compiler/utils/mips64/assembler_mips64.h +++ b/compiler/utils/mips64/assembler_mips64.h @@ -123,15 +123,19 @@ class Mips64Assembler FINAL : public Assembler { void Sra(GpuRegister rd, GpuRegister rt, int shamt); void Sllv(GpuRegister rd, GpuRegister rt, GpuRegister rs); void Srlv(GpuRegister rd, GpuRegister rt, GpuRegister rs); + void Rotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs); void Srav(GpuRegister rd, GpuRegister rt, GpuRegister rs); void Dsll(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 + void Drotr(GpuRegister rd, GpuRegister rt, int shamt); void Dsra(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 void Dsll32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 void Dsrl32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 + void Drotr32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 void Dsra32(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64 void Dsllv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 void Dsrlv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 + void Drotrv(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 void Dsrav(GpuRegister rd, GpuRegister rt, GpuRegister rs); // MIPS64 void Lb(GpuRegister rt, GpuRegister rs, uint16_t imm16); |