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| author | 2017-05-12 23:46:13 +0000 | |
|---|---|---|
| committer | 2017-05-12 23:46:15 +0000 | |
| commit | a152c4b160f5f296e55c545d37c29d17b4db2212 (patch) | |
| tree | 5496a518583c525f04b5e490f0d7b82630ddb4ff /compiler/utils/mips64/assembler_mips64.h | |
| parent | 54db2e2ff3a5520e75480f5ce2cf25b8dd37588c (diff) | |
| parent | 3837011236058617292bee831708449e5100c08c (diff) | |
Merge "MIPS64: Add ilvr.df MSA instructions"
Diffstat (limited to 'compiler/utils/mips64/assembler_mips64.h')
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h index 559d6720a5..c92cf4c048 100644 --- a/compiler/utils/mips64/assembler_mips64.h +++ b/compiler/utils/mips64/assembler_mips64.h @@ -769,6 +769,11 @@ class Mips64Assembler FINAL : public Assembler, public JNIMacroAssembler<Pointer void StW(VectorRegister wd, GpuRegister rs, int offset); void StD(VectorRegister wd, GpuRegister rs, int offset); + void IlvrB(VectorRegister wd, VectorRegister ws, VectorRegister wt); + void IlvrH(VectorRegister wd, VectorRegister ws, VectorRegister wt); + void IlvrW(VectorRegister wd, VectorRegister ws, VectorRegister wt); + void IlvrD(VectorRegister wd, VectorRegister ws, VectorRegister wt); + // Higher level composite instructions. int InstrCountForLoadReplicatedConst32(int64_t); void LoadConst32(GpuRegister rd, int32_t value); |