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| author | 2015-09-09 13:15:38 -0700 | |
|---|---|---|
| committer | 2015-09-17 14:41:52 -0700 | |
| commit | 85b62f23fc6dfffe2ddd3ddfa74611666c9ff41d (patch) | |
| tree | c916b01b1608558a7d8c9d100274c4c6b6706386 /compiler/utils/mips64/assembler_mips64.h | |
| parent | 6766eae2d91e894b4ceab9f29cc983900e7bc0c7 (diff) | |
ART: Refactor intrinsics slow-paths
Refactor slow paths so that there is a default implementation for
common cases (only arm64 with vixl is special). Write a generic
intrinsic slow-path that can be reused for the specific architectures.
Move helper functions into CodeGenerator so that they are accessible.
Change-Id: Ibd788dce432601c6a9f7e6f13eab31f28dcb8550
Diffstat (limited to 'compiler/utils/mips64/assembler_mips64.h')
| -rw-r--r-- | compiler/utils/mips64/assembler_mips64.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/compiler/utils/mips64/assembler_mips64.h b/compiler/utils/mips64/assembler_mips64.h index a120abb238..c170313728 100644 --- a/compiler/utils/mips64/assembler_mips64.h +++ b/compiler/utils/mips64/assembler_mips64.h @@ -240,7 +240,10 @@ class Mips64Assembler FINAL : public Assembler { void Addiu32(GpuRegister rt, GpuRegister rs, int32_t value, GpuRegister rtmp = AT); void Daddiu64(GpuRegister rt, GpuRegister rs, int64_t value, GpuRegister rtmp = AT); // MIPS64 - void Bind(Label* label); // R6 + void Bind(Label* label) OVERRIDE; // R6 + void Jump(Label* label) OVERRIDE { + B(label); + } void B(Label* label); // R6 void Jalr(Label* label, GpuRegister indirect_reg = RA); // R6 // TODO: implement common for R6 and non-R6 interface for conditional branches? |